JPH1012166A - Electric field emission image display device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an electric field emission image display device capable of appropriately controlling electron emission quantity from a cold cathode even if an interval between the cold cathode and a gate electrode is distorted by providing a control electrode whose top and back is pinched between an n-type semiconductor transmission part having the cold cathode and the gate electrode by means of an insulation layer. SOLUTION: A negative voltage is applied from a power source 15 to an n-type semiconductor transmission portion 2, a positive voltage is applied from a power source 18 to an anode 11, and when a positive voltage is applied from the power source 18 to an electrode 8, an electron 9 is emitted from a tip end part of a cold cathode 3. The electron 9 is accelerated by an anode electric field of the anode 11 and collides with a phosphor 10, to emit the phosphor 10. At this time, when a negative voltage is applied to a control electrode by means of a power source 16, a air depletion layer 6 is formed at a part of the n-type semiconductor transmission portion 2, and a current path 14 to the cold cathode 3 is narrowed. Thus, even if an interval between the cold cathode 3 and the gate electrode 8 is changed, an electric field emission image display device capable of controlling electron emission quantity from the cooling cathode 3 is obtained by changing a voltage applied to the control electrode 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field emission type image display device and a method of manufacturing the same, and more particularly to a field emission type image display device in which a plurality of minute cold cathodes are used as an emission source and a method of manufacturing the same. .

[0002]

2. Description of the Related Art In recent years, a field emission type image display device (hereinafter abbreviated as FED) has been developed as an image display device, and US Pat. No. 5,138,237 and US Pat.
No. 87 and the like.

The FED described in US Pat. No. 5,138,237
(First Conventional Example) will be described with reference to FIG.

FIG. 6 is a sectional view showing a main part of a first conventional example of an FED. In FIG. 6, reference numeral 21 denotes a p-type semiconductor substrate;
Is a cold cathode, 23 is an insulating layer, 24 is a conductive layer, 25 is a depletion layer, 26 is an anode, 27 is an electron, 28 is an electron emission surface, 29
Is a cold cathode side surface, and 30, 31, and 32 are power supplies.

[0005] As shown in FIG.
A cylindrical cold cathode 22 formed by diffusing other elements into diamond is formed at the center of the upper surface of a p-type semiconductor substrate 21, and an insulating layer 23 and a conductive layer 2 are formed around the cold cathode 22.
4 are sequentially stacked so as to be in contact with the cold cathode side surface 29. The upper surface of the conductive layer 24 is formed so as to have substantially the same height as the electron emission surface 28 of the cold cathode 22. Anode 26
Are disposed above the cold cathode 22 while being insulated from the p-type semiconductor substrate 21, the cold cathode 22, and the conductive layer 24. A phosphor (not shown) is provided on the surface of the anode 26 on the cold cathode 22 side. Are formed. The p-type semiconductor substrate 21, the conductive layer 24, and the anode 26 are connected to power sources 30, 31, and 32, respectively.
It is connected to the.

In such a configuration, when a negative voltage is applied to the p-type semiconductor substrate 21 and the conductive layer 24 from the power supplies 30 and 31 and a positive high voltage is applied to the anode 26 from the power supply 32, The electrons 27 are emitted from the electron emission surface 28 of the cold cathode 22 by the high applied voltage, and collide with the phosphor formed on the anode 26, so that the phosphor emits light. At this time, due to the negative voltage applied to the conductive layer 24, a depletion layer 25 is formed in a part of the cold cathode side surface 29 which is in contact with the conductive layer 24.
Is formed. The depletion layer 25 is a portion where the amount of conduction electrons generated in the cold cathode 22 is small. By controlling the voltage applied to the power supply 31, the amount of electrons 27 emitted from the cold cathode 22 can be controlled.

Next, an FED (second conventional example) described in US Pat. No. 3,970,887 will be described with reference to FIG.

FIG. 7 is a sectional view of a main part of a second conventional example of the FED. In FIG. 7, reference numeral 33 denotes a p-type semiconductor substrate;
Is an n-type semiconductor conduction part, 35 is a cold cathode, 36 is an insulating layer, 3
7 is a gate electrode, 38 is a protective layer, 39 is an anode, 40 is electrons, and 41, 42 and 43 are power supplies.

As shown in FIG. 7, the FED of the second prior art example
Indicates that the n-type semiconductor conductive portion 3 is
4 are formed, and a part of the n-type semiconductor conductive portion 34 is a conical cold cathode 35 having a sharp tip. On the upper surface of the p-type semiconductor substrate 33, an insulating layer 36, a gate electrode 37, and a protective layer 38 which are not in contact with the cold cathode 35 are sequentially laminated. The anode 39 is composed of the p-type semiconductor substrate 33 and the cold cathode 3
5. The gate electrode 37 is insulated from the cold cathode 35
And a phosphor (not shown) is formed on the surface of the anode 39 on the cold cathode 35 side. Also, n
The semiconductor conductive portion 34, the gate electrode 37, and the anode 39 are connected to power supplies 41, 42, and 43, respectively.

In such a configuration, the gate electrode 3
7. When a positive voltage is applied to the anode 39 by the power supplies 42 and 43 and a negative voltage is applied to the n-type semiconductor conductive part 34 from the power supply 41, electrons are emitted from the cold cathode 35 by the voltage of the gate electrode 37. After being accelerated by the voltage of the anode 39, the phosphor collides with the phosphor formed on the anode 39 to emit light.

[0011]

However, the above-mentioned conventional FED has the following problems.

(1) In the FED of the first conventional example, since the cold cathode and the conductive layer are arranged in a plane at substantially the same height,
An anode electric field is similarly applied to the cold cathode and the conductive layer from the anode. Therefore, in order to selectively emit electrons only from the electron emission surface of the cold cathode, the anode electric field generated by applying a voltage to the anode has a threshold electric field for electron emission from the cold cathode and the anode electric field from the conductive layer. The voltage applied to the anode must be controlled so as to be in the middle of the threshold electric field with respect to electron emission. That is, it is necessary to sufficiently control the voltage applied to the anode and the resulting anode electric field so that no electrons are emitted from the conductive layer. However, it is extremely difficult to easily perform these controls.

(2) In the FED of the second conventional example, the voltage to be applied to the gate electrode greatly changes only by a slight difference between the gate electrode and the cold cathode, and the same voltage is applied to the gate electrode. Also, no electrons are emitted from the cold cathode,
On the contrary, there is a problem that a large amount of electrons are emitted and the cold cathode is blown. In order to solve this problem, a method of installing a high-resistance film under the cold cathode has been considered.
When a cold cathode is manufactured by etching the surface of the substrate, such a high-resistance film cannot be provided. Therefore, it is required that the amount of electron emission from the cold cathode can be easily and sufficiently controlled with respect to the variation in the interval between the cold cathode and the gate electrode.

The present invention has been made to solve the above-mentioned conventional problems, and is capable of easily and sufficiently controlling the amount of electrons emitted from the cold cathode even when the distance between the cold cathode and the gate electrode varies. Field image display device that can easily and sufficiently control the amount of electrons emitted from the cold cathode even when the distance between the cold cathode and the gate electrode varies. It is an object of the present invention to provide a method for manufacturing a field emission image display device.

[0015]

In order to solve the above-mentioned problems, a field emission display according to the present invention comprises a p-type semiconductor substrate, an n-type semiconductor conductive portion formed in the p-type semiconductor substrate, and an n-type semiconductor substrate. A needle-shaped cold cathode formed on a portion of the type semiconductor conductive portion, a second insulating layer formed on the p-type semiconductor substrate and the n-type semiconductor conductive portion, and a control electrode formed on the second insulating layer. A first insulating layer formed on the control electrode, a gate electrode formed on the first insulating layer, a power supply for applying a voltage to each of the control electrode, the n-type semiconductor conductive portion, and the gate electrode;
It comprises the structure provided with.

With this configuration, it is possible to provide a field emission type image display device which can easily and sufficiently control the amount of electrons emitted from the cold cathode even when the distance between the cold cathode and the gate electrode varies. Becomes

According to the method of manufacturing a field emission type image display device of the present invention, there is provided a conductive part forming step of forming an n-type semiconductor conductive part in a p-type semiconductor substrate; A cold cathode forming step of forming a cold cathode, a second insulating layer forming step of forming a second insulating layer on a p-type semiconductor substrate and an n-type semiconductor conductive portion, and a control of forming a control electrode on the second insulating layer It has a configuration including an electrode forming step, a first insulating layer forming step of forming a first insulating layer on the control electrode, and a gate electrode forming step of forming a gate electrode on the first insulating layer.

With this configuration, even when the distance between the cold cathode and the gate electrode varies, the field emission type image display device that can easily and sufficiently control the amount of electrons emitted from the cold cathode can be easily manufactured. It is possible to provide a method for manufacturing an emission type image display device.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a p-type semiconductor substrate, an n-type semiconductor conductive portion formed in the p-type semiconductor substrate, and a portion formed in the n-type semiconductor conductive portion. Needle-shaped cold cathode, a second insulating layer formed on the p-type semiconductor substrate and the n-type semiconductor conductive portion, a control electrode formed on the second insulating layer, and a second electrode formed on the control electrode. A first insulating layer; a gate electrode formed on the first insulating layer; and a power supply for applying a voltage to each of the control electrode, the n-type semiconductor conductive portion, and the gate electrode. ,
Even when the distance between the cold cathode and the gate electrode varies,
This has the effect that the amount of electrons emitted from the cold cathode can be easily and sufficiently controlled.

According to a second aspect of the present invention, in the first aspect, a spacer formed on the gate electrode, a glass substrate provided on the spacer,
An anode formed on the lower surface of the glass substrate and a phosphor formed on the anode are provided, and electrons emitted from the cold cathode collide with the phosphor formed on the anode. This causes the phosphor to emit light.

According to a third aspect of the present invention, there is provided a conductive part forming step of forming an n-type semiconductor conductive part in a p-type semiconductor substrate, and forming a needle-like cold cathode in a part of the n-type semiconductor conductive part. A cold cathode forming step, a second insulating layer forming step of forming a second insulating layer on the p-type semiconductor substrate and the n-type semiconductor conductive portion, and a control electrode forming step of forming a control electrode on the second insulating layer. A first insulating layer forming step of forming a first insulating layer on the control electrode; and a gate electrode forming step of forming a gate electrode on the first insulating layer. Even in the case where the distance between the gate electrodes varies, the field emission type image display device capable of easily and sufficiently controlling the amount of electrons emitted from the cold cathode can be easily manufactured.

According to a fourth aspect of the present invention, in the third aspect of the present invention, there is provided a spacer forming step of forming a spacer on the gate electrode formed in the gate electrode forming step, and an anode on the spacer. Disposing a glass substrate provided with a phosphor and evacuating a glass substrate between the p-type semiconductor substrate and the glass substrate. Has the effect that electrons emitted from the cold cathode collide with each other to cause the phosphor to emit light.

According to a fifth aspect of the present invention, there is provided the invention as set forth in any one of the third and fourth aspects, wherein
In both the insulating layer forming step and the control electrode forming step, the second insulating layer and the control electrode are formed by oblique vapor deposition, and the oblique deposition angle of the second insulating layer with respect to the p-type semiconductor substrate surface is determined by the oblique vapor deposition angle of the control electrode. It has an effect that the distance between the control electrode and the cold cathode can be made larger than the distance between the second insulating layer and the cold cathode.

According to a sixth aspect of the present invention, there is provided the second aspect of the present invention, wherein the second aspect is the second aspect.
The oblique deposition angle of the insulating layer is 30 ± 5 degrees, the oblique deposition angle of the control electrode is 45 ± 5 degrees, and the insulating property between the control electrode or the second insulating layer and the cold cathode is either Also has the effect of improving.

As the above-described p-type semiconductor substrate and n-type semiconductor conductive portion, a silicon semiconductor, a diamond semiconductor, or the like is used.

As the first insulating layer and the second insulating layer, silicon oxide, aluminum oxide, silicon nitride or the like is used.

Further, as the control electrode and the gate electrode,
Niobium, titanium, nickel, aluminum, copper, gold and the like are used.

A DC power supply or the like is used as the power supply. Alumina, silica, or the like is used as the spacer.

As the anode, niobium, titanium, nickel, aluminum, copper, gold, ITO or the like is used.

As the phosphor, ZnO: Zn, Z
nS: Mn, ZnS: [Zn] + In ₂ O ₃ , ZnS:
Cu, Al + In ₂ O ₃ , ZnS: Au, Al + In ₂
O ₃ , (Zn _0.9 Cd _0.1 ) S: Au, Al + In ₂ O ₃
, (Zn _0.8 Cd _0.2 ) S: Au, Al + In ₂ O
₃ , (Zn _0.3 Cd _0.7 ) S: Ag, Cl + In ₂
O ₃ , (Zn _0.2 Cd _0.8 ) S: Ag, Cl + In ₂ O ₃
Are used.

Hereinafter, a specific example of the embodiment of the present invention will be described. (Embodiment 1) FIG. 1 is a sectional view of a main part of a field emission type image display device according to an embodiment of the present invention, and FIG. 2 is a p-type semiconductor of the field emission type image display device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a main part showing a peripheral part of a substrate.

1 and 2, 1 is a p-type semiconductor substrate, 2 is an n-type semiconductor conduction part, 3 is a cold cathode, 4 is a first insulating layer, 5 is a control electrode, 6 is a depletion layer, and 7 is a depletion layer. 2 insulating layer, 8 is a gate electrode, 9 is an electron, 10 is a phosphor, 11 is an anode, 1
2 is a glass substrate, 13 is a spacer, 14 is a current path, 1
Reference numerals 5, 16, 17, and 18 are power supplies.

As shown in FIG. 1, in the field emission type image display device according to the first embodiment, an n-type semiconductor conductive portion 2 is formed in a part of a p-type semiconductor substrate 1 and the n-type semiconductor conductive portion 2 is formed. Is a needle-shaped or a conical cold cathode 3 with a sharp point. On the upper surfaces of the p-type semiconductor substrate 1 and the n-type semiconductor conductive portion 2, a second insulating layer 7, a control electrode 5, a first insulating layer 4, and a gate electrode 8, which are not in contact with the cold cathode 3, are sequentially stacked. . Spacer 1 which is an insulator is formed on gate electrode 8.
3, a glass substrate 12 is provided, and an anode 11 is formed on the lower surface of the glass substrate 12;
A phosphor 10 is disposed at a position facing the cold cathode 3 on 1. The n-type semiconductor conductive part 2, the control electrode 5, the gate electrode 8, and the anode 11 are connected to power sources 15, 16, 1
7 and 18 are connected.

Hereinafter, the operation of the field emission type image display device according to the present embodiment having the above configuration will be described. A negative voltage is applied to the n-type semiconductor conduction section 2 by the power supply 15, and a positive voltage of 200 to 500 V is applied to the anode 11 by the power supply 18. Next, the power source 17 supplies the gate electrode 8 with 20 to
When a positive voltage of 100 V is applied, electrons 9 are emitted from the tip of the cold cathode 3. The emitted electrons 9 are accelerated by the anode electric field of the anode 11 and collide with the phosphor 10 so that the phosphor 10 emits light.

In the above operation, when a negative voltage of 0 to -100 V is applied to the control electrode 5 by the power supply 16, a depletion layer 6 is formed in a part of the n-type semiconductor conductive portion 2, and as shown in FIG. As described above, the current path 14 to the cold cathode 3 becomes narrow. Along with this, the electrons 9 hardly flow to the cold cathode 3, and as a result, the amount of electrons emitted from the cold cathode 3 decreases. The amount of electron emission depends on the value of the negative voltage applied to the control electrode 5, and the amount of electron emission from the cold cathode 3 can be controlled by changing the voltage applied to the control electrode 5.

As described above, according to the first embodiment, p
A control electrode 5 for controlling the amount of electrons emitted from the cold cathode 3 between the semiconductor substrate 1 and the gate electrode 8, and the distance between the cold cathode 3 and the gate electrode 8 is controlled by a voltage applied to the control electrode 5. Even when the temperature varies, the amount of electrons emitted from the cold cathode 3 can be easily and sufficiently controlled.

The first embodiment may have a structure in which a plurality of cold cathodes 3 are formed on a p-type semiconductor substrate 1 as shown in FIG.

(Embodiment 2) FIGS. 3 and 4 show a method of manufacturing a field emission type image display device according to Embodiment 2 of the present invention. FIG. 3 (b) to 3 are cross-sectional views of main parts of the obtained intermediate.
4F is a cross-sectional view of a main part of an intermediate obtained in a cold cathode forming step, FIG. 4A is a cross-sectional view of a main part of an intermediate obtained in a control electrode forming step, and FIG. 4B is a first insulating layer. Main part sectional view of the intermediate product obtained in the forming step, FIG.
(E) is a sectional view of a main part of an intermediate obtained in the gate electrode forming step.

FIGS. 3A to 3F and FIGS.
In (e), 19 is an oxide film, 20 is a resist layer, and is a p-type semiconductor substrate 1, an n-type semiconductor conduction part 2, a cold cathode 3, a first insulating layer 4, a control electrode 5, a second insulating layer 7, Since the gate electrode 8 is the same as in the first embodiment, the same reference numerals are given and the description is omitted.

Next, FIGS. 3A to 3F and FIG.
A method of manufacturing the field emission image display device according to the second embodiment will be described with reference to FIGS.

First, as a conductive portion forming step, FIG.
As shown in FIG. 2, a p-type semiconductor substrate 1 such as a silicon semiconductor having a crystal orientation plane 100 as an upper surface is formed on a p-type semiconductor substrate 1 by a diffusion method and a photolithography technique.
To form

Next, as a cold cathode forming step, the p-type semiconductor substrate 1 is heat-treated at about 1200 ° C. for about 20 hours, so that the oxide film 1 is formed on the surfaces of the p-type semiconductor substrate 1 and the n-type semiconductor conductive portion 2.
After the formation of the oxide film 9, the oxide film 19 is formed as shown in FIG.
A resist layer 20 is applied thereon. As shown in FIG. 3 (c), the resist layer 20 is removed by a photolithography method except for a portion above the central portion of the n-type semiconductor conductive portion 2 except for the portion above the buffer layer. Then, the oxide film 19 is etched to remove the oxide film 19 except for the lower portion of the resist layer 20 as shown in FIG. 3D, and further, the resist layer 20 is removed to obtain a circular shape as shown in FIG. Oxide film 19 is formed. Thereafter, the outermost surfaces of the p-type semiconductor substrate 1 and the n-type semiconductor conductive portion 2 are pretreated by dipping in buffered hydrofluoric acid for several seconds, and immediately using the oxide film 19 as a mask with an anisotropic etching solution such as KOH. The p-type semiconductor substrate 1 and the n-type semiconductor conductive part 2 are etched. As a result, the lower portion of the oxide film 19 is side-etched to form the substantially acicular or substantially conical cold cathode 3 as shown in FIG.

In the etching of the p-type semiconductor substrate 1 and the n-type semiconductor conductive portion 2, the oxide film 19 is
So that it does not desorb from

Next, as a second insulating layer forming step, a second layer made of silicon oxide or the like is formed on the intermediate p-type semiconductor substrate 1 and the n-type semiconductor conductive portion 2 obtained in the cold cathode forming step.
The insulating layer 7 is formed by an evaporation method.

Next, as a control electrode forming step, on the intermediate second insulating layer 7 obtained in the second insulating layer forming step,
A control electrode 5 made of niobium or the like is formed by a vapor deposition method,
An intermediate as shown in FIG. 4 (a) is obtained.

In the control electrode forming step, the control electrode 5
Is formed so as not to contact the cold cathode 3 and the n-type semiconductor conductive portion 2.

Next, as a first insulating layer forming step, a first insulating layer 4 made of silicon oxide or the like is formed on the intermediate control electrode 5 obtained in the control electrode forming step by sputtering or vapor deposition. Then, an intermediate as shown in FIG. 4B is obtained.

In this step, oblique deposition is not performed so that the first insulating layer 4 is not formed below the oxide film 19.

Next, as a gate electrode forming step, as shown in FIG. 4C, a gate electrode 8 made of niobium or the like is formed on the intermediate first insulating layer 4 obtained in the first insulating layer forming step. Is formed and patterned into a predetermined shape by photolithography to obtain an intermediate as shown in FIG. 4D. Further, the side portion of the cold cathode 3 is oxidized by subjecting the intermediate to a heat treatment at about 950 ° C. for about 16 hours. Thereafter, the laminate on the upper part of the cold cathode 3 is completely removed by chemical wet etching with buffered hydrofluoric acid, and the upper part of the cold cathode 3 is shaped like a needle or a needle with a sharp tip or a cone with a sharp tip. Fig. 4 (e)
An intermediate as shown in (1) is prepared.

Next, as a spacer forming step, a spacer 13 made of alumina, silica or the like is formed on the intermediate gate electrode 8 obtained in the gate electrode forming step.

Further, as the glass substrate disposing step, the intermediate spacer 13 obtained in the spacer forming step is used.
A glass substrate 1 on which an anode 11 and a phosphor are sequentially laminated
2 is arranged so that the phosphor faces the cold cathode 3, and the space between the p-type semiconductor substrate 1 and the glass substrate 12 is sealed, and the inside thereof is brought into a vacuum state of about 10 ^-8 Torr.

As described above, according to the second embodiment, p
A control electrode 5 is provided between the mold semiconductor substrate 1 and the gate electrode 8 so that the amount of electrons emitted from the cold cathode 3 can be easily and sufficiently controlled even when the distance between the cold cathode 3 and the gate electrode 8 varies. It is possible to easily manufacture a possible field emission image display device.

In the second embodiment, the case where a single cold cathode 3 is formed on the p-type semiconductor substrate 1 has been described as an example. However, the p-type semiconductor substrate shown in FIG. A field emission type image display device in which a plurality of cold cathodes 3 are formed in one can be manufactured by a method similar to that of the third embodiment.

(Embodiment 3) FIG. 5 is a view showing the essentials of an intermediate obtained by a second insulating layer forming step and a control electrode forming step in the method for manufacturing a field emission type image display device according to Embodiment 3 of the present invention. It is a fragmentary sectional view.

In FIG. 5, a p-type semiconductor substrate 1, an n-type semiconductor conductive part 2, a cold cathode 3, a control electrode 5, a second insulating layer 7,
Since the oxide film 19 is the same as in the second embodiment,
The same reference numerals are given and the description is omitted.

The method of manufacturing the field emission type image display device according to the third embodiment is different from that of the second embodiment in that
In the second insulating layer forming step and the control electrode forming step, the second insulating layer and the control electrode are formed by oblique deposition.

Except for these steps, the method of manufacturing the field emission type image display according to the third embodiment is the same as that of the second embodiment.

Hereinafter, the step of forming the second insulating layer and the step of forming the control electrode according to the third embodiment will be described in more detail.

First, in the second insulating layer forming step, the intermediate p-type semiconductor substrates 1 and n obtained in the cold cathode forming step are formed.
A second insulating layer 7 made of silicon oxide or the like is formed on the mold semiconductor conductive portion 2 by an oblique deposition method.

In the case of oblique deposition, the p-type semiconductor substrate 1
Is formed while rotating in a vapor deposition apparatus.
As shown in (2), the second insulating layer is formed up to the lower portion of the oxide film 19.

Next, as a control electrode forming step, the intermediate second insulating layer 7 obtained in the second insulating layer forming step is
A control electrode 5 made of niobium or the like is formed by oblique deposition while rotating the p-type semiconductor substrate 1 in the same manner as in the second insulating layer forming step. As a result, the control electrode 5 is formed up to the lower portion of the oxide film 19 as shown in FIG.
Is not deposited to the inner side than the second insulating layer 7, the distance between the control electrode 5 and the cold cathode 3 is larger than the distance between the second insulating layer 7 and the cold cathode 3. In order to improve the insulation between the control electrode 5 and the cold cathode 3, it is preferable that the upper control electrode 5 is farther from the cold cathode 3 than the lower second insulating layer 7.

When the control electrode 5 and the second insulating layer 7 are obliquely deposited, the oblique deposition angle a of the second insulating layer 7 with respect to the surface of the p-type semiconductor substrate 1 shown in FIG. If the angle is smaller than the oblique deposition angle b, the distance between the control electrode 5 and the cold cathode 3 can be surely made larger than the distance between the second insulating layer 7 and the cold cathode 3. Further, by controlling these angles, it is possible to more accurately set the distance between the control electrode 5 and the cold cathode 3 and the distance between the second insulating layer 7 and the cold cathode 3.

For example, the oblique deposition angle a of the second insulating layer 7 is set at 30 ± 5 degrees, and the oblique deposition angle b of the control electrode 5 is set at 45 ± 5 degrees.
By setting the angle to 5 degrees, the position of the inner peripheral portion of the control electrode 5 can be set to be 0.3 μm outside the inner peripheral portion of the second insulating layer 7.

As described above, according to the third embodiment, both the second insulating layer 7 and the control electrode 5 are obliquely deposited, and the oblique deposition angle of the second insulating layer 7 is made smaller than that of the control electrode 5. As a result, the distance between the control electrode 5 and the cold cathode 3
The distance between the insulating layer 7 and the cold cathode 3 can be larger than the distance between the insulating layer 7 and the cold cathode 3, and the insulating property between the control electrode 5 or the second insulating layer 7 and the cold cathode 3 can be improved by controlling the oblique deposition angle. It becomes possible.

[0065]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A p-type silicon semiconductor substrate having a crystal orientation plane 100 as an upper surface is formed on a p-type silicon semiconductor substrate by a diffusion method and a photolithography technique to form a line-shaped n having a width of about 10 μm and a depth of about 5 μm.
A type semiconductor conductive part was formed. This p-type silicon semiconductor substrate was heat-treated at about 1200 ° C. for about 20 hours to form a silicon oxide film of about 1 μm on the surface of the p-type silicon semiconductor substrate, and then a resist layer was formed on the silicon oxide film.

Next, after removing only the resist layer having a diameter of about 3 μm corresponding to the upper portion of the center of the n-type semiconductor conductive portion by photolithography, the other resist layer is removed.
The silicon oxide film is etched with buffered hydrofluoric acid or the like to remove the silicon oxide film other than the lower part of the resist layer, and further the resist layer is removed. The diameter is about 3 μm and the thickness is about 1 μm at the center on the n-type semiconductor conductive part. Was formed.

Next, the outermost surfaces of the p-type silicon semiconductor substrate and the n-type semiconductor conductive portion are pretreated by dipping in buffered hydrofluoric acid for several seconds, and the silicon oxide film is immediately formed with an anisotropic etching solution such as KOH. As a mask, the p-type silicon semiconductor substrate and the n-type semiconductor conductive portion were etched for 9 minutes to form a substantially needle-shaped cold cathode at the center of the n-type semiconductor conductive portion.

Next, a 0.3 μm-thick second insulating layer made of silicon oxide was formed on the p-type silicon semiconductor substrate and the n-type semiconductor conductive portion around the cold cathode by an oblique evaporation method at an oblique evaporation angle of 30 ± 5 degrees. After forming the film, a control electrode made of niobium and having a thickness of 0.3 μm was formed on the second insulating layer at an oblique evaporation angle of 45 ±
The film was formed at 5 degrees by an oblique evaporation method. At this time, neither the second insulating layer nor the control electrode was in contact with the cold cathode.

Next, a 1 μm-thick first insulating layer made of silicon oxide was formed on the control electrode by vapor deposition.
After forming a 0.3 μm thick gate electrode made of niobium on the first insulating layer, a heat treatment was performed at about 950 ° C. for about 16 hours to oxidize the cold cathode side. Further, the laminate formed on the upper part of the cold cathode was removed entirely by chemical wet etching with buffered hydrofluoric acid, and the upper part of the cold cathode was formed into a needle shape.

Next, a 200 μm-thick spacer made of alumina was formed on the gate electrode, and a glass substrate in which a linear anode made of ITO and a phosphor made of ZnO: Zn were sequentially laminated on the spacer was used. The phosphor is disposed so as to face the cold cathode, the space between the p-type silicon semiconductor substrate and the glass substrate is sealed, and the inside thereof is evacuated to about 10 ⁻⁸ Torr to form the field emission type image display of the present invention. The device was made.

The field emission type image display devices obtained by the above method were classified into three types: those having a displacement of the tip of the cold cathode of 0.1 μm or less, 0.2 μm, and 0.3 μm. Note that the displacement in this example is the distance between the tip of the cold cathode and the pseudo center of the inner periphery of the gate electrode, and was determined by microscopic observation.

With respect to each field emission type image display device, 0 V was applied to the n-type semiconductor conduction portion, 400 V was applied to the anode,
An operation test was performed in which a voltage of 100 V was applied to the gate electrode to cause the phosphor to emit light. At the time of this operation test, the case where a voltage of −50 V was applied to the control electrode was defined as Examples 1 to 3, and the case where no voltage was applied to the control electrode was defined as Comparative Examples 1 to 3.
The operation rate at each operation test was determined, and the results are shown in (Table 1).

The operating rate is the ratio of the number of cold cathodes, which were operated during the operation test and were not damaged after the operation test, to the total number of the cold cathodes among the plurality of cold cathodes formed on the p-type silicon semiconductor substrate. This was determined by the number of cold cathodes that were not damaged by microscopic observation.

[0074]

[Table 1]

As is evident from Table 1, in Comparative Examples 1 to 3 in which no voltage is applied to the control electrode, the operation rate decreases significantly with an increase in the amount of displacement. However,
In Examples 1 to 3, 0.3 μm having the largest displacement amount was used.
In this case, the operation rate was 80%, and it was clarified that a high operation rate could be maintained even when the distance between the cold cathode and the gate electrode varied by controlling the amount of electrons emitted from the cold cathode by the control electrode. .

[0076]

As described above, according to the field emission type image display device of the present invention, the amount of emitted electrons from the cold cathode can be easily and sufficiently controlled even when the distance between the cold cathode and the gate electrode varies. Therefore, an excellent effect of preventing a decrease in screen brightness and a poor contrast due to generation of a non-light emitting portion of the phosphor due to a short circuit between the cold cathode and the gate electrode can be obtained. In addition, since the short-circuit between the cold cathode and the gate electrode can be prevented by easily and sufficiently controlling the amount of electrons emitted from the cold cathode, the durability and reliability in long-term use can be improved. The effect is obtained.

Further, according to the method of manufacturing a field emission type image display device of the present invention, the amount of electrons emitted from the cold cathode can be easily and sufficiently controlled even when the distance between the cold cathode and the gate electrode varies. Field-emission image display device having a control electrode capable of performing the operation between the p-type semiconductor substrate and the gate electrode can be easily manufactured, so that the field-emission image display device has no reduction in screen luminance or poor contrast. An excellent effect that a display device can be manufactured at low cost is obtained. Further, the distance between the control electrode and the cold cathode can be made larger than the distance between the second insulating layer and the cold cathode, and the distance between the control electrode and the second insulating layer can be controlled by setting an oblique deposition angle. Since it is possible to improve the insulating properties with the cold cathode, it is possible to obtain an excellent effect that a short circuit between the control electrode and the cold cathode can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a field emission display according to an embodiment of the present invention;

FIG. 2 is an essential part cross-sectional view showing a peripheral portion of a p-type semiconductor substrate of the field emission image display device according to one embodiment of the present invention;

3A is a cross-sectional view of a main part of an intermediate obtained in a conductive part forming step. FIG. 3B is a cross-sectional view of a main part of an intermediate obtained in a cold cathode forming step. (D) Principal sectional view of an intermediate obtained in the cold cathode forming step (e) Principal sectional view of the intermediate obtained in the cold cathode forming step (f) Intermediate obtained in the cold cathode forming step Cross section of main part of object

FIG. 4A is a cross-sectional view of a main part of an intermediate obtained in a control electrode forming step. FIG. 4B is a main part cross-sectional view of an intermediate obtained in a first insulating layer forming step. (D) Principal cross section of intermediate obtained in gate electrode forming step (e) Principal cross section of intermediate obtained in gate electrode forming step

FIG. 5 is a cross-sectional view of a main part of an intermediate obtained by a second insulating layer forming step and a control electrode forming step in the method of manufacturing the field emission image display device according to one embodiment of the present invention.

FIG. 6 is a sectional view of a main part showing a first conventional example of an FED.

FIG. 7 is a sectional view of a main part showing a second conventional example of an FED.

[Explanation of symbols]

1, 21, 33 p-type semiconductor substrate 2, 34 n-type semiconductor conductive part 3, 22, 35 cold cathode 4 first insulating layer 5 control electrode 6, 25 depletion layer 7 second insulating layer 8, 37 gate electrode 9, 27 , 40 electrons 10 phosphor 11, 26, 39 anode 12 glass substrate 13 spacer 14 current path 15, 16, 17, 18, 30, 31, 32, 41, 4,
2, 43 power supply 19 oxide film 20 resist layer 23, 36 insulating layer 24 conductive layer 28 electron emission surface 29 cold cathode side surface 38 protective layer

Claims (6)

[Claims] A p-type semiconductor substrate; an n-type semiconductor conductive portion formed in the p-type semiconductor substrate; a needle-shaped cold cathode formed in a part of the n-type semiconductor conductive portion; A second insulating layer formed on the semiconductor substrate and the n-type semiconductor conductive portion; a control electrode formed on the second insulating layer; a first insulating layer formed on the control electrode; A gate electrode formed on one insulating layer, the control electrode and the n
A field emission type image display device comprising: a semiconductor conductive portion; and a power supply for applying a voltage to each of the gate electrodes. 2. A spacer formed on the gate electrode, a glass substrate provided on the spacer, an anode formed on a lower surface of the glass substrate, and a phosphor formed on the anode. The field emission type image display device according to claim 1, further comprising: 3. A conductive part forming step of forming an n-type semiconductor conductive part in a p-type semiconductor substrate; a cold cathode forming step of forming a needle-shaped cold cathode in a part of the n-type semiconductor conductive part;
A second insulating layer forming step of forming a second insulating layer on the type semiconductor substrate and the n-type semiconductor conductive portion; a control electrode forming step of forming a control electrode on the second insulating layer; A method for manufacturing a field emission type image display device, comprising: a first insulating layer forming step of forming a first insulating layer; and a gate electrode forming step of forming a gate electrode on the first insulating layer. . 4. A spacer forming step of forming a spacer on the gate electrode formed in the gate electrode forming step, a glass substrate provided with an anode and a phosphor on the spacer, and the p-type semiconductor 4. The method according to claim 3, further comprising a step of arranging a glass substrate to evacuate a space between the substrate and the glass substrate. 5. In the second insulating layer forming step and the control electrode forming step, both the second insulating layer and the control electrode are formed by oblique vapor deposition, and the second insulating layer is inclined with respect to the substrate surface. 5. The method according to claim 3, wherein a deposition angle is smaller than the oblique deposition angle of the control electrode. 6. The oblique deposition angle of the second insulating layer is 30.
± 5 degrees, and the oblique deposition angle of the control electrode is 45
6. The method according to claim 3, wherein the angle is ± 5 degrees.