JPH04132972A - Circuit for testing lsi - Google Patents

Abstract

PURPOSE:To improve a defect detection rate and reduce the number of data patterns by switching (n) pieces of memory elements to a set or a reset state based on an output signal from a data memory means and an input signal to an external input terminal for testing. CONSTITUTION:An LSI houses a data memory means 2 applying output signals to FF11 to 1n, and is provided with common external input terminals 31 to 3n and an external input terminal 4 for testing. An output terminal of the means 2 and the terminal 4 are connected to switching circuits 51 to 5n. Based on an output signal from the means 2 and an input signal input to the terminal 4, the circuits 51 to 5n switch (n) pieces of memory elements, that is, FF11 to 1n to a set state or a reset state. Thus the means 2 housed in the LSI and the memory elements that store binary states, that is, FF11 to FF1n can be directly controlled irrespective of a program stored in the LSI, so that a defect detection rate of the LSI is improved when the number of test data patterns are equal, whereas the number of the patterns can be reduced when the defect detection rates are equal.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is directed to an LSI that is used when executing a test program for selecting defective LSI products during LSI manufacturing.
This relates to a dedicated LSI test circuit provided within the SI.

[Prior Art] In order to screen out defective products during LSI manufacturing, it is necessary to run a test program on the completed LSI to test whether it operates as expected. The content of the test program is to apply pattern data, generally called test data, to the input terminals of the LSI, and to confirm that the expected changes appear at the output terminals.

A numerical value indicating whether the operation of the constituent circuits of the LSI has been verified by this test program is expressed as a failure detection rate.

In order to increase this fault detection rate, it is possible to increase the number of patterns in the test data, but since there is generally a limit (upper limit) to the number of patterns, the important issue is how to achieve a high fault detection rate with a small number of patterns. It is. Conventionally, the content of test data is as follows.

There are methods that add a pattern to the LSI under test to simulate the same operation as the actual device, and methods that apply random input data.

[Problems to be Solved by the Invention] The content of conventional test data is such that failures occur in LSIs having sequential circuits made up of storage elements that store a large number of binary states and data storage means that provide signals to these storage elements. It is not easy to increase the detection rate, and there is a problem that the number of patterns increases too much to obtain a high failure detection rate.

An object of the present invention is to increase the failure detection rate of LSI when the number of test data patterns is the same, and to reduce the number of test data patterns when the failure detection rate is the same. Our objective is to provide LSI test circuits.

[Means for Solving the Problem] According to the present invention, there are n (n≧2) storage elements that store a predetermined program and store a binary state, and a signal is applied to these storage elements and arbitrary data can be stored. L with built-in n-bit data storage means that can write
In an LSI test circuit that tests whether or not an SI is a defective product using a test program, one test external input terminal provided for testing the LSI and shared for normal operation and testing of the LSI. and a common external input terminal for supplying data to the data storage means, and an output signal from the data storage means and an input signal input to the external input terminal for testing to control the n storage elements. There is obtained an LSI test circuit characterized in that it is equipped with n switching circuits for switching to a set state or a reset state.

According to one aspect of the present invention, there is obtained the LSI testing circuit, wherein the n storage elements are comprised of flip-flops.

According to one aspect of the present invention, in the LSI test circuit, the switching circuit receives signals from the data storage means and the test external input terminal, and inputs the AND signal of these signals for instructing the flip-flop to set. an AND circuit that receives an inverted signal of the output signal from the AND circuit and an input signal from the test external input terminal, and supplies an AND signal of these to the reset instruction input terminal of the flip-flop; There is obtained an LSI test circuit characterized by having the following.

[Embodiment] Next, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, reference numerals 11 to 1n indicate flip-flops built into the LSI. Also.

The LSI also includes a built-in n-bit data storage means 2. This data storage means 2 can write arbitrary data, and the flip-flops 1, to 1n
gives an output signal to

Common external input terminals 3□ to 3n for writing data into the data storage means 2 are provided on the LSI. These shared external input terminals 3, to 3n are commonly used for normal operation and testing of the LSI.

Furthermore, the LSI is provided with one external input terminal 4 for testing.

The output terminal of the data storage means 2 and the test external input terminal 4 are connected to switching circuits 5, -5o. These n switching circuits 51 to 5o.

Each of the n flip-flops 11 to 1n is switched to a set state or a reset state.

The switching circuits 5□ to 5n include two AND circuits 5a and 5
It has b. The AND circuit 5a is.

It receives the output signal of the data storage means 2 and the input signal from the test external input terminal 4, respectively, and applies an AND signal of these two signals to the set designation input terminals MS of the flip-flops 1□ to 1n. Further, the AND circuit 5b receives an inverted signal of the output signal from the AND circuit 5a and an input signal from the test external input terminal 4, and outputs an AND signal of these two signals to the flip-flop 11.
~1 is applied to the reset instruction input terminal MR.

The switching circuits 5□ to 5n are connected to the data storage means 2 that receives input signals from the shared external input terminals 3 and 3n only when the logic value of the input signal from the test external input terminal 4 is "1". The logic values of the flip-flops 11 to 1n can be switched in the same way as the logic values of . Therefore, among the number of test data patterns required to operate the sequential circuit constructed by the flip-flops 1□-1n and the data storage means 2, only the flip-flops 11-1n
The number of patterns in which the data storage means 2 is switched twice or more is unnecessary for the test and can be omitted.

[Effects of the Invention] The present invention directly controls data storage means built into an LSI and a storage element that stores binary states, such as a flip 70 tube, at the time of testing, regardless of the program stored in the LSI. Therefore, when the number of test data patterns is the same, the failure detection rate of the LSI can be increased, and when the failure detection rate is the same, the number of test data patterns can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1, ~1n pocket means, 3, section input terminal. ...Flip-flop, 2...Data record ~3...
・Shared external input terminal, 4...outer 5□~5o...switching circuit. Figure 1 +31 n

Claims (3)

[Claims] (1) n (n≧2) memory elements that store a predetermined program and store binary states, and n-bit data storage means that can give signals to these elements and write arbitrary data. In an LSI test circuit that tests whether a built-in LSI is a defective product using a test program, there is one test external input terminal provided for testing the LSI, and a terminal for normal operation and testing of the LSI. n common external input terminals for supplying data to the data storage means, and input signals input to the output signal from the data storage means and the external input terminal for testing. 1. An LSI testing circuit comprising n switching circuits for switching a memory element to a set state or a reset state. (2) The LSI testing circuit according to claim 1, wherein the n storage elements are comprised of flip-flops. (3) In the LSI testing circuit according to claim 2, the switching circuit receives signals from the data storage means and the testing external input terminal, and converts these AND signals to the set of flip-flops. An AND circuit applied to an instruction input terminal, an inverted signal of the output signal from this AND circuit, and an input signal from the test external input terminal, and an AND signal of these is applied to the reset instruction input terminal of the flip-flop. 1. An LSI testing circuit characterized by having an AND circuit that gives