JPH04132549U - microprocessor circuit - Google Patents

Abstract

(57) [Summary] (with modifications) [Configuration] A microprocessor 1 with a built-in cache memory, and an interrupt to the microprocessor when it detects that there is no output from this microprocessor to the external bus 2 within a predetermined time. It is equipped with an external bus monitoring circuit 3 that sends out signals. Even when the microprocessor 1 continues to use the internal cache memory and no output is made to the external bus, the external bus monitoring circuit forcibly causes the output to be made to the external bus within a certain period of time. Further, there are a plurality of microprocessors 1, 1', and a comparison circuit 4 detects a mismatch between the outputs of the two, thereby detecting an abnormality. [Effect] Output to the external bus is not interrupted, and existing programs can be reused even for circuits whose operations are related to external bus output.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention is a microphone that uses a microprocessor with built-in cache memory. Regarding microprocessor circuits, especially when two microprocessors are used and synchronized, perform the same operation, and check that the output signals to the external bus on both sides always match. The so-called fully synchronous type 2 improves the operational reliability of microprocessors, etc. by Access and output to external buses as seen in heavy-duty microprocessor circuits relates to microprocessor circuits whose operation depends on

0002

[Conventional technology]

Traditionally, safety has been particularly required for railway signal systems and nuclear reactor control systems among industrial equipment. When using a microprocessor in a field that In order to detect The output of both users can be configured to check each other's output, or both can be configured to work synchronously. Reliability and safety are ensured by checking the match of the output to the external bus using an additional circuit. ing. A conventional example of the latter microprocessor circuit is shown in FIG. Fully synchronous type in Figure 2 The dual-system microprocessor circuit 10 is safe in response to failures in various parts and power outages. It has a so-called fail-safe configuration in which the output from the side is sent out. In other words, two Comparator circuit 4 connected to microprocessor 1, 1' and respective external bus 2, 2' , a relay drive circuit 5 connected to this comparison circuit 4, a subsequent relay 6 and an external Consists of memory and I/O circuits (not shown) connected to buses 2 and 2' . The two microprocessors 1 and 1' operate in the same manner according to the same clock signal CLS. It is configured to perform the same processing at the same time. The comparison circuit 4 is a microprocessor. The data that processor 1 outputs to its external bus 2 and the data that microprocessor 1' outputs to its external bus 2 are It constantly compares the data output to external bus 2' and sets it to "1" or " according to the data. 0" signal is generated and sent to the subsequent relay drive circuit 5, and this output is always The situation is constantly changing. Then, in the relay drive circuit 5, this output changes. The relay 6 is operated when it is considered normal.

0003 However, the microprocessor and other parts failed and two microprocessors were removed. When different data is output to the bus, the comparator circuit 4 detects this and the subsequent relay The signal sent to the drive circuit 5 is fixed at "1" or "0". Corresponds to this Then, the relay drive circuit 5 drops the relay 6. As a result, the contacts of relay 6 The abnormal output is sent to the subsequent device (not shown) through the microprocessor 1, 1'. Such failures will be detected and necessary predetermined measures will be taken. The above-mentioned comparison circuit 4 connects to the external bus 2 output from the microprocessors 1 and 1'. , 2' generates a "1" or "0" signal according to the data, and the final output relay (Normal relay) Since the configuration is to operate 6, under normal conditions, “1” and “0” are in place. It is necessary to occur at a regular frequency. Therefore, for example, even in the operating program, external Considerations have been taken, such as not using the “NOP” command, which does not cause data changes to the bus. It is.

0004 By the way, with the development of microprocessors, effective methods for high-speed processing have been developed in recent years. Microprocessors with built-in cache memory are also available. Chi By the way, here is a comparison of microprocessor access times for various types of memory. For example, for normal local memory it takes 70-150ns, while the VME standard The access time for memory on the bus is 500 to 1200 ns, but internal For cache memory, the speed is increased to 60 ns or less. In addition, micropro Some setsa have two types of built-in cache memory: one for programs and one for data. Some do.

[0005]

[Problem that the idea aims to solve]

By the way, the conventional microprocessor circuit 10 as described above has the above-mentioned capacitor. If you apply a microprocessor with built-in flash memory as is, it will Output may not be made for a long time, causing inconvenience. In other words, in the case of a microprocessor with internal cache memory, the microprocessor Rosetsusa executes processing using the program once loaded into cache memory, and then Access to the external bus is executed while the execution instruction exists in the cache memory. do not. Therefore, a circuit using a microprocessor with cache memory When a loop program is executed on a system or a system, external access occurs frequently. It will not be executed for a while and there will be no output to the external bus. For this reason, the above-mentioned fail It is assumed that “1” and “0” signals do not occur with a certain frequency from the safe comparator circuit 4. Eventually, the subsequent relay 6 was restored, and an abnormal signal was sent out incorrectly. I'm going to go to the middle of the day.

[0006] To deal with this, create a program that does not include any parts that loop for longer than a predetermined time. or create a process to access an external bus during loop processing. Although it is possible to take measures using software such as keeping the In addition to the disadvantage of not being able to repurpose grams, how much should the above prescribed time be set? (varies for each system) and the running time at runtime. It is difficult to create a program while taking relationships into account, and so on. It can hardly be called a strategy. This invention was created in view of the above-mentioned situation, and it is possible to add a simple circuit to the existing circuit. You can use a high-speed microprocessor with built-in cache memory by simply adding We offer a microprocessor circuit that allows existing programs to be reused while The task is to come up with a plan.

[0007]

[Means to solve the problem]

In order to solve the above problems, this invention uses a microprocessor circuit. A microprocessor with built-in cache memory and this microprocessor The microprocessor detects when there is no output to the external bus within a predetermined time. and an external bus monitoring circuit that sends an interrupt signal to the server.

[0008] In addition, in other inventions of the present application, the microprocessor circuit is Multiple microprocessors with built-in cache memory and If there is no output from the processor to any of the external buses within a predetermined time, an external bus monitoring circuit that detects and sends an interrupt signal to the microprocessor; and a comparison circuit that compares the status of the external bus and detects a discrepancy and sends out an abnormal signal. The structure shall be equipped with the following.

[0009]

[Effect]

The external bus monitoring circuit allows the microprocessor to monitor the external bus within a predetermined time. It detects when there is no output and sends an interrupt signal to the microprocessor. microphone The processor uses a predetermined program as the interrupt processing corresponding to this interrupt signal. The system is started and executed, and output is made to the external bus. As a result, programs containing loop programs that are continuously executed inside the cache memory. Executing the program will not have a negative impact on the existing system. This is an existing program This means that the system can be easily repurposed, and unnecessary program development can be avoided. .

0010

【Example】

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of the microprocessor circuit of the present invention. Ru. Note that the same or equivalent parts as in FIG. 2 are indicated with the same figure numbers. The microprocessor circuit 20 of FIG. 1 has two microprocessor circuits similar to the circuit of FIG. Comparator circuit 4 connected to setters 1, 1' and respective external buses 2, 2', Relay drive circuit 5 connected to circuit 4, subsequent relay 6 and external bus 2, 2' It is configured to include a memory and an I/O circuit (not shown) connected to the . these parts The operation of is the same as described above, so it will be omitted.

[0011] In addition to these existing parts, the microprocessor circuit 20 also provides external bus monitoring. It is equipped with a circuit 3. The external bus monitoring circuit 3 is connected to the microprocessors 1 and 1'. Detects if there is no output (no access) to each external bus within a specified time. This is a circuit that sends an interrupt signal INT to the microprocessors 1 and 1' based on the The signals output when microprocessors 1 and 1' access their respective external buses. counters 31 and 31' connected to respective numbers (for example, DSA and DSB), and Count up output when the count number of counters 31, 31' reaches a predetermined value A single interrupt signal generation circuit 3 into which signals (CNTUP, CNTUP') are respectively input. 3, and a count pulse that inputs the count pulse CTP to the counters 31 and 31'. The generator 32 is configured to include a generator 32.

0012 Next, the operation of the microprocessor circuit 20 will be explained. As in conventional circuits, the two microprocessors 1, 1' are clocked by the same clock. The same processing is performed in synchronization according to the signal CLS. The counters 31, 31' are micro The signal output when processors 1 and 1' access the external bus (in the example When DSA, DSB) is input, the count value is reset. Also, count Pulse CTP is constantly counted, and when the count value reaches the set value, it starts counting. The up signal (CNTUP, CNTUP') is sent to the interrupt signal generation circuit 33. The interrupt signal generation circuit 33 generates an interrupt with appropriate pulse width, polarity, level, etc. It creates a read signal INT and connects it to the interrupt terminals 7 and 7' of the two microprocessors 1 and 1'. Send them to each of them. The microprocessors 1 and 1' perform predetermined processing in response to the interrupt. In other words, after executing a program that includes external access processing, the original program is Continue running. Therefore, the microprocessor continues to use internal cache memory. Even if no access is made to the outside, the external bus monitoring circuit 3 is forced to maintain a constant state. The external access will be allowed within the specified time, and under normal conditions, external access may be interrupted. There is no such thing.

[0013] As mentioned above, the comparator circuit 4 is connected to the microprocessor 1 which is connected to the external bus 2. data that the microprocessor 1' outputs to its external bus 2'. and generates a “1” or “0” signal depending on the data and then The signal is sent to the ray drive circuit 5. This output is constantly changing under normal conditions. And then The relay drive circuit 5 considers the change in this output to be normal and operates the relay 6. It's set. However, the microprocessor failed and two microprocessors were transferred to the external bus. When different data is output to the comparator circuit 4, this is detected and the subsequent relay drive circuit The signal sent to line 5 is fixed. In response to this state, the relay drive circuit 5 , drop the relay 6. As a result, the abnormal output is transmitted to the subsequent equipment via the contact of relay 6. A failure in the microprocessor 1, 1', etc. is detected and a predetermined Necessary measures will be taken.

[0014] The program in the above circuit does not need to consider access to the external bus. You can basically reuse the conventional program by simply adding an interrupt program. stomach. Note that when creating a new program, there is no need to consider time allocation. On the other hand, it is possible to use an external bus that was forced to be excluded in conventional programs. On the other hand, there is no need to consider the frequent use of “NOP” instructions, which do not cause data changes. It becomes. Note that the external bus monitoring circuit allows the microprocessor to monitor the external bus for a predetermined period of time. All you need to do is to detect when there is no access and no data change on the external bus. For example, it is possible to make appropriate changes such as input based on data on an external bus.

[0015] The above is a fail-safe microprocessor using two microprocessors. Although we have explained about microprocessor circuits, even if the circuit has only one microprocessor, If external access at regular intervals is required for device operation, or if the device is in operation from the outside. The above technical idea can be applied if you want to monitor Not even. In other words, a microprocessor with built-in cache memory and a The microprocessor detects when there is no output from the setter to the external bus within a predetermined time. and an external bus monitoring circuit that sends interrupt signals to the microprocessor circuit. , the microprocessor uses internal cache memory as described above. Even if the bus continues to be used and no external access is made, the external bus monitoring circuit will be forced to operate. access to the outside within a certain period of time, and there is no interruption in external access.

[0016]

[Effect of the idea]

As detailed above, in the present invention, the microprocessor circuit is A microprocessor with built-in cache memory and this microprocessor The microprocessor detects when there is no output on the external bus within a predetermined time. Since it is equipped with an external bus monitoring circuit that sends out interrupt signals, The microprocessor continues to use internal cache memory and output to the external bus. Even if the output is not output, the external bus monitoring circuit will force output to the external bus within a certain period of time. Because the external bus output is uninterrupted, it can therefore be operated externally. You can check.

[0017] In addition, in other inventions of the present application, the microprocessor circuit is Multiple microprocessors with built-in cache memory and Detects when there is no output from the processor to any of the external buses within a predetermined time. an external bus monitoring circuit that sends interrupt signals to the microprocessor, and Equipped with a comparison circuit that compares the status of the external bus, detects a discrepancy, and sends an abnormal signal. I configured it, so A loop program that can be continuously executed inside the cache memory by simply adding a simple circuit. Executing a program containing a program will not have a negative impact on the existing system, and RAM can be substantially repurposed, and unnecessary program development can therefore be avoided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a microprocessor circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional microprocessor circuit.

[Explanation of symbols]

1, 1'...microprocessor, 2, 2'...external bus, 3...external bus monitoring circuit, 4...comparison circuit.

Claims (2)

[Scope of utility model registration request] [Claim 1] A microprocessor with a built-in cache memory, and an external bus monitoring circuit that detects when there is no output from the microprocessor to an external bus within a predetermined time and sends an interrupt signal to the microprocessor. A microprocessor circuit equipped with [Claim 2] A plurality of microprocessors each having a built-in cache memory, and detecting that there is no output from each of these microprocessors to any of the external buses within a predetermined time, and sending an interrupt signal to the microprocessor. A microprocessor circuit equipped with an external bus monitoring circuit that sends out a signal, and a comparison circuit that compares the states of each external bus, detects a discrepancy, and sends out an abnormal signal.