JPH04132082A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To stabilize the operation of an address selection circuit by simultaneously operating a driving circuit in a first group and the one in a second group and putting these driving circuits in the first and the second groups to be operated simultaneously in physically distant positions at least for some rows or columns at all times. CONSTITUTION:Corresponding to one address selection signal, a driving circuit driving the word line or bit line of memory cell arrays 41 and 42 on one side of a decoder circuit 4 and driving circuits 2L and 2R and the driving circuit driving the word line or bit line of memory cell arrays 43 and 44 on the other side are arranged while physically keeping for several rows and columns. Therefore, the influence of noises caused on the power supply line by the relatively large current flowing through driving circuits 41 to 44 is reduced. Thus, the operation of the address selection circuit can be stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor integrated circuit, and more particularly to a memory circuit provided with an improved address selection circuit.

<Prior art> Figure 4 shows, for example, IEEE transactions.
on Elect-ron Devices, Vol.
ED-33, No. 1. January 198
6+P 104 to PIIG are diagrams showing the chip layout of the memory circuit IO. In the figure, a so-called x4-bit configuration R^- is shown as an example, where 1 is an X decoder circuit section for word line selection, 2 is a word line drive circuit section, and 4
1.42.43.44 is 110. -1. , l10-2
, l10-3.110.4 each memory cell array, 51
．． 52.53.54 is the same <l10-1. l10-
2, l10-3, and l10-4 are Y decoder circuits for selecting each bit line pair.

The X decoder circuit section l is an X decoder circuit 11, 12-...
・Including In, the word line drive circuit section 2 connects each word line 31
．． Word line drive circuit 21 for selectively driving 32...3n. '22...2n is included.

Each X decoder circuit 11~In, word line drive circuit 21~
2n are address signals A0 to A3, A0 to A supplied via the address selection signal line group 3 as shown in FIG.
, selectively energized by. Signals A0, Ao, A2, A3 of address selection signal line group 3 are all low level L
(Thus, the complementary signals ^., A4, A2, and A3 are all at high level H), the transistor Tl-74 of the X decoder circuit 11 is off and the node PI becomes H.

As a result, the transistor F of the word line drive circuit 21
1 is turned on, the word line 31 is selected, and current flows into the word line 31.
is connected to at least one of A0~^3, so
In this case, at least one of the transistors Tl-74 is on, each of the notes P2-Pn is at L, the transistors F2-Fn of the word line drive circuits 22-2n are off, and no current flows into the word lines 32-3n. Not supplied, therefore
Any word line can be selected by appropriately determining the logic of the signals supplied to 80 to A (therefore, Ao to π).

Returning to FIG. 4, when, for example, the X decoder circuit 11 is selected by the signal supplied to the address selection signal line group 3 of FIG. 5, the node P1 becomes H, and the word line drive circuit 2
1 is energized, word lines 31.31 for memory cell arrays 41.42 and 43.44 located on both sides thereof are selected and driven. That is, one X decoder circuit 11 drives word lines 31 and 31 of four memory cell arrays. The memory cells in each memory cell array 41 to 44 are Y
Each memory cell array 4 is
0, which is addressed by selecting one of the bit line pairs 61, 62, . . . , 61 among 1 to 44,
When the bit line 61 is selected, the four memory cells 111 are addressed together with the selected word line 31.

<Problem to be solved by the invention> Note 32, fist, consisting of the conventional semiconductor integrated circuit as described above...3n, 31, ]Z -----Jn, JJ
:(, rL+l, LIt----^ A so-called source follower circuit connected to Gn is adopted. Therefore, as explained in FIG. The nodes P2 to Pn) are at L, and the output thereof is at L, and this word line drive circuit 22
~2n almost no current flows, however, node P
1 becomes H, and the selected word line drive circuit 2
A current of a magnitude corresponding to the size of the transistor G1, which is common to the gate and source, flows through the transistor G1. This current is quite large because it is necessary to change the potential of the selected word line 31 at high speed, and generally the X decoder circuit 1
This is more than 10 times as large as the current flowing through 1. For this reason, the conventional X decoder circuit section 1 as shown in FIG.
The structure of the word line drive circuit section 2 has a drawback in that noise is likely to occur on the power supply wiring in response to selection or non-selection of the word line drive circuits 21 to 2n. In addition, since the voltage drop in the power supply wiring is generally large at the center of the chip, the X decoder circuit located at the center of the chip (for example, n = 12
If it is 8, the X decoder circuit will be within the range of the upper and lower number rows to the upper and lower number rows centered on the X decoder circuit of n = 64)
When this is selected, there is a drawback that the stability of the address selection operation deteriorates due to the voltage drop in the power supply wiring.

This invention was made to eliminate the above-mentioned drawbacks of conventional memory circuits, and it reduces the noise generated in the power supply wiring, and also allows the address selection circuit to be operated without being affected by the voltage drop in the power supply wiring. The purpose is to ensure stable operation.

<Means for Solving the Problems> A semiconductor integrated circuit of the present invention includes a decoder circuit, two drive circuits connected to the decoder circuit, and a region on both sides of a substrate where the decoder circuit and drive circuit are provided. The two drive circuits drive word lines or bit lines of the memory cell arrays arranged on one side of the area where the decoder circuit and drive circuit are provided, respectively. It consists of a first group for driving the word line or bit line of the memory cell array arranged on the other side. One drive circuit in the second group operates simultaneously, and the drive circuits in the first group and the drive circuits in the second group that operate simultaneously are always separated by at least several rows or columns. ) are configured to be physically separated.

<Function> In the memory circuit made of the semiconductor integrated circuit of the present invention, the drive circuit drives the word line or bit line of the memory cell array on one side of the decoder circuit and the drive circuit in response to one address selection signal. Since the drive circuit that drives the word line or bit line of the memory cell array on the other side is physically located several rows or columns apart, the relatively large current flowing through the drive circuit causes damage to the power supply line. The influence of noise occurring above is alleviated. Furthermore, since the above drive circuit only drives the word line or bit line of the memory cell array on either side of the decoder circuit or the drive circuit, it is possible to reduce the power consumed by each drive circuit. Coupled with the fact that the two drive circuits that operate simultaneously are physically separated, it is possible to suppress the voltage drop in the power supply wiring for supplying power to each drive circuit, and it is possible to suppress address selection. It is possible to stabilize the operation of the circuit.

<Embodiment> Hereinafter, a memory circuit using a semiconductor integrated circuit of the present invention will be explained with reference to the drawings. This example uses R of X4 bit configuration.
In AIII, a circuit configuration for selecting and driving word lines of a memory cell array arranged on both sides of a region where a decoder circuit and a drive circuit are provided is shown.

FIG. 1 shows the principle of a memory circuit using a semiconductor integrated circuit according to the present invention, in which 20 is a memory circuit formed on, for example, a GaAs semiconductor substrate, 41, 42, 43, 44 are 110-
1. Each memory cell array corresponding to l10-2, l10-3, l10-4, 51.52.53.54 is the same, each bit line selection corresponding to l10-1, l10-2, l10-3, l10-4 This is a Y decoder circuit for 30
is an X decoder circuit section and a word line drive circuit section including n X decoder circuits and 2R word line drive circuits connected to both sides of the X decoder circuits. A, ear indicates the highest signal line of the address selection signal line group consisting of Ao to A- and Ao to L, and this signal line is as shown in the figure.
The memory cell arrays 41 to 44 intersect at the center in the vertical direction. For example, when the word line drive circuit selects the uppermost word line 71-1 in the upper half of the left memory cell array 41.42, the uppermost word line 71-1 in the lower half of the right memory cell array 43.44 is selected. 72-h is selected, and when, for example, the lowest word line 71-g in the upper half of the memory cell array 41.42 is selected, the lowest word line 72-n in the lower half of the right memory cell array 43.44 is selected. is selected, and furthermore, when the d-th word line 72-d in the upper half of the right memory cell array 43.44 is selected, the d-th word line 71-k in the lower half of the left memory cell array 41.42 is selected. This is to ensure that the following items are selected. Regarding this point, ll1
Taking as an example the number of word lines per 0 or 16 trees,
This will be explained in more detail with reference to FIGS. 2 and 3.

Refer now to FIG. In Figure 2, the X decoder circuit section 4
The structure of the other parts except for the word line drive circuit sections 2L and 2R is the same as that of the conventional memory circuit formed by a semiconductor integrated circuit shown in FIG. However, the word lines of the memory cell array 41.42 arranged on the left side of the X decoder circuit section and the word line drive circuit section 30, which are composed of the X decoder circuit 4 and the word line drive circuit sections 2L and 2R, are 71-1.71. −
2...71-16, and the word line of the memory cell array 43.44 arranged on the right side is 72-1.72-2.
,...72-16.

The X decoder circuit section 4 includes X decoder circuits 11, 12,...
. . 116, and the word line drive circuit section 2L includes a first group of word line drive circuits 81, 82, . . . 816,
The word line drive circuit 2R is a second group of word line drive circuits 9.
Contains 1.92...916. The gate of the transistor Fil-F116 of each word line drive circuit is the output node P1 of the X decoder circuit 11, 12...116.
．． P2...PI6, respectively, and the gates of the transistors F21 to F216 of each word line drive circuit are connected to the uppermost signal line ^2... as will be explained with reference to FIG.
A3. If T's, it is connected to ^ or its complementary signal line ^3.

Next, referring to FIGS. 1 to 3, the X decoder circuit section 4
．． The connection relationship between the word line drive circuits @2L and 2R and the address selection signal line group 3 will be explained. That is, the gate of the transistor T1 of the X decoder circuits 11 to 116 is connected to the signal line A0 or Ao, the gate of the transistor T2 is connected to the signal line A1 or π, and the gate of the transistor T3 is connected to the signal line A2 or η. has been done.

The word line drive circuit in the upper half of the word line drive circuit section 2L of the first group, for example, the gates 8 of transistors F21 to F28 (Q! not shown) of 81 to 88 (not shown) and the word line drive circuit of the second group. The word line drive circuit in the lower half of the line drive circuit section 2R, for example, transistors F29 to 9g to 911i.
The gate of F21.6 is connected to the highest signal line ^3 that intersects at the center, and is connected to the word line drive circuit section 2L of the first group.
For example, the gates of transistors F29 to F216 of transistors 89 to 816 and the word line drive circuit 1 in the upper half of the word line drive circuit section 2R of the second group.
For example, transistors F21-91 to 98 (not shown)
The gate of F28 (not shown) is connected to the uppermost auxiliary signal curb crossed in the center. Thus, the signal lines A3 and η act as transmission lines for the word line drive circuit selection signal.

As mentioned above, the signals supplied to each X decoder circuit IfS116 are supplied to the gates of transistors F21 to F216 of 0, π, 80, AI, A2, and word drive circuits 81 to 816 and 91 to 916. Signal A3,■
This constitutes one set of X address selection signals. Also, X
The decoder circuit section 4 receives the signals A0 and A so that one X decoder circuit in the upper half and one X decoder circuit in the lower half are always energized.
o to A* are connected to each signal line so that the shoulders are input.

next,! The operation of the memory circuit shown in FIG. s2 will be explained with reference to FIG. 3 again.

Signal A of address selection signal line group 3. , A1. At
, A3 are all L (therefore, the auxiliary signals I, A, ,
T; "η are all H), transistors T1 to T3 of the X decoder circuits 11 and 19 are off, and the output node P1.F
9 becomes H, and all other output notes P of the X decoder circuit become L. As a result, the first group of word line drive circuits 8]3 and 89, #! Group 2 word line drive 1
1g91 and 99 each transistor Fil, F1
9 turns on.

On the other hand, since the highest signal A3 and ■ are H,
Transistors F21 to F28 . of the word line drive circuits 81 to 88 in the upper half of the first group. Transistors F29 to F21 of the word line drive circuits 99 to 916 in the lower half of the second group
6 is turned on. As a result, the word line 71 is placed at the top of the upper half of the left memory cell array 41, 42.
-1 and the word line 72-8 arranged at the top of the lower half of the right memory cell array 43.44 are selected, and current flows into these word lines 71-1 and 72-8.
Since the X decoders other than 11.18 are connected to at least one of π, te, and nodes P2 to P8 . P.I.
G (not shown) ~PI6 becomes H and the corresponding word drive circuit 12~18.110~II'S is not activated or is H, so the word drive circuit g1
and 89 are not activated, so the word line 71
Word lines other than -1 and 72-8 are not selected.

Address signal (^0^r A2 All) = (3
000) (However, when ~l~=H, -〇-=L), the word line drive circuit 82 of the first group and the word line drive circuit 91O (not shown) of the second group are energized. , a word line 71-2.7 connected to each of these word line drive circuits.
2-10 (not shown) is selected.

The address signal is (AoA, A, A3) = ((11G(1)(
AOAt At Ayu) = (1100)(AO^s
As AOA3)=(1110), the word lines in the upper half of the left memory cell array are sequentially selected from top to bottom, and at the same time, the word lines in the bottom half of the right memory cell array are similarly selected sequentially from top to bottom. Ru.

When the signal A becomes H, the word line in the upper half of the right memory cell array is selected sequentially from top to bottom as the signal 80~^3 changes, and at the same time the word line in the lower half of the left memory cell array is selected. word lines are selected sequentially from top to bottom.

Thus, according to the present invention, two word line drive circuits (for example, 81 and 99, 91 and 89, etc.) which are always physically separated from each other in the memory circuit 20 configured on the GaAs substrate are selected. This reduces the influence of noise caused by the current flowing through each power supply line, compared to the conventional method in which one word line drive circuit drives all the word lines of the memory cell array, and It is possible to suppress the voltage drop and stabilize the operation of the address selection circuit. Note that bit line pairs 61, 62, and 61, 62, and 62 in the memory cell arrays 41 to 44 are controlled by the Y decoder circuits 51 to 54, respectively.
. . 6-, a specific memory cell in each memory cell array, for example Mll, is selected, as in the conventional memory circuit shown in FIG.

In the above embodiment, the most significant signal A3, ■ of the X address signal is used to select the word line drive circuit, but the present invention is not limited to this, and the X address signal of any order is used to select the word line drive circuit. It can also be used as a selection signal. In this case, the word line drive circuit to be energized does not sequentially energize the upper half on the left side and the lower half on the right side, or the upper half on the right side and the lower half on the left side, as in the embodiment; Each word line drive circuit section is divided into two or more predetermined groups, for example, four groups, and the word line drive circuits in each of the left and right groups are sequentially selected. That is, in the first step, for example, each of the word line drive circuits in the first group on the left and the second group on the right is sequentially selected from above, and in the second step, each of the first group on the right and the second group on the left is selected. Select the word lines sequentially from the top and select the third word line.
In the step, each word line drive circuit of the third group on the left and the Is4 group on the right is selected sequentially from above, and in the fourth step, each word line drive circuit of the third group on the right and the fourth group on the left is selected. You will be able to select from the top. It goes without saying that the address signal may be of any order depending on the number of rows of memory cells, and is not limited to Ao to A:I and Ao to A3. Instead of this method, a bit line selection method may be used.

<Effects of the Invention> As described above, according to the present invention, a drive circuit selectively drives a word line or a bit line of a memory cell array on one side of a region where a decoder circuit section and a drive circuit section are arranged. and the drive circuit that selects and drives the word line or bit line of the memory cell array on the other side are always physically separated by at least several rows or columns. The large current reduces noise generated in the power supply line near the drive circuit, suppresses voltage drop on the power supply line near the drive circuit, and enables stable address operation.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram illustrating the principle of a memory circuit using a semiconductor integrated circuit according to the present invention, FIG. 2 is a diagram schematically showing the circuit configuration of an embodiment of a memory circuit using a semiconductor integrated circuit according to the present invention, and FIG. The figure is a diagram illustrating the connection relationship between the X decoder circuit section, the word line drive circuit section, and the address selection signal line group used in the memory circuit based on the semiconductor integrated circuit of the present invention, and FIG. FIG. 5 is a diagram schematically showing the circuit configuration of an example of a memory circuit, and FIG. 5 shows an X decoder circuit section, a word line drive circuit section, and an address selection signal line group used in the memory circuit based on the conventional semiconductor integrated circuit shown in FIG. It is a figure explaining the connection relationship with. 2L...First group word line drive circuit section, 2R...
...Second group word line drive circuit section, 4...X decoder circuit section, 11-1n...X decoder circuit, 20
...Memory circuit, 41-44...Memory cell array, 51-54...Y tacho-5 circuit, 61-6 layer...
...Bit line pair, 30...X decoder circuit It and word line drive circuit, 71-1 to 71-n...Word line of left memory cell array, 72-1 to 72-1
1...Word line of the right memory cell array, 81~
816...First group word line drive circuit, 91 to 91
6... Second group word line drive circuit.

Claims (1)

[Claims] (1) A decoder circuit, two drive circuits connected to the decoder circuit, and a plurality of memory cell arrays arranged on both sides of a region on a substrate in which these decoder circuits and drive circuits are provided, The two drive circuits include a first group for driving word lines or bit lines of a memory cell array arranged on one side of the area where the decoder circuit and the drive circuit are provided, and a first group arranged on the other side. a second group for driving word lines or bit lines of the memory cell array,
One drive circuit in the first group and one drive circuit in the second group operate simultaneously, and the drive circuit in the first group and the drive circuit in the second group operate simultaneously. A semiconductor integrated circuit characterized in that the drive circuit is always physically separated by at least several rows or columns.