JPH04131960A - Computer operating method and computer system - Google Patents

Abstract

PURPOSE:To maximize the throughput within a single cycle by securing the independent operations between an arithmetic part and a transmission/reception part by means of an alternate buffer memory, starting simultaneously the arithmetic processing and the data transmission/reception processing with a synchronizing signal common to all computers, and completing both processings within a single cycle of the synchronizing signal. CONSTITUTION:When a computer #1 (11) detects a synchronizing signal 154b, an arithmetic part 111 carries out an operation 111b and stores this arithmetic result in a buffer memory 113. At the same time, a transmission part 114 performs the transmission processing 114a to transmit the contents of a buffer memory 112 to a computer #2 (12). Thereafter the computer #1 repeats the preceding operations for each detection of pulses 154c, 154d, 154e... of the synchronizing signals 154. Thus the computers #1 (11), #2 (12) and #3 (13) start the arithmetic operations and the transmission/reception of data concurrently with detection of the synchronizing signal. These operations are carried out in parallel by the independent circuits. As a result, no loss time is produced by the transmission/reception processing of each computer and the throughput is maximized within a single cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer system in which a plurality of computers share processing while maintaining synchronization.

[Conventional technology]

A conventional example of synchronizing multiple computers is JP-A-63
There is a publication No.-291156. In this conventional example, for each computer, the timing of the synchronization signal applied to the subsequent computer is shifted from the generation time of the synchronization signal of the previous stage by a longer time than the time required for processing in the previous stage computer. As a result, the processing time of the entire system was shortened, in other words, loss time was reduced.

A conventional example will be specifically explained. FIG. 6 is a block diagram of the conventional example, and FIG. 7 is a timing chart of the conventional example. In this conventional example, a synchronization signal having a phase difference of a fixed time period is given to each computer to a plurality of computers connected in multiple stages.
It executes processing. That is, this conventional example has one synchronization signal generation section 62 and three cascade-connected computers #1 to #3 (61 to 63), and the synchronization signal generation section 62 has a clock circuit 66 and three computers #1 to #3 (61 to 63) connected in cascade. , and synchronous signal generating sections 63, 64 and 65 that generate synchronous signals 71 to 73 at different timings, respectively. Calculator #1 (61
) is generated by the first synchronization signal generation circuit 63 as the synchronization signal 71 (
Computation processing (711a, 71b, ...) is performed for each
711b, -) and transmission processing (712a, 712b).

), and the computer $ 2 (62) takes a time t1 longer than the total time (t+ + tIs) for those processes.
Synchronization signals 72 (72a, 72b,
) performs arithmetic processing (722a, 722b,
) and transmission processing (723a, 723b).

···)I do. Computer #3 (63) similarly generates a synchronization signal 73 (
73a, 73b.

...), the calculations (732a, 732b, ...) are performed for each step.

[Problem to be solved by the invention]

In order to apply the above-mentioned conventional example, it is necessary to know the entire processing time, including the start timing of data transfer to each computer as described above. In a multi-stage multiprocessor system that controls real-time simulation of audio and video, the processing content and data transfer amount of individual computers may change sequentially, so it is difficult to uniquely determine the start time of data transfer. Can not.

Therefore, the problem is that it is impossible to establish the timing of starting processing for each computer from the host computer that is in charge of controlling the system, so that it cannot be applied to such a system.

Furthermore, in the conventional example, there is no problem if the time for data transmission and reception processing (tls + t2r + j2s + t3r) of each computing engine is extremely short compared to the calculation time, but if it becomes longer, the synchronization signal will be lost within the synchronization time to. Computation time (
t+, j2+t3), which leads to a reduction in throughput. Conversely, if we try to improve the throughput within tQ, we will need to increase the data transmission/reception processing (t
est j2r+ test j3r) will not be able to secure enough time. Therefore, this method is not effective for systems that require a large amount of data to be transferred or for systems that require processing with a high load rate.

Furthermore, in the conventional method, an individual synchronization signal must be given to each computer, which poses a problem in terms of suitability for large-scale and complicated system configurations.

(I) It requires hardware logic to generate a synchronization signal for each number of computers, and it is impossible to set the phase difference of the synchronization signals for each computer unless the processing time for each computer is known.

(2) If the connection of a computing engine or the processing time changes, it may be necessary to reset the phase difference of not only a specific computer but also all synchronizing signals.

This significantly reduces work efficiency during software depacking, system startup, and maintenance/inspection.

It is an object of the present invention to provide a computer operating method and a computer system that solve the above-mentioned problems and further improve the throughput of the system to the maximum extent possible.

[Means to solve the problem]

The computer operating method of the present invention uses an alternating buffer memory in the computer that can be accessed simultaneously from the arithmetic unit and the transmitter/receiver, thereby making the operations of the arithmetic unit and the transmitter/receiver independent. By using a common synchronization signal for all computers, arithmetic processing and data transmission/reception processing are started at the same time, and the processing is completed within one cycle of the synchronization signal.

(Claim 1).

Furthermore, in the computer system of the present invention, in each computer, a calculation section, a transmission/reception section for communication with other computers, two alternating buffer memories provided between the calculation section and the transmission/reception section, A switching section is provided that alternately switches the two alternating buffer memories for use in the arithmetic section and for use in the transmission/reception section in synchronization with a synchronization signal (claim 2).

Furthermore, the computer system of the present invention includes, in each computer, a calculation section, a transmission section for communicating with other computers, and two alternating buffer memories provided between the calculation section and the transmission/reception section; The arithmetic unit in each computer is comprised of a switching unit that alternately switches the two alternating buffer memories to one for the arithmetic unit and one for the transmitting/receiving unit.

Each time the synchronization signal is input, the switching section is activated to
Two buffer memories, one for the calculation section.

The other is for the transmitter/receiver unit and is switched alternately, and all the arithmetic units and all the transmitter/receivers independently perform arithmetic processing and transmission/reception processing with the corresponding buffer memory in synchronization with a synchronization signal. (Claim 3)

Further, in the computer system of the present invention, in three or more computers connected in cascade to each other, the first-stage computer is provided with an arithmetic section, a transmitting section to the next-stage computer, and between the arithmetic section and the transmitting section. It consists of two alternating buffer memories, and a switching section that alternately switches the two alternating buffer memories to one for an arithmetic section and one for a transmitting/receiving section. , a transmitter to the next computer,
Two alternating buffer memories (I) are provided between the receiving section and the calculating section, and the two alternating buffer memories (I) are alternately used for the receiving section and for the calculating section.

The first switching section to be switched, the two buffer memories (■) provided between the arithmetic section and the transmitting section, and the two alternating buffer memories (II) are alternately used for the arithmetic section and for the transmitting section. The final stage computer includes a receiving part from the previous stage computer, a calculating part, and two alternating buffer memories provided between the receiving part and the calculating part. , a switching section that alternately switches the two alternate buffer memories for the receiving section and the computing section, and the computing section in each computer switches each of the switching sections each time a synchronization signal is input. Each of the two alternating buffer memories is switched alternately, one for the calculation section and the other for the reception section and the transmission section, and all the calculation sections, all reception sections, and all transmission sections are switched. , and a corresponding buffer memory in synchronization with the synchronization signal, arithmetic processing, reception processing, and transmission processing are performed (claim 4).

Furthermore, the computer system of the present invention includes a computer that receives input from a plurality of computers and outputs processing results to the plurality of computers, and a synchronization signal generator that generates a completely synchronized synchronization signal to each computer. , the computer includes a receiving section compatible with a plurality of computers on the input side, an arithmetic section, two alternating buffer memory groups (I) provided between each of the receiving sections and the arithmetic section, and a plurality of computers on the output side. a computer-compatible transmitter, and two alternating buffer memory groups (II) provided between the arithmetic unit and each transmitter.
), a first switching section that switches the two alternating buffer memory groups (I) into one for the receiving section and one for the arithmetic section in synchronization with the synchronizing signal, and
I) for the arithmetic section and for the transmitting section, and a second switching section that switches I) in synchronization with the synchronization signal (claim 5).

[For production]

In the computer operating method and computer system of the present invention, the arithmetic unit and the transmitting/receiving unit operate independently using a common synchronization signal for all of the plurality of computers, and each of them operates in a predetermined manner within one cycle of the synchronization signal. Claim 1 characterized by the processing of
, 1.3). As a result, the following effects are obtained.

(I) There is no loss time due to transmission/reception processing for each computer, and the maximum throughput within one cycle can be ensured.

(2) It is compatible with all types of connection of computing institutions without considering the calculation processing time and transmission/reception time of each computer, and the connection can be easily changed.

Furthermore, in the computer system of the present invention, in a computer system in which three or more computers are connected in cascade,
Calculation and transmission in the first-stage computer, reception, calculation, and transmission in the middle-stage computer, and reception and calculation in the final-stage computer are switched in a complete cycle, and two-alternate buffer memory is used for each process. The buffer memory necessary for each process is selected by employing the following (claim 4). This results in
Throughput in cascade-connected computer systems is improved.

Furthermore, in the computer system of the present invention, in a computer that receives input from a plurality of computers and outputs processing results to the plurality of computers, alternate buffer memories are used to handle the input and output. Calculation and transmission can be performed synchronously (claim 5). As a result, in computers that perform parallel input and output, throughput can be improved.

〔Example〕

The present invention will be explained in detail below.

FIG. 1 shows an overall configuration diagram of an embodiment of the present invention.

Computer #1 (I1) is connected to the calculation unit 111 and the connection bus 1.
Alternate buffer memories 112 and 113 that can alternately switch between 15° and 116, and a switching unit 11 that performs the switching
7 and a transmitter 114 for transmitting data to the computer $2 (I2). Calculator #2 (I2)
Like the computer $ 1 (I1), in addition to the arithmetic unit 124, buffer memories 125, 126, and transmitter 127, the receiver 121 . Buffer 7 memory 122.123. and switching sections 128A and 128B. Calculator #3
(I3) includes a receiving section 131, buffer memory 132, 133, and calculation section 13 similar to computer #2 (I2).
4. It is composed of a switching section 135. Here, both the transmitting section and the receiving section are circuits that independently perform data inversion processing in response to an activation signal. Furthermore, the arithmetic unit includes a CPU and a memory that stores programs.

First, a synchronization signal generator 15 for synchronizing the entire computer.
In contrast, a startup control unit 1 for starting the operation of the system
A start signal 145 from clock circuit 15 is applied to clock circuit 15.
Based on the clock signal 153 from 1, the synchronous signal generation circuit 152 generates synchronous signals 154° 155, 156 of the same phase.
, and output them respectively from computers #1 and 32゜#3 (I1,
12, 13).

The computer 31 (I1) receives the synchronization signal 154 shown in FIG.
When the first pulse 154a of
executes the process 111a and stores the result in the buffer memory 1.
12. When the calculation process 111a is completed, the computer #1 (I1) activates the switching unit 117,
Switch the path lines 115 and 116 connected to the buffer memories 112 and 113, so that the buffer memory 112 is connected to the receiving section 114, and the buffer memory 113 is connected to the calculation section 111.
connected to. Next, when the computer #1 (I1) detects the synchronization signal 145b, the calculation unit 111 performs the calculation 111b.
At the same time as executing and storing the results in the buffer memory 113, the transmitter 114 performs a transmitting process 114a to transmit the contents of the buffer memory 112 to the computer #2 (I2).
I do.

Thereafter, computer #1 (I1) repeats the above operation every time it detects each pulse (I54c, 154d, 154e, -) of the synchronization signal 154.

Computer #2 (I2) receives synchronization signal 155 (I55a
= 155d), the buffer memory 122
and 123 are alternately connected to the receiving section 128 and the calculating section 124, so that they can immediately receive transmission data from the computer #1 (I1) as soon as it is sent. Therefore, at the same time as the transmission processing 114a of computer $ 1 (H) is performed, the computer # 2 (I2) performs the reception processing 121a, and the received data is stored in the buffer memory 12.
2.

At this time, the buffer memory 123 is connected to the arithmetic unit 124, but the received data is empty and no arithmetic processing is performed.Next, the computer #2 (I2) detects the synchronization signal 155a. Therefore, buffer memory 1
22 to the arithmetic unit 124 and the buffer memory 123 to the receiving unit 121, wait for the next data to be sent from computer #1 (I1), and perform the receiving process 121b at the same time as the sending process 114b. Buffer memory 1
23. Further, in parallel with this process, the calculation unit 124 performs a reception process 12 immediately after detecting the synchronization signal 155a.
Arithmetic processing 124a is performed based on the data in the buffer memory 122 stored in 1a, and the result is stored in the buffer memory 12.
5. Then, when the computer $ 2 (I2) detects the synchronization signal 155b, the buffer memory 122 is connected to the reception section 121, the buffer memory 123 is connected to the calculation section 124, the buffer memory 125 is connected to the transmission section 127, and the buffer memory 1
26 switches to the arithmetic unit 124, and at this point, a reception process 121c, an arithmetic process 124b, and a transmission process 127a are performed in parallel. Thereafter, computer #2 receives the synchronization signal (I
15a, 115b, 115c, -) is detected, the above operation is repeated.

Calculator $ 3 (I3) first uses computer # 2 (I2
) is received in the reception process 131a and stored in the buffer memory 132. Next, by detecting the synchronization signal 156a, the buffer memory 132
34, the buffer memory 133 is switched to the receiving section 131, and the receiving section 131 performs receiving processing 131b, and at the same time, the calculating section 134 performs calculating processing 134a based on the data in the buffer memory 132. Thereafter, the above operation is repeated while switching the connections between the buffer memories 132 and 133 every time the synchronizing signal 156 (I56a, 165b, . . . ) is detected.

In this way, calculator #1. $2. $3 (I1,12
13), calculation and data transmission/reception processing are started at the same time as the synchronization signal is detected, and these are performed in parallel by independent circuits. In addition, these processing times
r t12νj21 r i22+ j23y i3
1 pt32 is set within the period to of the periodic signal. Therefore, the maximum throughput in arithmetic processing for each calculation can be secured within the period to without being aware of loss time due to data transmission and reception processing. Furthermore, the connection of calculation periods can be easily changed without considering each other's processing time.

If the 1-hydraulic type is applied, a unique effect is that not only the above-mentioned one-dimensional connection form but also two-dimensional multiple connection state as shown in the block diagram of Fig. 3 can be easily performed. I can do it. FIG. 3 will be explained in detail.

This example uses eight computers #1 to $8 (31 to 38).
and one periodic signal generator 39.

Calculator 32.36.38 is an example of input/output with 1 human power and 1 output, Calculator 31.35 is an example of 2 outputs and 3 outputs, Calculator 3
3°37 is an example of two-man power and three-man power, and the computer 34 is an example of two-man power and two outputs. The synchronization signal generation device 39 includes a clock circuit 39B and a synchronization signal generation circuit 39A.
Common synchronization signals (1) to (2) are output to each of the computers 31 to 38.

Computers #1 to #8 (31 to 38) are the same as the computer shown in FIG.
4.35.37. ).

Taking the computer $4 (34) as an example, its block diagram has the configuration shown in Figure 4, with four pairs of transmitter/receiver sections and double buffer memory sections (42, 43, 45, 46゜48).
, 49.412.414). Furthermore,
Receiving units 41, 44, transmitting units 411, 413, calculation unit 47
has. This computer #4 (34) operates in exactly the same way as computer #2 (I2) shown in FIG. Fifth
The figure shows a timing chart for computer #4 (34). The synchronization signal ■ to computer #1 is sent to symbol 51 (51a,
51b,...). Synchronization signal also to computer #4■
is input, which is indicated by the symbol 40. Signals 40 and 51
are the same synchronization signal. In response to the synchronization signal 51a, the computer #1 (31) and the computer $5 (35) perform operations 511a and 551a, respectively. Next, synchronization signal 5
1b, Calculator #1 (31), Calculator $5 (
35) and computer #5 (34) are respectively processed 51
1b, 512a, 551b, 552a, 541
a, perform 542a. At this time, the calculator $ 4 (34
) is sent to computer #1 (31) by the receiving unit 41.44.
, the computer $5 (35). And computer #4 (34) receives synchronization signal 51C.
Accordingly, while receiving data in reception processing 541b and 542b, calculation 543a is performed based on the two types of data already received in 541a and 542a. Synchronization signal 51d
At the time point, computer #4 (34) performs processing 541c, 542c, and 543b in the same manner as described above, and transmits the data resulting from the calculation 543a to processing 544a by transmitting units 411 and 413.

545a, and sent to computer #3 (33) and computer #7 (37), respectively.

In this manner, the present invention can be easily operated not only in series but also in parallel multiple connections.

A specific example using this computer system will be described.

A three-dimensional object is imaged by two TV cameras installed at different positions, computer #1 captures the image captured by the first TV camera, and computer #5 captures the image captured by the second TV camera. shall be.

It is assumed that the computer system shown in FIG. 3 processes these two images and extracts certain features. Role 1 of each calculator #1 to #8 in this case? J44 Set as below.

Computer #1: Preprocessing such as noise removal for the first image, Computer #2: Binarization processing computer # of the preprocessing result image
5... Pre-processing such as noise removal on the second image, Computer #4... Computer $1. Product-sum calculation processing of the preprocessing result of #5.

Computer #6: Binarization processing computer # for preprocessing result images
8... Edge enhancement processing computer #3 for preprocessing result image
... Feature I is extracted from the processing results of computers #2 and #34.

Calculator #7... Calculator #4. Extraction of feature (2) from the processing result of $6.118, where feature I and (2) indicate the properties of the image.

In addition, computer #1 in FIG. 1 has one transmitter, computer #3
In the above, one receiving section was used, but there is no particular problem if they are referred to as a transmitting/receiving section without distinction.

〔Effect of the invention〕

According to the present invention, since the arithmetic section, the transmitting section, and the receiving section are made independent, there is an effect that the load factor of the arithmetic section can be increased to nearly 100 percent in principle.

In addition, even if the system connection status becomes larger and more complex,
It is compatible with all system configurations, and connections can be easily changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention, FIG. 2 is an operation timing chart thereof, FIG. 3 is a block diagram to which the present invention is applied, and FIG. 4 is a block diagram showing the inside of one of the computers.
FIG. 5 is a timing chart thereof, FIG. 6 is a block diagram explaining the conventional system, and FIG. 7 is a timing chart thereof. 11... Calculator (#1), 12... Calculator (32)
, 13... Computer (#3), 14... Start-up control unit,
15... Synchronization signal generation section, 31-38... Computer #
1 to #8.39...Synchronization signal generation unit, 61...Computer #1.62...Computer #2.63...Computer #3
．． 64...First synchronization signal generation circuit, 65...Second
66... Third sync signal generation circuit, 67... Clock circuit, 60... Sync signal generation section. Representative Patent Attorney Tadashi Akimoto Actual Diagram Diagram

Claims (1)

[Claims] 1. It has a plurality of computers connected to each other and a synchronization signal generation section that generates a synchronization signal in complete synchronization to each of the computers. Using an alternating buffer memory that can simultaneously access data from the transmitter and receiver, the operation of the arithmetic unit and the transmitter/receiver are made independent, and a synchronization signal common to all computers starts arithmetic processing and data transmission/reception processing at the same time. A method of operating a computer in which processing is completed within one cycle of a synchronization signal. 2. Consists of a plurality of computers connected to each other and a synchronization signal generation section that generates a synchronization signal with a complete cycle to each of the computers. The transmitter/receiver, two alternate buffer memories provided between the arithmetic unit and the transmitter/receiver, and the two alternate buffer memories are alternately used for the arithmetic unit and for the transmitter/receiver in synchronization with the synchronization signal. A computer system comprising: a switching unit that performs switching; 3. A plurality of computers connected to each other, and a synchronization signal generation unit that generates a synchronization signal with a complete period to each of the computers;
Each of the above-mentioned computers includes an arithmetic unit, a transmitting/receiving unit for communicating with other computers, two alternating buffer memories provided between the arithmetic unit and the transmitting/receiving unit, and the two alternating buffer memories. It consists of a switching section that alternately switches between the arithmetic section and the transmitting/receiving section, and each time the periodic signal is input, the arithmetic section in each computer can move the switching section to switch between the two buffer memories. shall be alternately switched between one for the arithmetic unit and the other for the transmitter/receiver, and all the arithmetic units and all the transmitter/receivers will perform arithmetic operations with the corresponding buffer memory in synchronization with the above periodic signal. A computer system that performs processing, transmission and reception independently. 4. Three or more computers connected in cascade to each other,
a synchronization signal generation section that generates a perfectly periodic synchronization signal to the computer; It consists of two alternating buffer memories and a switching section that alternately switches the two alternating buffer memories between the arithmetic section and the transmitting section. , a transmitter for the next stage computer, two alternate buffer memories (I) provided between the receiver and the arithmetic unit, and two alternate buffer memories (I) for the receiver and the arithmetic unit. A first switching section that alternately switches between the two buffer memories (I) provided between the calculation section and the transmission section.
I) and a second switching unit that alternately switches the two alternating buffer memories (II) between the arithmetic unit and the transmitting unit, and the final stage computer receives data from the previous stage computer. a computing section, two alternating buffer memories provided between the receiving section and the computing section, and a switching section that alternately switches the two alternating buffer memories for the receiving section and for the computing section; Each time a synchronization signal is input, the arithmetic section in each computer activates each of the above switching sections to create two alternating buffer memories, one for the arithmetic section, the other for the receiving section and the transmitting section. alternately,
A computer in which all arithmetic units, all receiving units, and all transmitting units perform arithmetic processing, reception processing, and transmission processing with the corresponding buffer memory in synchronization with the synchronization signal. system. 5. It has a computer that receives input from multiple computers and outputs processing results to the multiple computers, and a synchronization signal generator that generates a synchronization signal with a complete period to each computer, and the computer has an input A receiving section compatible with multiple computers on the side,
an arithmetic unit, two alternating buffer memory groups (I) provided between each receiving unit and the arithmetic unit, a transmitting unit compatible with a plurality of computers on the output side, and between the above arithmetic unit and each transmitting unit; The two alternating buffer memory groups (II) provided in
A first switching unit that switches in synchronization with the synchronization signal, and a second switching unit that switches the two alternating buffer memory groups (II) into one for the calculation unit and one for the transmission unit in synchronization with the synchronization signal. A computer system consisting of.