JPH04130818A - Input circuit - Google Patents

Abstract

PURPOSE:To set multiple modes with few input terminals by providing a timing generation circuit generating the control signals of first and second load elements and a shift clock and pulling up and pulling down the input terminal while synchronizing with a certain timing. CONSTITUTION:When P and N signals are outputted if an H-level is given to the input terminal 1, first and second shift registers 6 and 6' become H. When an L-level is given to the input terminal 1, the first and second shift registers 6 and 6' become L. When input is in open, the Q output of the first shift register 6 becomes L and the Q output of the second shift register 6' becomes H. Since the outputs of the first and second shift registers 6 and 6' are different from each other by three states of the input terminal 1, three states of input can be judged by decoding the output with a decoder 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an input circuit, and in particular, the present invention relates to an input circuit that pulls up an input terminal.
Use it in three ways, like pull-down or open.
The present invention relates to an input circuit that can determine three states using one input terminal.

[Conventional technology]

Conventional input circuits of this type were as shown in FIGS. 3 to 5. In Figure 3, input terminal 1 directly connects to buffer 2.
4 and 5 are block diagrams showing an example in which the input terminal 1 is connected to the pull-up resistor 21. It is connected to the buffer 2o through a pull-down resistor 22.

[Problem to be solved by the invention]

Since the input circuit shown in FIG. 3 described above is directly connected to the buffer 2°, the state of the input terminal 1 can only be set in two ways, pull-up or pull-down, and only binary logic can be determined. In addition, in the input circuits of FIGS. 4 and 5, the processing of input terminal 1 can give three values: pull-up, pull-down, or open, but buffer 2
As for the output of 0, only binary logic judgment could be made as in FIG. 3. Therefore, in such conventional input circuits, only two values, that is, two modes can be set for one input terminal 1. For example, even if two input terminals are combined, only four modes can be set. Ta. Generally speaking, for n (n is a positive integer) input terminals,
Only 2" modes could be set.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input circuit which solves the above-mentioned drawbacks and is capable of outputting three modes using - input terminals.

[Means to solve the problem]

The configuration of the input circuit of the present invention is such that the input circuit is connected between a first power source and an input terminal, and is connected as a load between the input terminal and the first power source by a control input signal input to a gate. a first load element that switches between the input terminal and the second power source; and a first load element that is connected between the second power source and the input terminal, and is connected as a load between the input terminal and the second power source by a control input signal input to the gate. an input buffer that receives the signal from the input terminal and converts the impedance; and a shift register that uses the output of the input buffer as a data input and shifts input data using a shift clock. and a timing generation circuit that generates control signals for the first and second load elements, the shift clock, and a decoder circuit that decodes the output data of the shift register.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an input circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart showing its operation.

In FIG. 1, the input circuit of this embodiment includes a timing generation circuit 5 having outputs of an N signal, a P signal, a clock (C) signal, a reset (R) signal, and a read permission (S) signal, and a MOS ) transistors 2 and 3, buffer 4,
1st. a second shift register (D-type flip-flop) 6.6', a decoder 10 consisting of three two-man power NAND gates, an input terminal 1, and each output terminal 7.8.9 of the NAND gate; Read permission signal output terminal 1
1.

In FIGS. 1 and 2, first, a P signal generated by the timing generation circuit 5 causes the load element 2 made of a MOS transistor to conduct, and pulls up the input terminal 1 to the VDfl side. At that time, the state of the input terminal 1 is 0, which is input to the first shift register 6 through the input buffer 4 which inverts the input and outputs it.
Next, the load element 3 is made conductive by the N signal generated by the timing circuit 5, and the input terminal 1 is pulled down to the GND side. At that time, the state of input terminal 1 is input buffer 4.
is input to the first shift register 6.

At this time, the impedance of the load elements 2 and 3 is set to be sufficiently larger than the impedance that drives the input terminal 1 from the outside.

As described above, when the "H" level is first applied to the input terminal 1, if the P and N signals are output according to the timing shown in FIG. Both the second shift registers 6 and 6' are at "H", and when the "L" level is applied to the input terminal 1, the first... Second shift register 6.6
' are both "L".

Further, when the input is open, the Q output of the first shift register 6 is "L", and the Q output of the second shift register 6' is 'H'.

As mentioned above, the outputs of the first and second shift registers 6 and 6' differ depending on the three states of the input terminal 1, so by decoding the outputs with the decoder 10, it is possible to determine the three states of the input. By reading this output while the read a permission S signal outputted from the timing generation circuit 5 is being outputted, the state of the input terminal 1 is determined.

〔Effect of the invention〕

As explained above, the present invention can pull up and pull down the input terminal in synchronization with a certain timing and read the state of the terminal at that time. It has the effect of being able to judge the values of the three states of ``level input oven'', and as a result, with n input terminals, conventionally only the 2'' mode could be set, but it is now possible to set the 3fi mode.
Another effect is that many mode settings can be made with a small number of input terminals.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an input circuit according to an embodiment of the present invention, Fig. 2 is a timing diagram of the circuit shown in Fig. 1, and Figs. 3 to 5 are block diagrams showing conventional input circuits. be. 1... Input terminal, 2, 3... Load element, 4... Input buffer, 5... Timing generation circuit, 6... shift register, 7, 8
．． 9...Output signal, 10...Decoder, 11...Read permission signal. Agent Patent Attorney Hara Uchi

Claims (1)

[Claims] A first load element connected between a first power source and an input terminal, and configured to switch whether or not to be connected as a load between the input terminal and the first power source by a control input signal input to a gate. and a second power supply connected between the second power supply and the input terminal, and switching whether or not to be connected as a load between the input terminal and the second power supply according to a control input signal input to the gate. a load element; an input buffer that receives a signal from the input terminal and converts impedance; a shift register that uses the output of the input buffer as a data input and shifts input data using a shift clock;
and a control signal for a second load element, a timing generation circuit that generates the shift clock, and a decoder circuit that decodes output data of the shift register.