JPH04130769A - Input protective device for mos integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the charge discharged in a semiconductor substrate thereby lessening the effect on the inner active element in a MOS type integrated circuit by this charge by a method wherein the low concentration wells in the opposite conductivity type to that of the semiconductor substrate connected to an input terminal is encircled by the other low concentration wells in the opposite conductivity type to that of the substrate impressed with a fixed potential extending over the whole periphery. CONSTITUTION:Low concentration wells 4, 5 are formed in the regions including the diffused layers 2, 3 approaching to each other encircling the peripheral parts of the diffused layer 2 at the intervals of about 5-10mum excluding the region including the diffused layer 2. Accordingly, when an aluminum wiring 9 is impressed with an excessive voltage to expand the depletion layer of the low concentration well 4, this expanded depletion layer comes into contact with that of the low concentration well 5 extending over the whole periphery. Accordingly, most of the charge generated by the impressed excessive voltage shall be discharged in the low concentration well side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input protection device for a MOS type integrated circuit, and more particularly to a bunch-through type input protection device.

[Conventional technology]

Conventionally, in MOS integrated circuits, when the voltage applied to the gate electrode becomes excessive, the gate insulating film tends to be destroyed.
In addition, the release of charge generated due to the application of excessive voltage is caused by MO
An input protection device is required because it affects the internal active elements of the S-type integrated circuit.

The most common conventional input protection devices include a diffused resistor (conductivity type opposite to that of the semiconductor substrate) connected to the input terminal, and a device that connects the charge generated by the excessive voltage applied to the input terminal to the ground wiring or power supply wiring. It is configured in combination with a MO3 type transistor that emits light. However, since the MO8 type transistor that constitutes the input protection device is formed in the same process as the internal MO3 element that constitutes the internal circuit, the gate insulating film of the MO3 type transistor of the input protection device is thin and its diffusion layer (source or drain) is thin. When a high voltage is applied to the gate electrode (which is formed in the same process as the diffused resistor), an excessive potential difference is generated between the gate electrode and its diffusion layer, and the gate insulating film is easily destroyed.

For the above reasons, recently, an input protection device as shown in the plan layout diagram of FIG. 3 has been used.

First, an overview of the configuration of this input protection device will be explained. One end of the high-concentration diffusion layer 22 of a conductivity type opposite to that of the semiconductor substrate is connected to two aluminum wirings serving as input terminals via an opening 28, and the other end is connected to a predetermined MO8 element (not shown). . - On the other hand, the high concentration diffusion layer 23 of the opposite conductivity type is
It is connected through the opening 28a to an aluminum wiring 30, which is a ground wiring or power supply wiring applied to a fixed potential. In the adjacent portions of the diffusion layers 22 and 23, low concentration wells 24 and 25 of conductivity type opposite to that of the semiconductor substrate are formed in regions including each, and the opposing portions of the low concentration wells 24 and 25 are spaced apart from each other by approximately 5 to 10 μm. have.

Next, the operation of this input protection device will be described. - In a typical operation, when an excessive voltage is applied to the aluminum wiring 29 which is an input terminal, the high concentration diffusion layer 2
The depletion layer formed in 2 expands, and the charges generated due to the application of excessive voltage are released from this depletion layer into the semiconductor substrate.
A part of it is released through the high concentration diffusion layer 23 to the aluminum wiring 30, which is a ground wiring or a power supply wiring.

Although the above-mentioned operation is also seen, the characteristic operation and main operation of this input protection device is as shown below. In the vicinity of the diffusion layers 22 and 23, an excessive voltage is applied to the aluminum wiring 29 and the high concentration diffusion layer 2
The depletion layer formed in the low concentration well 24 connected to 2 expands, and the charges generated by the application of an excessive voltage are released from this depletion layer into the semiconductor substrate. It contacts the depletion layer formed by the low concentration well 25 which is connected to the aluminum wiring 30 via the aluminum wiring 30, and is emitted to the aluminum wiring 30 using the contact between the two depletion layers as an electric path. In other words, this part operates as a punch-through type input protection device.

[Problem to be solved by the invention]

The input protection device for the conventional punch-through type MO8 integrated circuit described above protects against excessive voltage when an excessive voltage is applied to the input terminal.
The depletion layer of the low concentration well connected to the input terminal expands,
Charges generated due to the application of excessive voltage are released from the entire surface of this depletion layer. The depletion layer of the low concentration well connected to the aluminum wiring applied to a fixed potential is close to the depletion layer of the low concentration well connected to the input terminal only in some regions. Due to the expansion of the depletion layer of the concentration well, contact between the two depletion layers occurs only in this partial region. For this reason, most of the charges generated by the application of excessive voltage are released into the semiconductor substrate, and M
This will affect the internal active elements of the O8 type integrated circuit. Therefore, in order to reduce the influence on the internal active elements, the distance between the input protection device and the internal active elements must be set at several tens to hundreds of micrometers, which increases the chip area of the MO8 type integrated circuit. .

[Means to solve the problem]

The input protection device for an MO8 type integrated circuit according to the present invention includes first and second low concentration wells of opposite conductivity type and first and second low concentration wells of opposite conductivity type on a -conductivity type semiconductor substrate. It has a second high concentration diffusion layer, the first high concentration diffusion layer is connected to the input terminal and a predetermined MO8 element, a part of the first low concentration well and a part of the first high concentration diffusion layer. are formed in the same region, the second high concentration diffusion layer is applied with a fixed potential, a part of the second low concentration well and a part of the second high concentration diffusion layer are formed in the same region, Except for the region including the first high concentration diffusion layer, the second low concentration well has a structure in which the second low concentration well is formed surrounding the first low concentration well with a predetermined interval.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan layout diagram of one embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA' in FIG. 1.

On a P-type semiconductor substrate 1, an N-type low concentration well 4.5 and N-type high concentration diffusion layers 2 and 3 are formed. One end of the high concentration diffusion layer 2 is connected to an aluminum wiring 9, which is an input terminal, through an opening 8, and the other end is connected to a predetermined MO
It is connected to three elements (not shown). On the other hand, the high concentration diffusion layer 3 is connected to an aluminum wiring 10, which is a ground wiring or a power supply wiring, to which a fixed potential is applied through an opening 8a. Low-concentration wells 4.5 are formed in a region including each of the diffusion layers 2.3 in the vicinity of the diffusion layer 2.3, and low-concentration wells 5.
They are formed surrounding the low concentration well 4 with an interval of about 0 μm. A thick field oxide film 6 is formed on the semiconductor substrate 1 around the high concentration diffusion layer 2.3, and on the high concentration diffusion layer 2.3 and the field oxide film 6 except for the openings 8 and 8a. A thin insulating film 7 is formed.

In this embodiment, a low concentration well 4.5 is formed in a region including each of the diffusion layers 2.3 in the vicinity of the diffusion layer 2.3.
There are 5 to 10 low concentration wells 5, excluding the region including the diffusion layer 2.
They are formed surrounding the low-concentration well 4 with an interval of about μm, so when an excessive voltage is applied to the aluminum wiring 9 and the depletion layer of the low-concentration well 4 expands, it spreads over almost the entire circumference. It comes into contact with the depletion layer of the low concentration well 5.

In this example, in order to make the junction area of the depletion layer wider, N
Although a type low concentration well is used, a structure may be adopted in which the N type high concentration diffusion layer 3 surrounds the N type high concentration diffusion layer 2 over almost the entire circumference.

Furthermore, there is no problem even if the conductivity types of the semiconductor substrate, the high concentration diffusion layer, and the low concentration well are reversed.

〔Effect of the invention〕

As explained above, in the present invention, a low concentration well of a conductivity type opposite to that of the semiconductor substrate connected to an input terminal extends over almost the entire circumference; Since the input terminal is surrounded by a predetermined interval, if an excessive voltage is applied to the input terminal and the depletion layer of the low concentration well connected to the input terminal expands, this will cause the Contact with the depletion layer of the concentration well (this causes most of the charge generated by the application of an excessive voltage to be released to the low concentration well side, which is applied to a fixed potential), causing damage to the semiconductor substrate. The discharged charge is reduced, and the effect of this charge on the internal active elements of the MO8 type integrated circuit is reduced.

In addition, there is no need to provide a large distance between the input protection device and the internal active elements, which also eliminates the need to increase the chip area of the MO8 type integrated circuit.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a plan view Wt of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line A-A' in FIG.
FIG. 2 is a plan layout diagram of an input protection device for an O8 type integrated circuit. 1... Semiconductor substrate, 2, 3, 22. 23... High concentration diffusion layer, 4, 5. 24. 25... Low concentration well, 6.
...Field oxide film, 7...Insulating film, 8.8a. 28.28a--Opening, 9,10.29.30--
Aluminum wiring.

Claims (1)

[Scope of Claims] First and second low concentration wells of opposite conductivity type and first and second high concentration diffusion layers of opposite conductivity type are provided on a semiconductor substrate of one conductivity type, said first The high concentration diffusion layer is connected to the input terminal and a predetermined MOS
connected to an element, a portion of the first low concentration well and a portion of the first high concentration diffusion layer are formed in the same region, and a fixed potential is applied to the second high concentration diffusion layer; A part of the second low-concentration well and a part of the second high-concentration diffusion layer are formed in the same region, and except for the region including the first high-concentration diffusion layer, the second low-concentration well An input protection device for a MOS integrated circuit, characterized in that a well is formed surrounding the first low concentration well at a predetermined interval.