JPH04128940A - Emulator - Google Patents

Emulator

Info

Publication number
JPH04128940A
JPH04128940A JP2250855A JP25085590A JPH04128940A JP H04128940 A JPH04128940 A JP H04128940A JP 2250855 A JP2250855 A JP 2250855A JP 25085590 A JP25085590 A JP 25085590A JP H04128940 A JPH04128940 A JP H04128940A
Authority
JP
Japan
Prior art keywords
amplifier
evaluation
built
chip
evaluation chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2250855A
Other languages
Japanese (ja)
Inventor
Yasushi Masaike
政池 康史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP2250855A priority Critical patent/JPH04128940A/en
Publication of JPH04128940A publication Critical patent/JPH04128940A/en
Pending legal-status Critical Current

Links

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  • Microcomputers (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To protect an emulator from causing a failure in the built-in amplifier when the emulator is loaded with software by mounting the evaluation chip in the pin connector section of the connector. CONSTITUTION:Application set 8 is connected directly to the I/O of the evaluation chip by using the pin of evaluation mounting connector 1. Further, the evaluation chip is connected to the I/O of the emulation board via cable 2. With this, to the amplifier built in evaluation chip 7 a regular signal on the system is input without being affected by noise. Accordingly, the evaluation chip 7 including the built-in amplifier is allowed to carry out accurate evaluation. With this, software can be developed under the same environment as that where this product was mounted in an application set, and the condition never occurs that a failure of the built-in amplifier is found after the completion of the software.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はエミュレータに関し、特に微弱な信号専用の増
幅器を内蔵したタイプの入力端子を有するマイクロプロ
セッサのエミュレータに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an emulator, and more particularly to a microprocessor emulator having a type of input terminal incorporating an amplifier dedicated to weak signals.

〔従来の技術〕[Conventional technology]

従来この種のエミュレータは、応用セットとエミュレー
ションボードとコントローラの3つの装置を有し、ケー
ブルにより応用セットとエミュレーションボードが、ま
た、エミュレーションボードとコントローラがそれぞれ
接続されていた。
Conventionally, this type of emulator has three devices: an application set, an emulation board, and a controller, and the application set and emulation board are connected to each other by cables, and the emulation board and the controller are connected to each other by cables.

そして、エバリユエーションチップ(以下エバチップと
いうは、エミュレーションボード上にICコネクタで実
装された状態でソフトウェアの開発及びデバッグを行な
っていた。
Software was developed and debugged with an evaluation chip (hereinafter referred to as an evaluation chip) mounted on an emulation board using an IC connector.

第3図は従来の入力信号増幅器を内蔵した入力端子を有
するマイクロプロセッサソフト開発用エミュレータの構
成模式図である。
FIG. 3 is a schematic diagram of the configuration of a conventional emulator for microprocessor software development having an input terminal with a built-in input signal amplifier.

応用セット8から出力される微弱な信号は、接続ケーブ
ル2上で乗るノイズの影響を防ぐために外付増幅回路1
2により増幅された後ケーブル2を介、してエミュレー
ションボード15上のエバチップ7に入力される。
The weak signal output from the application set 8 is sent to the external amplifier circuit 1 to prevent the influence of noise on the connection cable 2.
After being amplified by 2, the signal is input to the evaluation chip 7 on the emulation board 15 via the cable 2.

但し、この入力信号はシステム上の正規の信号とは振幅
の異なるものとなっている。
However, this input signal has a different amplitude from the regular signal on the system.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のエミュレータにおいて、本製品のチップ及びエバ
チップに増幅器が内蔵されている場合、応用セットの出
力信号は微弱で電圧振幅が小さく、応用セットとエミュ
レーションボード間の接続ケーブル上でのノイズにより
エバチップが誤動作する為、応用セットから信号を出力
する時に別の外付増幅器等を用いて信号を増幅させる方
法をとっていた。
In conventional emulators, if this product's chip or evaluation chip has a built-in amplifier, the output signal of the application set is weak and the voltage amplitude is small, and the evaluation chip may malfunction due to noise on the connection cable between the application set and the emulation board. To do this, when outputting a signal from an application set, a separate external amplifier or the like was used to amplify the signal.

しかし、これでは実際の本製品のチップ上に内蔵された
増幅器の正常動作を確認することができないという欠点
があった。
However, this method had the disadvantage that it was not possible to confirm the normal operation of the amplifier built into the actual chip of this product.

又、このことは、ソフトウェア完成後本製品のチップに
ソフトウェアを搭載した時点で内蔵増幅器の不具合が発
見されるケースが多くなってしまう為、製品としての完
成時期に大きく影響を与える欠点であった。
In addition, this was a drawback that had a major impact on the completion time of the product, as there were many cases where defects in the built-in amplifier were discovered after the software was completed and the software was installed on the chip of this product. .

〔課題を解決するための手段〕[Means to solve the problem]

本発明のエミュレータはコネクタを用いて応用セットと
エミュレーションボードとを接続するケーブルとエバリ
ユエーションチップとを含むソフトウェア開発及びデバ
ッグ用のエミュレータにおいて、前記エバリユエーショ
ンチップを前記コネクタのビンコネクタ部に実装して構
成されている。
The emulator of the present invention is an emulator for software development and debugging that includes an evaluation chip and a cable that connects an application set and an emulation board using a connector, in which the evaluation chip is mounted in a bin connector part of the connector. It is configured as follows.

〔実施例〕〔Example〕

以下本発明の一実施例を図を参照して説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例の構成模式図、第2図(a)
、(b)は第1図のエバチップ実装コネクタのそれぞれ
正面図及び側面図である。
Figure 1 is a schematic diagram of the configuration of an embodiment of the present invention, Figure 2 (a)
, (b) are a front view and a side view, respectively, of the Eva chip mounting connector of FIG. 1.

応用セット8とエバチップとの入出力は、エバチップ実
装コネクタ1のビンにより直結される。
The input and output of the application set 8 and the EV chip are directly connected through the bin of the EV chip mounting connector 1.

またエバチップとエミュレーションボードとの入出力は
ケーブル2を介して接続される。
Further, the input/output between the evaluation chip and the emulation board is connected via a cable 2.

これによってエバチップ7に内蔵された増幅器には、ノ
イズの影響無しにシステム上の正規の信号が入力される
As a result, a normal signal on the system is inputted to the amplifier built in the evaluation chip 7 without being affected by noise.

従って、エバチップ7は、内蔵の増幅器を含めた正確な
エバリユエーションが行える。
Therefore, the evaluation chip 7 can perform accurate evaluation including the built-in amplifier.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、マイクロプロセッサ・の
ソフトウェア開発用エバチップを、応用セットとエミュ
レーションボードの接続ケーブルの応用セット側コネク
タに実装することにより、本製品を応用セット内に実装
した時と同じ環境でソフトウェアの開発ができ、ソフト
ウェア完成後に内部の入力信号増幅器の不具合が発見さ
れるようなことがなくなるという効果がある。
As explained above, the present invention can be implemented by mounting an evaluation chip for microprocessor software development on the application set side connector of the connection cable between the application set and the emulation board. This has the effect that software can be developed in the same environment, and that defects in the internal input signal amplifier will not be discovered after the software is completed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例の構成模式図、第2図(a
)、(b)は−第1図のエバチップ実装コネクタの、正
面図及び側面図、第3図は従来のマイクロプロセッサの
エミュレータの一例の構成模式1・・・エバチップ実装
コネクタ、2,4・・・接続ケーブル、3・・・エミュ
レーションボード、5・・・コントローラ、6・・・ピ
ン、7・・・エバチップ、12・・・外付増幅回路、1
5・・・エミュレーションボード。
FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, and FIG. 2 (a
), (b) are - front and side views of the EV chip mounting connector shown in FIG.・Connection cable, 3... Emulation board, 5... Controller, 6... Pin, 7... Eva chip, 12... External amplifier circuit, 1
5... Emulation board.

Claims (1)

【特許請求の範囲】[Claims] コネクタを用いて応用セットとエミュレーションボード
とを接続するケーブルとエバリュエーションチップとを
含むソフトウェア開発及びデバッグ用のエミュレータに
おいて、前記エバリュエーションチップを前記コネクタ
のピンコネクタ部に実装することを特徴とするエミュレ
ータ。
An emulator for software development and debugging that includes an evaluation chip and a cable that connects an application set and an emulation board using a connector, wherein the evaluation chip is mounted on a pin connector part of the connector. .
JP2250855A 1990-09-20 1990-09-20 Emulator Pending JPH04128940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2250855A JPH04128940A (en) 1990-09-20 1990-09-20 Emulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2250855A JPH04128940A (en) 1990-09-20 1990-09-20 Emulator

Publications (1)

Publication Number Publication Date
JPH04128940A true JPH04128940A (en) 1992-04-30

Family

ID=17214011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2250855A Pending JPH04128940A (en) 1990-09-20 1990-09-20 Emulator

Country Status (1)

Country Link
JP (1) JPH04128940A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100291728B1 (en) * 1996-07-09 2001-07-12 가네꼬 히사시 Emulation device with no fear of faulty operation due to noise

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100291728B1 (en) * 1996-07-09 2001-07-12 가네꼬 히사시 Emulation device with no fear of faulty operation due to noise

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