JPH04127468A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To flatten not only the substrate on which a BPSG film is formed as a layer insulating film, but also the surface of the BPSG film, by forming two kinds of trenches, a shallow and deep trenches, into a semiconductor substrate and forming a transfer gate so that the transfer gate can be buried in the shallow trench. CONSTITUTION:A shallow transfer gate trench 12 of about 400nm in depth is formed by subjecting a substrate to reactive sputter etching. Then a capacitive trench 6 of about 4mum in depth id formed etching the substrate. Then, after a phosphor-doped capacitive film 2 of polycrystalline silicon having a thickness of about 600nm is deposited on the entire surface of the substrate by a CVD method, a photoresist film 11d is formed on the surface of a desired area including the capacitive trench 6. After the film 11d is formed, a phosphor-doped polycrystalline silicon transfer gate film 4 of about 300nm in thickness is deposited on the entire surface by a CVD method. In addition, a photoresist film 11e for forming a transfer gate is formed by patterning the film 4. After the film 11e is formed, the film 4 is patterned by making reactive sputter etching by using the film 11e as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and particularly to a method of manufacturing a memory circuit portion of a trench type DRAM.

[Conventional technology]

The memory circuit section of a conventional trench-type DRAM has been formed through the following steps.

First, a mask layer is formed on the surface of a semiconductor substrate, and a field oxide film is selectively formed.

Next, a photoresist film serving as a mask for trench etching is formed, and a trench serving as a trench-type capacitor portion is formed in the semiconductor substrate by reactive sputter etching.

Next, boron is ion-implanted into the inner wall of the groove, and arsenic is ion-implanted into the inner wall of the groove and around the opening of the groove, and an oxide film is deposited on the surface of the semiconductor substrate and the inner wall of the groove. Further, a phosphorus-doped polycrystalline silicon film is deposited and processed so as to fill only the inside of the groove.

Next, a gate oxide film is formed, boron ions are implanted,
Furthermore, a phosphorus-doped polycrystalline silicon film is deposited again, and a transfer gate made of this phosphorus-doped polycrystalline silicon film is formed by photolithography. Subsequently, arsenic ions are implanted using the transfer gate as a mask to form a diffusion layer.

Next, a BPSG film as an interlayer insulating film is deposited on the entire surface,
A contact groove leading to the diffusion layer is formed in the BPSG film using photolithography technology, and a WSi film is deposited and processed to form the WS.
Digit lines made of i film are formed and trench type DRA
A memory circuit section of M is formed.

[Problem to be solved by the invention]

However, in the conventional method for manufacturing a semiconductor integrated circuit device described above, a transfer gate made of a phosphorus-doped polycrystalline silicon film is formed on a semiconductor substrate, and a BPSG film is formed as an interlayer insulating film on top of the transfer gate, so that digit lines and arsenic The depth of the contact groove for making contact with the diffusion layer formed by ion implantation becomes deeper, and the shape of the contact groove sidewalls and bottom of the WSi film that becomes the digit line deteriorates, resulting in digit line disconnection, etc. A problem occurs.

An object of the present invention is to eliminate the above-mentioned drawbacks, to reduce the depth of the contact groove for making contact between the digit line and the diffusion layer formed by arsenic ion implantation, and to reduce the depth of the contact groove on the sidewalls and bottom of the contact groove. An object of the present invention is to provide a method for forming a memory circuit portion of a trench type DRAM that improves the shape of a WSi film.

[Means to solve the problem]

A method of manufacturing a semiconductor integrated circuit device according to the present invention is a method of manufacturing a memory circuit portion of a trench-type DRAM, and includes the steps of: forming shallow grooves and deep grooves extending from the surface to the inside in a semiconductor substrate; and forming the surface of the semiconductor substrate and the shallow grooves. and forming an insulating film on the inner wall of the deep trench, implanting boron and arsenic ions into the deep trench, implanting boron ions into the shallow trench, and forming a phosphorous-doped polycrystalline silicon film on the surface of the semiconductor substrate. depositing the phosphorus-doped polycrystalline silicon film and filling the insides of the shallow groove and the deep groove with the phosphorus-doped polycrystalline silicon film; and etching the phosphorus-doped polycrystalline silicon film so that the phosphorus-doped polycrystalline silicon film is deposited only inside the shallow groove and the deep groove. A step of leaving a silicon film and using the shallow trench as a transfer gate and the deep trench as a capacitor, a step of depositing a BPSG film as an interlayer insulating film over the entire surface, and forming a free trench in a predetermined portion of the BPSG film. and a step of forming a digit line.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(j) are step-by-step sectional views for explaining a first embodiment of the present invention.

First, a photoresist film 11a is formed on a semiconductor substrate on which a field oxide film 1 of about 800 nm is formed (FIG. 1(a)), and the semiconductor substrate is etched to a depth of about 400 nm by reactive sputter etching. A shallow transfer gate groove 12 is formed [FIG. 1(b)].

Next, after peeling off the photoresist film 11a, a mask nitride film 13 with a thickness of about 10 nm is deposited over the entire surface of the semiconductor substrate by CVD. Subsequently, the mask nitride film 13 is buttered by reactive sputter etching using the photoresist film 11b as a mask [FIG. 1(C)].

Next, after peeling off the photoresist film 11b, the semiconductor substrate is etched by reactive sputter etching using the photoresist film 11c as a mask to form a capacitive groove 6 with a depth of about 4 μm. Next, photoresist M 11
Using c as a mask, boron ions are implanted into the side walls of the capacitive trench 6 to form a boron diffusion layer 7 [Fig. 1(d)]
].

Next, after peeling off the photoresist film 11c, using the mask nitride film 13 as a mask, the side walls of the capacitive trench 6 and the capacitive trench 6 are
Arsenic ions are implanted around the opening to form a capacitive arsenic diffusion layer 7a of HI-C structure [FIG. 1(e)].

Next, after removing the mask nitride film 13 by wet etching, a groove oxide film 14 of about 15 nm is formed by thermal oxidation. Subsequently, a phosphorus-doped capacitive polycrystalline silicon film 2 of about 600 nm is deposited on the entire surface by CVD, and a photoresist film li covering desired regions including the capacitive groove 6 is formed.
d [Fig. 1(f)].

Next, the capacitive polycrystalline silicon film 2 is patterned using the photoresist film lid as a mask, and then the photoresist film lid is peeled off. The trench oxide film 14 is also removed by patterning at this time. Subsequently, boron ions are implanted for vth control, and a gate oxide film 9 with a thickness of 20 nm is formed by thermal oxidation on the exposed surface of the semiconductor substrate and the surface of the capacitive polycrystalline silicon film 2. After that, CVD
A phosphorus-doped transfer gate polycrystalline silicon film 4 of about 300 nm is deposited on the entire surface by a method. Furthermore, the transfer gate polycrystalline silicon film 4 is patterned to form a photoresist film lie for forming a transfer gate [FIG. 1(g)].

Next, the transfer gate polycrystalline silicon film 4 is patterned by reactive sputter etching using the photoresist film lie as a mask.

By this etching, the transfer gate groove 12 is
It is filled with a transfer gate polycrystalline silicon film 4. Subsequently, after separating the photoresist film lie f#J, using the transfer gate polycrystalline silicon film 4 as a mask, arsenic ions are implanted to form a contact diffusion m8 in the gap between the transfer gate grooves 12. [
Figure 1 (h)).

Next, a BPSG film 3 having a thickness of about 600 nm is deposited over the entire surface. Subsequently, a photoresist film 11f having a pattern covering areas other than the contact diffusion layer 8 is formed [FIG. 1(i)].

Next, using the photoresist film if as a mask, BPSG
The film 3 is etched to form a contact groove 10. Subsequently, after peeling off the photoresist film iff, a WSi film 5 is deposited on the entire surface [Fig. 1 (j)], and this is patterned using photolithography technology to form digit lines, forming a memory circuit of a trench type DRAM. part is formed.

FIGS. 2(a) to 2(h) are step-by-step sectional views for explaining a second embodiment of the present invention.

First, a field oxide film 1 of about 600 nm is formed [
A photoresist film 11g is formed on the semiconductor substrate shown in FIG. 2(a), and the semiconductor substrate is etched by reactive sputter etching to form a shallow transfer gate groove 12a with a depth of about 400 nm (see FIG. 2(a)). b)].

Next, after peeling off the photoresist film 11g, boron ions are implanted for Vth control, and a gate oxide film 9a having a thickness of 20 nm is formed by thermal oxidation on the exposed surface of the semiconductor substrate. Next, the entire surface is coated with 300% by CVD method.
A phosphorus-doped transfer gate polycrystalline silicon film 4a having a thickness of approximately nm is deposited. Further, the transfer gate polycrystalline silicon film 4a is patterned to form a photoresist film 11h for forming a transfer gate [FIG. 2(C)].

Next, the transfer gate polycrystalline silicon film 4a is patterned by reactive sputter etching using the photoresist film 11h as a mask. As a result of this etching, transfer gate trench 12a is filled with transfer gate polycrystalline silicon film 4a. Subsequently, after peeling off the photoresist film 11h, the semiconductor substrate is etched by reactive sputter etching using the photoresist film 111 as a mask to form a capacitive groove 6 with a depth of approximately 4 μm.
form. Next, using the photoresist film 11i as a mask, boron ions are implanted into the side walls of the capacitive groove 6 to form a boron diffusion layer 7 [FIG. 2(d)].

Next, after peeling off the photoresist film 11i, arsenic ions are implanted using the transfer gate polycrystalline silicon film 4a as a mask, and a HI-C structure is formed on the side walls of the capacitor trench 6 and around the opening of the capacitor trench 6. At the same time as forming the arsenic diffusion layer 7a, a contact diffusion layer 8 is formed in the gap between the transfer gate grooves 12a [FIG. 2(e)].

Next, a trench oxide film 14a having a thickness of about 15 nm is formed by thermal oxidation on the side wall surface of the capacitive trench 6, the peripheral surface of the opening of the capacitive trench 6, and the surface of the transfer gate polycrystalline silicon film 4a. Subsequently, a phosphorus-doped capacitive polycrystalline silicon film 2 of about 600 nm is deposited on the entire surface by CVD, and a photoresist film 1 is formed to cover desired regions including the capacitive trench 6a.
1j [Fig. 2(f)].

Next, using the photoresist film ILj as a mask, the transfer gate polycrystalline silicon film 4a is selectively etched, and then the photoresist film 11j is peeled off. Subsequently, a BPSG film 3 having a thickness of about 600 nm is deposited on the entire surface. Subsequently, a photoresist film 11k having a pattern covering areas other than the contact diffusion layer 8 is formed [see FIG.
g)].

Next, using the photoresist film 11k as a mask, the BPSG
The film 3 is etched to form a contact groove 10. Subsequently, after peeling off the photoresist film 11k, a WSi film 5 is deposited on the entire surface (FIG. 2(h)), and this is patterned using photolithography to form digit lines, forming a memory circuit of a trench type DRAM. part is formed.

This embodiment has better overall flatness than the first embodiment and is more advantageous than the first embodiment in forming and etching a photoresist film pattern.

〔Effect of the invention〕

The present invention described above forms two types of grooves, shallow grooves and deep grooves, on the surface of a semiconductor substrate, and forms a BPSG film as an interlayer insulating film by forming a transfer gate in the shallow groove portion. At the same time as the base is planarized, the surface of the BPSG film is also planarized, the step difference of the contact trench of the digit line with respect to the diffusion layer of the transfer transistor is alleviated, and the shape of the digit line in the contact trench portion is improved. This eliminates problems such as disconnection of the digit line at this portion.

[Brief explanation of the drawing]

FIGS. 1(a)" to (j) are step-by-step sectional views for explaining the first embodiment of the present invention, and FIGS. 2(a) to (h) are sectional views of the second embodiment of the present invention. It is a sectional view in the order of steps for explanation. 1... Field oxide film, 2... Capacitive polycrystalline silicon film, 3... BPSG film, 4.4a... Transfer gate polycrystalline silicon film, 5 ...WSi film, 6...
・Capacitance trench, 7...Boron diffusion layer, 7a...Capacitance arsenic diffusion layer, 8...Contact diffusion layer, 9, 9a...Gate oxide film, 10:I contact trench, lla, flb
. lie, 11d+ lie, llf, l1g, 11h
, lli, llj, llk...photoresist film, 1
2, 12a... Transfer gate trench, 13... Mask nitride film, 14.14a... Groove oxide film.

Claims (1)

[Scope of Claims] A method for manufacturing a memory circuit portion of a trench-type DRAM, comprising: forming shallow grooves and deep grooves inward from a surface of a semiconductor substrate; forming an insulating film; implanting boron and arsenic ions into the deep trench; implanting boron ions into the shallow trench; depositing a phosphorus-doped polycrystalline silicon film on the surface of the semiconductor substrate; filling the inside of the trench and the deep trench with the phosphorus-doped polycrystalline silicon film; etching the phosphorus-doped polycrystalline silicon film to leave the phosphorus-doped polycrystalline silicon film only inside the shallow trench and the deep trench; A step of using the trench as a transfer gate and using the deep trench as a capacitor, a step of depositing a BPSG film as an interlayer insulating film over the entire surface, a step of forming a contact trench in a predetermined portion of the BPSG film, and a step of forming a digit line. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: