JPH04127450A - Manufacture of lead frame and semiconductor device - Google Patents

Manufacture of lead frame and semiconductor device

Info

Publication number
JPH04127450A
JPH04127450A JP24957090A JP24957090A JPH04127450A JP H04127450 A JPH04127450 A JP H04127450A JP 24957090 A JP24957090 A JP 24957090A JP 24957090 A JP24957090 A JP 24957090A JP H04127450 A JPH04127450 A JP H04127450A
Authority
JP
Japan
Prior art keywords
pitch
leads
outer leads
lead
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24957090A
Other languages
Japanese (ja)
Inventor
Yuichi Asano
祐一 浅野
Kenji Kobayashi
賢司 小林
Fumihito Takahashi
高橋 文仁
Hitoshi Kobayashi
均 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Miyagi Electronics Ltd
Original Assignee
Fujitsu Miyagi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Miyagi Electronics Ltd filed Critical Fujitsu Miyagi Electronics Ltd
Priority to JP24957090A priority Critical patent/JPH04127450A/en
Publication of JPH04127450A publication Critical patent/JPH04127450A/en
Pending legal-status Critical Current

Links

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To easily bring outer leads into contact with a package and, at the same time, to prevent the deformation of the outer leads by arraying the root sections of the outer leads which are brought into contact with the package at the prescribed first pitch and the leading end sections of the outer leads extended from the root sections at the second pitch which is wider than the first pitch. CONSTITUTION:Outer leads 3 are arranged in such a way that their root sections 3A of a prescribed length are arranged at a hyperfine pitch (p) (0.3 or 0.4mm) and their leading end sections 3b are arranged at the conventional pitch P (for example, 1mm). A polyimide tape 4 is stuck to the leading end sections 3B and fixes the leads 3. The final test is performed by using the leading end sections 3B of the outer leads 3 while the leads 3 are attached to a lead frame and, after the final test is made, the outer leads 3 are cut off from the position shown by dotted lines and the leading end sections 3B arranged at wider pitch are removed. Thereafter, the leads are bent into their final forms.

Description

【発明の詳細な説明】 〔概要〕 リードフレームおよびそれを用いた超微細ピッチの半導
体装置の製造方法に関し。
DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a lead frame and a method for manufacturing an ultra-fine pitch semiconductor device using the lead frame.

超微細ピッチのデバイスの最終試験において。In final testing of ultra-fine pitch devices.

アウタリードとの接触を容易にしかつアウタリードの変
形を防止することを目的とし。
The purpose is to facilitate contact with the outer lead and prevent deformation of the outer lead.

l)一端がチップに電気的に接続された複数のリードが
封止された構造のパッケージにおいて、該リードは封止
されるインナリード部と封止部から外部に突き出したア
ウタリード部からなり、該アウタリード部のパッケージ
に接する付け根部分は所定の第1のピッチで配列され、
該付け根部分より延在する該アウタリードの先端部は該
第1のピッチより広い第2のピッチで配列されているよ
うに構成する。
l) In a package having a sealed structure in which a plurality of leads are electrically connected to the chip at one end, the leads consist of an inner lead portion to be sealed and an outer lead portion protruding from the sealing portion to the outside. The base portion of the outer lead portion that contacts the package is arranged at a predetermined first pitch,
The tips of the outer leads extending from the base portion are arranged at a second pitch that is wider than the first pitch.

2)請求項1記載のリードフレームから前記アウタリー
ドと共に前記パッケージを切り離した後。
2) After separating the package together with the outer lead from the lead frame according to claim 1.

該アウタリードの先端部を用いて特性測定を行う工程と
、その後前記第2のピッチで配列されたアウタリードの
先端部を除去する工程とを有するように構成する。
The method is configured to include a step of measuring characteristics using the tips of the outer leads, and a step of removing the tips of the outer leads arranged at the second pitch.

3)前記アウタリードの先端部が粘着テープで固定され
ているように構成する。
3) The tip of the outer lead is fixed with an adhesive tape.

〔産業上の利用分野〕[Industrial application field]

本発明はリードフレームおよびそれを用いた超微細ピッ
チの半導体装置の製造方法に関する。
The present invention relates to a lead frame and a method of manufacturing an ultra-fine pitch semiconductor device using the lead frame.

近年、 SMD (Surface Mounting
 Device :表面実装デバイス)パッケージの利
用は著しく拡大され。
In recent years, SMD (Surface Mounting)
The use of surface mount device (Device) packages has expanded significantly.

より小型化を求めてアウタリードのピッチが0.3ある
いは0.4mmピッチのフラットパッケージのデバイス
が開発されている。
In pursuit of further miniaturization, flat package devices with outer leads having a pitch of 0.3 or 0.4 mm have been developed.

それに伴い、これらのデバイスの組み立て工程終了後に
デバイスの特性を測定する最終試験をどのように行うか
、またその際のリードの変形をいかに抑えるかが課題と
なっている。
Along with this, issues have arisen as to how to conduct a final test to measure the characteristics of these devices after the assembly process is completed, and how to suppress deformation of the leads at that time.

具体的には、0.3mmピッチ級のデバイス用の試験ソ
ケットの作製が困難である。
Specifically, it is difficult to manufacture test sockets for devices with a pitch of 0.3 mm.

本発明は上記課題を満足するリードフレームを用いて、
超微細ピッチのデバイスの製造方法として利用できる。
The present invention uses a lead frame that satisfies the above problems, and
It can be used as a method for manufacturing ultra-fine pitch devices.

〔従来の技術〕[Conventional technology]

従来、フラットパッケージのデバイスの最終試験は、デ
バイスのアウタリードが変形しないようにキャリア等の
治具に装着して行っているが、この場合、キャリアの脱
着時にはアウタリードの変形を起こすとともに、脱着工
数が大変である。
Conventionally, the final test of flat package devices is performed by mounting the outer leads of the device on a jig such as a carrier to prevent deformation, but in this case, the outer leads may be deformed when the carrier is attached and detached, and the number of man-hours required for attachment and detachment is increased. It's difficult.

さらに、0.3あるいは0.4mmピッチ級のデバイス
になると、測定接触子そのものが正確にアウタリードに
接続するのが困難である。
Furthermore, for devices with a pitch of 0.3 or 0.4 mm, it is difficult to accurately connect the measurement contact itself to the outer lead.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来技術の上記欠点に対処して9本発明は超微細ピッチ
のデバイスの最終試験において、アウタリードとの接触
を容易にしかつアウタリードの変形を防止することを目
的とする。
Addressing the above-mentioned shortcomings of the prior art, the present invention aims to facilitate contact with the outer leads and prevent deformation of the outer leads during final testing of ultra-fine pitch devices.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題の解決は。 What is the solution to the above problem?

■)一端がチップに電気的に接続された複数のリードが
封止された構造のパッケージにおいて、該リードは封止
されるインナリード部と封止部から外部に突き出したア
ウタリード部からなり、該アウタリード部のパッケージ
に接する付け根部分は所定の第1のピッチで配列され、
皺付け根部分より延在する該アウタリードの先端部は該
第1のピッチより広い第2のピッチで配列されているリ
ードフレーム、あるいは 2)前記l)記載のリードフレームから前記アウタリー
ドと共に前記パッケージを切り離した後。
(2) In a package with a sealed structure in which a plurality of leads are electrically connected to the chip at one end, the leads consist of an inner lead portion to be sealed and an outer lead portion protruding from the sealing portion to the outside. The base portion of the outer lead portion that contacts the package is arranged at a predetermined first pitch,
The tips of the outer leads extending from the wrinkle root portions are arranged in a lead frame arranged at a second pitch wider than the first pitch, or 2) the package is separated together with the outer leads from the lead frame described in l) above. After.

該アウタリードの先端部を用いて特性測定を行う工程と
、その後前記第2のピッチで配列されたアウタリードの
先端部を除去する工程とを有する半導体装置の製造方法
、あるいは 3)前記アウタリードの先端部が粘着テープで固定され
ている前記2)記載の半導体装置の製造方法により達成
される。
A method for manufacturing a semiconductor device, comprising the steps of measuring characteristics using the tips of the outer leads, and then removing the tips of the outer leads arranged at the second pitch, or 3) the tips of the outer leads. This is achieved by the method for manufacturing a semiconductor device described in 2) above, in which the semiconductor device is fixed with an adhesive tape.

〔作用〕[Effect]

本発明では、最終試験は従来と同様の大きいアウタリー
ドピッチで行い、その後、リードを加工して本来の超微
細ピッチのデバイスにしている。
In the present invention, the final test is performed with a large outer lead pitch similar to the conventional one, and then the leads are processed to form a device with the original ultra-fine pitch.

従って、測定時すべてのアウタリードへの測定接触子の
接続は容易であり、また微細化されない従来ピッチで測
定できるためリードの変形も低減できる。
Therefore, it is easy to connect the measurement contacts to all the outer leads during measurement, and deformation of the leads can be reduced because measurements can be made at conventional pitches that are not miniaturized.

〔実施例〕〔Example〕

第1図は本発明の一実施例を説明する平面図である。 FIG. 1 is a plan view illustrating an embodiment of the present invention.

図において、1はリードフレーム、2はパッケージ、3
はアウタリード、4は粘着テープでボリイミドテープで
ある。
In the figure, 1 is a lead frame, 2 is a package, and 3 is a lead frame.
is an outer lead, and 4 is an adhesive tape made of polyimide tape.

図は、樹脂モールドにより封止を終えた状態を示す。組
み立ての個々の工程は通常のものであるためここでは記
載を省略する。
The figure shows the state after sealing with the resin mold. Since the individual assembly steps are conventional, their description will be omitted here.

アウタリード3は付け根の所定長さの部分3Aは本来の
超微細ピッチp (0,3または0.4mm)で配列さ
れ、先端部3Bは従来のピッチP(例えば。
In the outer lead 3, a portion 3A of a predetermined length at the base is arranged at the original ultra-fine pitch P (0, 3 or 0.4 mm), and a tip portion 3B is arranged at the conventional pitch P (for example, 0.3 or 0.4 mm).

1mm)で配列されている。1 mm).

ポリイミドテープ4は先端部3Bに貼付してリードを固
定している。
A polyimide tape 4 is attached to the tip 3B to fix the lead.

最終試験は、リードフレームのままアウタリード3の先
端部3Bを用いて行い、最終試験後9点線の位置でアウ
タリード3を切断し、拡大ピッチの先端部3Bを除去す
る。
The final test is carried out using the tip portion 3B of the outer lead 3 with the lead frame intact, and after the final test, the outer lead 3 is cut at the 9-dot line position and the enlarged pitch tip portion 3B is removed.

その後、第2図に示される最終形態のようにリード曲げ
を行う。
Thereafter, the leads are bent as shown in the final form shown in FIG.

第2図(a)、 (b)は超微細ピッチデバイスの最終
形態を示す平面図と側面図である。
FIGS. 2(a) and 2(b) are a plan view and a side view showing the final form of the ultrafine pitch device.

このような リードフレームlはつぎのような特徴を持
っている。
This type of lead frame l has the following characteristics.

■ 樹脂封止後、アウタリード3はリードフレームから
切り離されるため、アウタリードの先端部とリードフレ
ームは接続していないので、特性測定が可能となる。
(2) After resin sealing, the outer lead 3 is separated from the lead frame, so the tip of the outer lead and the lead frame are not connected, making it possible to measure the characteristics.

■ アウタリードの先端部がポリイミドテープで固定さ
れているため、リード部を固定する特別の方法は不要で
ある。
■ Since the tips of the outer leads are fixed with polyimide tape, no special method is required to fix the leads.

■ リード曲げ工程が組み立ての最終工程であるため、
リード変形の機会が少ない。
■ Since the lead bending process is the final process of assembly,
There is little chance of lead deformation.

■ 最終試験はアウタリードの先端部を用いて行うため
、超微細ピッチデバイスであるにもかかわらず、試験ソ
ケットや接触子等の高精度化が不要である。
■ Since the final test is performed using the tip of the outer lead, there is no need for high precision test sockets or contacts, even though it is an ultra-fine pitch device.

■ 従来技術の延長で、超微細ピッチのデバイスの組み
立てができる。
■ By extending conventional technology, it is possible to assemble ultra-fine pitch devices.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、超微細ピッチのデ
バイスの最終試験において、アウタリードとの接触を容
易にしかつアウタリードの変形を防止することができた
As explained above, according to the present invention, it was possible to facilitate contact with the outer lead and prevent deformation of the outer lead in the final test of a device with an ultra-fine pitch.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を説明する平面図。 第2図(a)、 (b)は超微細ピッチデバイスの最終
形態を示す平面図と側面図である。 図において。 ■はリードフレーム。 2はパッケージ。 3はアウタリード。 4はポリイミドテープ にブチ1ニイラ゛[の5f−イ5t)2篇 図
FIG. 1 is a plan view illustrating an embodiment of the present invention. FIGS. 2(a) and 2(b) are a plan view and a side view showing the final form of the ultrafine pitch device. In fig. ■ is a lead frame. 2 is the package. 3 is outer lead. 4 is a polyimide tape with 1 piece and 2 pieces (5f-5t)

Claims (1)

【特許請求の範囲】 1)一端がチップに電気的に接続された複数のリードが
封止された構造のパッケージにおいて、該リードは封止
されるインナリード部と封止部から外部に突き出したア
ウタリード部からなり、該アウタリード部のパッケージ
に接する付け根部分は所定の第1のピッチで配列され、
該付け根部分より延在する該アウタリードの先端部は該
第1のピッチより広い第2のピッチで配列されているこ
とを特徴とするリードフレーム。 2)請求項1記載のリードフレームから前記アウタリー
ドと共に前記パッケージを切り離した後、該アウタリー
ドの先端部を用いて特性測定を行う工程と、 その後前記第2のピッチで配列されたアウタリードの先
端部を除去する工程 とを有することを特徴とする半導体装置の製造方法。 3)前記アウタリードの先端部が粘着テープで固定され
ていることを特徴とする請求項2記載の半導体装置の製
造方法。
[Claims] 1) In a package having a sealed structure in which a plurality of leads are electrically connected to a chip at one end, the leads protrude outside from the sealed inner lead part and the sealed part. consisting of an outer lead portion, the base portion of the outer lead portion in contact with the package is arranged at a predetermined first pitch;
A lead frame characterized in that tip portions of the outer leads extending from the base portion are arranged at a second pitch that is wider than the first pitch. 2) After separating the package together with the outer leads from the lead frame according to claim 1, measuring the characteristics using the tips of the outer leads, and then measuring the tips of the outer leads arranged at the second pitch. 1. A method for manufacturing a semiconductor device, comprising the step of removing. 3) The method of manufacturing a semiconductor device according to claim 2, wherein a tip end of the outer lead is fixed with an adhesive tape.
JP24957090A 1990-09-18 1990-09-18 Manufacture of lead frame and semiconductor device Pending JPH04127450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24957090A JPH04127450A (en) 1990-09-18 1990-09-18 Manufacture of lead frame and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24957090A JPH04127450A (en) 1990-09-18 1990-09-18 Manufacture of lead frame and semiconductor device

Publications (1)

Publication Number Publication Date
JPH04127450A true JPH04127450A (en) 1992-04-28

Family

ID=17194968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24957090A Pending JPH04127450A (en) 1990-09-18 1990-09-18 Manufacture of lead frame and semiconductor device

Country Status (1)

Country Link
JP (1) JPH04127450A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669410A (en) * 1992-08-17 1994-03-11 Nec Yamagata Ltd Manufacture of semiconductor device
JPH07169902A (en) * 1993-12-16 1995-07-04 Nec Corp Semiconductor device
JP2006253719A (en) * 2002-02-01 2006-09-21 Sharp Corp Manufacturing method for semiconductor laser apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669410A (en) * 1992-08-17 1994-03-11 Nec Yamagata Ltd Manufacture of semiconductor device
JPH07169902A (en) * 1993-12-16 1995-07-04 Nec Corp Semiconductor device
JP2006253719A (en) * 2002-02-01 2006-09-21 Sharp Corp Manufacturing method for semiconductor laser apparatus

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