JPH04127157A - Production of semiconductor element - Google Patents
Production of semiconductor elementInfo
- Publication number
- JPH04127157A JPH04127157A JP24713290A JP24713290A JPH04127157A JP H04127157 A JPH04127157 A JP H04127157A JP 24713290 A JP24713290 A JP 24713290A JP 24713290 A JP24713290 A JP 24713290A JP H04127157 A JPH04127157 A JP H04127157A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- dry etching
- forming
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 238000005253 cladding Methods 0.000 claims 2
- 150000001875 compounds Chemical class 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 239000011368 organic material Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- LLZRNZOLAXHGLL-UHFFFAOYSA-J titanic acid Chemical compound O[Ti](O)(O)O LLZRNZOLAXHGLL-UHFFFAOYSA-J 0.000 abstract description 2
- 238000003491 array Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000003377 silicon compounds Chemical class 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体レーザあるいはアレーの活性層を含む発
光領域にドライエツチングマスクを介してドライエツチ
ング加工を行なう方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of dry etching a light emitting region including an active layer of a semiconductor laser or array through a dry etching mask.
従来の半導体レーザの共振器端面をドライエッチ加工で
作製するには三層構造(上層レジスト。Conventional semiconductor laser cavity end faces are fabricated using dry etching to create a three-layer structure (upper layer resist.
中間層、Ti蒸着膜、下層レジスト)からなるマスクを
介して行なっていた。しかし上層レジストマスク作製時
にストリエーションおよび定在波の影響で積層状の横じ
まが発生し、これがレーザ共振器端面まで転写され、反
射率を減少させる大きな原因となっていた。This was done through a mask consisting of an intermediate layer, a Ti vapor deposited film, and a lower resist layer. However, during the fabrication of the upper resist mask, layered horizontal stripes occur due to the effects of striations and standing waves, which are transferred to the laser resonator end face and become a major cause of a decrease in reflectance.
上記従来技術は上層レジストのストリエーションおよび
定在波の点について配慮がされておらず半導体レーザお
よびレーザアレーの作製において活性層を含む凸部から
なる発光領域の端面と側面をドライエッチする場合にス
トリエーションおよび定在波の影響で積層状の横じまが
転写され、反射率を減少させる問題があった。The above conventional technology does not take into account the striations and standing waves of the upper resist layer, and when dry etching the end and side surfaces of the light emitting region consisting of convex parts including the active layer in the fabrication of semiconductor lasers and laser arrays, There was a problem in that the laminated horizontal stripes were transferred due to the influence of vibration and standing waves, reducing the reflectance.
上記目的を達成するために本発明は、最上層ホトレジス
トマスクを高温加熱処理することにより、ストリエーシ
ョンおよび定在波の影響による積層状の横じま凹凸を解
消した最上層マスクを得る。In order to achieve the above object, the present invention subjects the top layer photoresist mask to a high temperature heat treatment to obtain a top layer mask in which laminated horizontal striped irregularities caused by striations and standing waves are eliminated.
上記のレジストマスクを用いて、中間層および下層レジ
ストをドライエツチングして、パターンエツジにストリ
エーションのない、シャープなドライエツチング用マス
クを製作する。その後、下層レジストをマスクにして、
活性層を含む発光領域をトライエッチして、垂直側面・
端面を有する平滑なストライプ状のメサを形成すること
が可能となり、導波路および端面の加工精度が向上する
ので、すぐれた特性を持つ、半導体レーザおよびアレー
を製作することが出来る。Using the above resist mask, the intermediate layer and lower layer resist are dry etched to produce a sharp dry etching mask with no striations at pattern edges. After that, use the lower resist as a mask,
Tri-etch the light-emitting region including the active layer to remove vertical side surfaces and
It becomes possible to form a smooth striped mesa having an end face, and the processing accuracy of the waveguide and end face is improved, making it possible to manufacture semiconductor lasers and arrays with excellent characteristics.
以下本発明の一実施例を第1図から第3図により説明す
る。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
InP半導体基板1上に第1層ホトレジスト層2を2μ
m乃至10μmの厚さで形成した(第1図(a))。こ
こで第1層ホトレジスト層2には0FPR800(東京
応化社:商品名)を用いた。A first photoresist layer 2 with a thickness of 2 μm is deposited on an InP semiconductor substrate 1.
The film was formed with a thickness of m to 10 μm (FIG. 1(a)). Here, 0FPR800 (Tokyo Ohka Co., Ltd.: trade name) was used for the first photoresist layer 2.
230℃で20分間熱処理した。次にケイ素化合物であ
る○CD(東京応化社:商品名)にオルトチタン酸を混
合した溶液を回転塗布し、230℃で20分間熱処理し
、第1図(b)に示すように中間層3を0.08μmの
膜厚で形成した。その後、上層ホトレジスト膜を1μm
の厚さで形成し、縮小投影装置で露光して第1図(c)
に示すようなパターン4を形成した。Heat treatment was performed at 230°C for 20 minutes. Next, a solution containing orthotitanic acid was spin-coated onto the silicon compound ○CD (Tokyo Ohka Co., Ltd.: trade name), and heat treated at 230°C for 20 minutes to form the intermediate layer 3 as shown in Figure 1(b). was formed with a film thickness of 0.08 μm. After that, the upper layer photoresist film was coated with a thickness of 1 μm.
1(c) and exposed with a reduction projection device.
A pattern 4 as shown in FIG.
しかし上層ホトレジスト層には第2図(a)に示すよう
なストリエーション5および定在波の影響で積層状の横
じま6が発生する。ストリエーションおよび定在波の影
響による積層状の横じまは170℃で20分間加熱処理
することにより、第2図(b)7に示すように解消出来
た。However, in the upper photoresist layer, striations 5 as shown in FIG. 2(a) and horizontal stripes 6 in a laminated manner are generated due to the influence of standing waves. The laminated horizontal stripes caused by striations and standing waves could be eliminated by heat treatment at 170° C. for 20 minutes, as shown in FIG. 2(b) 7.
中間層のケイ素化合物はCHF、とC2F、の混合ガス
によるドライエッチ加工により上層ホトレジストパター
ン4を中間層3に転写し第3図(a)に示すようなパタ
ーン3′を形成した。次に02ガスにより下層ホトレジ
スト層3にパターン3′をドライエッチ加工により転写
し、第3図(b)に示すように垂直性にすぐれたドライ
エツチングマスク2′を得た。このドライエツチングマ
スクは幅1μm、長さ100μm、高さ3μm、ストリ
エーション±0.01μm以下の高精度なホトレジパタ
ーンを得た。For the silicon compound of the intermediate layer, the upper photoresist pattern 4 was transferred to the intermediate layer 3 by dry etching using a mixed gas of CHF and C2F to form a pattern 3' as shown in FIG. 3(a). Next, the pattern 3' was transferred to the lower photoresist layer 3 by dry etching using 02 gas to obtain a dry etching mask 2' with excellent verticality as shown in FIG. 3(b). This dry etching mask yielded a highly accurate photoresist pattern with a width of 1 μm, a length of 100 μm, a height of 3 μm, and a striation of ±0.01 μm or less.
その後第3図(c)に示すように垂直なパターン2′を
マスクとしてCQ2ガスにより、基板1をドライエッチ
加工し、ストリエーションおよび定在波の横じまの影響
のない深さ5から10μm。Thereafter, as shown in FIG. 3(c), the substrate 1 is dry-etched using CQ2 gas using the vertical pattern 2' as a mask to a depth of 5 to 10 μm without the influence of striations and horizontal stripes of standing waves. .
幅1μm、長さ100μmの垂直な端面と側面1′をも
つストライプ状のメサを得た。埋込み成長により凸部が
平坦になるまで半導体層を形成し、既多層構造の上部と
下部にオーム電極を形成した。A striped mesa having a vertical end surface and a side surface 1' having a width of 1 μm and a length of 100 μm was obtained. A semiconductor layer was formed by buried growth until the convex portion became flat, and ohmic electrodes were formed on the top and bottom of the existing multilayer structure.
その後側々の素子をへき開により分離し、従来の半導体
レーザアレーよりも反射率が5%高い半導体レーザアレ
ーを得ることができた。Thereafter, the elements on the sides were separated by cleavage, and a semiconductor laser array with a reflectance 5% higher than that of a conventional semiconductor laser array was obtained.
本実施例において被加工材にInP基板を用いたが、S
i基板、GaAs基板の材料でもかまわない。半導体基
板のみに限らず誘電体材料、金属材料にも適用可能であ
る。In this example, an InP substrate was used as the workpiece, but S
The material may be an i-substrate or a GaAs substrate. It is applicable not only to semiconductor substrates but also to dielectric materials and metal materials.
本発明によれば、三層構造の上層レジストパターン形成
後高温加熱処理することによりストリエーションおよび
定在波の影響による積層状の横じまを消去することによ
り、中間層および下層ホトレジストをドライ加工し、垂
直性のすぐれたドライエッチ用マスクを作成することが
出来る。上記マスクを用いてダブルヘテロ構造をもつI
nP結晶をトライエツチング加工することにより、側面
・端面の垂直性、平滑性にすぐ九たストライプ状の導波
路を形成することが出来、すぐれた特性を有する半導体
レーザ、レーザアレーを得ることが出来る。According to the present invention, after forming the upper resist pattern of the three-layer structure, high-temperature heat treatment is performed to eliminate striations and horizontal stripes in the stack due to the influence of standing waves, thereby dry processing the middle layer and lower layer photoresist. Therefore, it is possible to create a dry etching mask with excellent verticality. I with a double heterostructure using the above mask
By tri-etching nP crystal, it is possible to form a striped waveguide with vertical and smooth side and end faces, and it is possible to obtain semiconductor lasers and laser arrays with excellent characteristics.
第1図は本発明の一実施例のドライエッチ加工用三層構
造マスクの形成工程を示す断面図、第2図は従来例およ
び本発明は上層ホトレジスト層の状態を示す斜視図、第
3図は半導体レーザアレーをドライエッチ加工する工程
を示した断面図であ第
図
(ρ
(C)
第
茅
区
(b)
(C)FIG. 1 is a sectional view showing the formation process of a three-layer mask for dry etching according to an embodiment of the present invention, FIG. 2 is a perspective view showing the state of the upper photoresist layer of the conventional example and the present invention, and FIG. 3 is a perspective view showing the state of the upper photoresist layer. is a cross-sectional view showing the process of dry etching a semiconductor laser array.
Claims (1)
層有機物層、第2層化合物層あるいは金属層、第3層ホ
トレジスト層にパターン形成後、パターンエッジに生じ
るストリエーシヨンおよびパターン側面に発生する積層
状横じまの凹凸が消滅するまで加熱処理を行なった後に
、順次前記第2層、第1層に所望なパターンを転写し、
被加工基板上に垂直側面を有するマスクを形成し、しか
る後にドライエッチング法を用い垂直な半導体端面を加
工することを特徴とする半導体素子の製造方法。 2、半導体基板上にバッファー層、第1クラッド層、レ
ーザ活性層、第2クラッド層を形成する工程と既ダブル
ヘテロ構造内に凸部から成るストライプを有する発光領
域を形成する工程において、既構造上に第1項記載の半
導体のドライエッチング加工用のマスク材を被着する工
程と、既マスクを除いた半導体表面を結晶ドライエッチ
ング加工して、半導体結晶にストライプ状の凸部を形成
する工程と、ストライプ状の凸部周辺を埋込み、かつ埋
込み表面が平坦になるまで半導体層を形成する工程と、
既多層構造の上部および下部にオーム性電極を形成する
工程とを含む半導体レーザの製造方法。[Claims] 1. In a method for manufacturing a semiconductor device, a first
After forming a pattern on the organic material layer, the second compound layer or metal layer, and the third photoresist layer, heat treatment is performed until the striations that occur at the edge of the pattern and the unevenness of the laminated horizontal stripes that occur on the side surface of the pattern disappear. After that, a desired pattern is transferred to the second layer and the first layer in sequence,
1. A method of manufacturing a semiconductor device, comprising forming a mask having vertical side surfaces on a substrate to be processed, and then processing vertical semiconductor end faces using a dry etching method. 2. In the step of forming a buffer layer, first cladding layer, laser active layer, and second cladding layer on a semiconductor substrate, and the step of forming a light emitting region having stripes consisting of convex portions in an already double heterostructure, A step of applying a mask material for semiconductor dry etching processing described in item 1 above, and a step of performing crystal dry etching processing on the semiconductor surface excluding the existing mask to form striped convex portions on the semiconductor crystal. a step of filling the periphery of the striped convex portion and forming a semiconductor layer until the buried surface becomes flat;
A method for manufacturing a semiconductor laser, comprising the step of forming ohmic electrodes on top and bottom of an existing multilayer structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24713290A JPH04127157A (en) | 1990-09-19 | 1990-09-19 | Production of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24713290A JPH04127157A (en) | 1990-09-19 | 1990-09-19 | Production of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04127157A true JPH04127157A (en) | 1992-04-28 |
Family
ID=17158911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24713290A Pending JPH04127157A (en) | 1990-09-19 | 1990-09-19 | Production of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04127157A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017147314A (en) * | 2016-02-17 | 2017-08-24 | 東京エレクトロン株式会社 | Pattern forming method |
-
1990
- 1990-09-19 JP JP24713290A patent/JPH04127157A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017147314A (en) * | 2016-02-17 | 2017-08-24 | 東京エレクトロン株式会社 | Pattern forming method |
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