JPH04126402A - Waveform equalizing circuit - Google Patents

Abstract

PURPOSE:To improve the resolution without decreasing the amplitude by forming three kinds of signals, an input signal, signals resulting from delaying the input signal by a time tau1 and a time tau2 respectively and combining these signals. CONSTITUTION:A transfer function H(omega) of the circuit is expressed as an equation of H(omega)=1-2K2(1-2K1cosomegatau1)cosomegatau2, where omega=2pif, and 0<=K1<=1 and 0<=K2<=1. An input signal of a waveform A is given to a buffer amplifier 31 and inputted to a noninverting input + of an adder/subtractor 37 through a delay element 32 whose delay time is tau1 and a delay element 33 whose delay time is tau2. Thus, a waveform B is a delayed waveform A by a delay time (tau1+tau2). A waveform C is the same as a waveform E with respect to the waveform A weighted by an attenuation constant K2, and a waveform D is a delay of the waveform C by a time 2tau2. When the waveforms C, D are subtracted from the waveform B by the adder/subtractor 37, the waveform E appearing at an output of the adder/subtractor 37 has a same peak level as that of the waveform B, a small half-power value and is less in waveform interference between adjacent bits.

Description

[Detailed Description of the Invention] [Summary] The amplitude of an input signal is sampled at equal intervals on the time axis,
Regarding the waveform equalization circuit used in the demodulation method that demodulates data based on this sample value, it makes it easy to distinguish between data "1" and "0" when performing amplitude detection, and prevents waveform interference between adjacent humans. In order to provide a waveform equalization circuit that reduces the
A circuit that shapes an input waveform used in a demodulation method that demodulates data based on this sample value has a transfer function H(ω) of ω=2πf.

As 0≦K, ≦1, 0≦K2≦1, the formula, H ((1))
=1-2KZ(1-2KICO9(IJ r 1)CO
S(JJ r z).Specifically, the first delay means generates a signal that delays the input signal by time (τ1+τ2), and the second delay means generates a signal that delays the input signal by time τ1. a third delay means for producing a signal delayed by a time τ2 from the output signal of the second delay means; a third delay means for producing a signal delayed by a time τ1 from the output signal of the second delay means; 1. Adds + weight to the output signals of the delay means 3 and inverts the two types of signals.
a fourth delay means for producing a signal obtained by delaying the output signal of the first addition/subtraction means (4) by a time of 2τ2;
Two types of signals are added to the signal obtained by delaying the input signal by time (τ, +τ2), which are inverted by adding a weight of 2 to the signal output from the fourth delay means and the signal obtained by delaying this signal by time 2τ2. A waveform equalization circuit is constituted by the second addition/subtraction means.

[Industrial application field]

The present invention relates to an input signal waveform equalization circuit, and in particular to a demodulation method that samples the amplitude of an input signal such as a reproduction signal of a magnetic disk drive at equal intervals on the time axis and demodulates data based on the sampled values. The present invention relates to a waveform equalization circuit used in

As computer systems become faster, magnetic disk devices serving as external storage devices are also required to have faster speeds and larger capacities. For this reason, the signal handled by the demodulation circuit of a magnetic disk drive has a higher frequency, and the recording density on the medium (
BPI) increases, and interference between adjacent bits increases in the reproduced signal, making it difficult to distinguish between data "I" and "O" when performing amplitude detection. Therefore, there is a need for a waveform equalization circuit that reduces this interference between adjacent bits.

[Conventional technology]

FIG. 7 shows the configuration of a waveform equalization circuit 70 of a demodulation circuit in a conventional magnetic disk drive.

This conventional waveform equalization circuit 70 includes a buffer amplifier 71.
, two delay elements 72 and 73 with delay times τ, a terminating resistor 74, attenuators 75 and 76 for the attenuation constant, and an adder/subtractor 77. The input signal passes through a buffer amplifier 71, two delay elements 72 and 73 with a delay time τ, and is consumed by a resistor 74 terminating the output side of the delay element 73. On the other hand, the circuits between the buffer amplifier 71 and the delay element 72, between the delay element 72 and the delay element 73, and between the delay element 73 and the terminating resistor 74 are branched.
The outputs of the delay element 73 and the attenuator 7 have respective attenuation constants.
5.76 and is input to the inverting input - of the adder/subtractor 77,
The output of the delay element 72 is input to the non-inverting input terminal of the adder/subtracter 77.

The input waveform is A, and each of the three inputs of the adder/subtractor 77 is B.
, C, D, that is, if the output waveform of the attenuator 75 is B, the output waveform of the delay element 72 is C, the output waveform of the attenuator 76 is D, and the output waveform of the adder/subtractor 77 is E, each waveform is the 8th waveform. The result will be as shown in the figure. The operation of the conventional waveform equalization circuit will be explained using each waveform shown in FIG. After passing through a buffer amplifier 71, the input signal shown by waveform A is guided to a delay element 72 with a delay time τ and an attenuator 75 with an attenuation constant. Therefore, waveform B is an attenuated form of waveform A, and waveform C is a form that is delayed from waveform A by time τ. In addition, the buffer amplifier 71
After passing through delay elements 72 and 73, attenuator 7
The waveform passed through the attenuator 76 having the same attenuation constant K as that of 5 is the same as the waveform B, but is delayed by the time 2τ. Waveform C is input to the child terminal of adder/subtractor 77, and waveform B and waveform RI are input to one terminal of adder/subtractor 77, so the output waveform E of adder/subtractor 77 is obtained by subtracting waveform B and waveform RI from waveform C. It takes shape.

In this way, the conventional waveform equalization circuit delays the input signal using a delay element, and the time τ and 2τ
By obtaining a delayed signal, weighting the signal delayed by 2τ from the input signal by K, and subtracting it from the signal delayed by time τ, the input signal has a small half-width and less waveform interference between adjacent bits. This is a circuit that improves resolution by converting it into a waveform.

The transfer function H(ω) of the waveform equalization circuit in Fig. 7 is H(ω)
It is expressed as = 1 2K cos ωτ.

[Problems to be Solved by the Invention] However, with the conventional waveform equalization circuit, a waveform with less waveform interference between adjacent focuses can be obtained, but as can be seen from FIG. For example, the amplitude decreases more and more, which is undesirable for a demodulation method that samples the amplitude at equal intervals on the time axis and demodulates data based on the sampled values.

In addition, equalization methods such as Nyquist equalization are available as methods to reduce waveform interference, but it is not possible to achieve sufficient equalization for signals with large waveform variations, such as reproduction signals in magnetic recording, and hardware Problems such as an increase in

The present invention solves the problems of the conventional waveform equalization circuit, and transforms a human signal into a waveform with a small half-width and less waveform interference between adjacent bits, thereby increasing the amplitude while maintaining the effect of improving resolution. It is an object of the present invention to provide a waveform equalization circuit that does not reduce the waveform.

[Means to solve the problem]

The principle structure of the present invention that solves the above problems is shown in FIG. As shown in FIG. 1(a), the waveform equalization circuit of the present invention is used in a demodulation method that samples the amplitude of an input signal at equal intervals on the time axis and demodulates data based on the sampled values. A circuit that shapes the input waveform of
Assuming that K2≦1, it is configured to be expressed by the equation, H(ω)=1 2K2 (1-2, cosωτ,)cosωτ2. Specifically, as shown in FIG. 1(b), a first delay means 1 generates a signal delayed by a time (τ, +τ2) from the input signal, and a second delay means 1 generates a signal delayed by a time τ1 from the input signal. The delay means 2 and the time τ from the output signal of the second delay means 2
A third delay means 3 generates a signal delayed by 2, the input signal is delayed by a time τ, the input signal is delayed by 2τ1, and the output signal of the third delay means 3 is delayed by 1. A first adding/subtracting means 4 which adds two weighted and inverted signals; a fourth delaying means 5 which produces a signal obtained by delaying the output signal of the first adding/subtracting means 5 by a time 2τ2; A second addition/subtraction means that adds two types of signals to the signal delayed by (τ1+τ2), the signal output from the fourth delay means 5, and the signal obtained by delaying this signal by a time of 2τ2, each of which is inverted by adding a weight of 2 to each. 6 constitutes a waveform equalization circuit.

[Effect]

According to the present invention, the input signal is set to a time τ.

Three types of signals are created: and a signal delayed by a time of 2τ1, and a weight is added to the attenuation rate for the signal obtained by delaying the input signal and the human signal by a time of 2τ. Then, an operation is performed to subtract the two types of signals to which these weights have been added from the signal obtained by delaying the input signal by a time τ1. After this, two types of signals are created: a calculated signal and a signal delayed by a time of 2τ2, and a signal in which the attenuation rate is weighted by 2 is added to these two types of α signals, and the input signal is delayed by a time of (τ1+τ2). An output signal is created by subtracting from the delayed signal.

According to the present equalization circuit, the resolution is improved without reducing the amplitude, so even if the signal quality deteriorates due to high-density recording, highly reliable demodulation is possible.

〔Example〕

Embodiments of the waveform equalization circuit of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block circuit diagram showing the configuration of a waveform equalization circuit 20 according to an embodiment of the present invention. The waveform equalization circuit 20 of this embodiment includes a buffer amplifier 21.31, three delay elements 22, 23, and 32 with a delay time τ, three delay elements 28, 29, and 33 with a delay time τ2, and a terminating resistor. 24, 30.
34, an attenuator 25.26 for the attenuation constant, an attenuator 35.36 for the reduction constant, and an adder/subtractor 2737.

The input signal is branched into two, one of which is sent to the buffer amplifier 2I.
It passes through two delay elements 22 and 23 with a delay time τ1, and is consumed by a resistor 24 terminating the output side of the delay element 23. Further, the circuits between the buffer amplifier 21 and the delay element 22, between the delay element 22 and the delay element 23, and between the delay element 23 and the terminating resistor 24 are also branched, and the outputs of the buffer amplifier 21 and the delay element 23 are each attenuated by an attenuation constant. , and the output of the delay element 22 is input to the non-inverting input terminal of the adder/subtractor 27.

The output of the adder/subtractor 27 passes through two delay elements 28 and 29 with a delay time τ2, and is consumed by a resistor 30 terminating the output side of the delay element 29. Further, the output of the adder/subtractor 27 and the output of the delay element 29 are also branched, and are inputted to the inverting input - of the adder/subtractor 37 through attenuators 35 and 36 each having an attenuation constant Kz.

The other branched input signal passes through the delay element 32 with a delay time τ1 and the delay element 33 with a delay time τ2, and then passes through the delay element 32 with a delay time τ1 and the delay element 33 with a delay time τ2.
3 is consumed by a resistor 34 terminating the output side of 3. Further, the output of the delay element 33 is branched and is directly added to vJIi
It is input to the non-inverting type of calculator 37.

Waveform equalization circuit 2 of this embodiment where the signal flows as described above
0, the input waveform is A, and each of the three inputs of the adder/subtractor 37 is B, as in the conventional example.

C, D, that is, the output waveform of the delay element 33, B, the attenuator 3
Let C be the output waveform of the attenuator 5, D be the output waveform of the attenuator 36, and E be the output waveform of the adder/subtractor 37, the respective waveforms will be as shown in FIG.

The operation of the waveform equalization circuit of this embodiment will be explained using each waveform shown in FIG. After the input signal shown by waveform A passes through the buffer amplifier 31, it has a delay time τ.

The signal is inputted to the non-inverting input terminal of the adder/subtractor 37 through the delay element 32 having a delay time τ2 and the delay element 33 having a delay time τ2. Therefore, waveform B is simply waveform A delayed by delay time τ, +τ2. On the other hand, the waveform C input to one of the inverting inputs of the adder/subtracter 37 via the attenuator 35 before being input to the attenuator 35 is generated by the adder/subtracter shown in FIG. This is the same relationship as the output of 77. Therefore, waveform C has the same shape as waveform E shown in FIG. 8 for waveform A, with the attenuation constant weighted by 2.
is further delayed by time 2τ2.

Here, the attenuation constant is set to 2 so that the peak values of waveform C and waveform 2 match the levels of α and β points of waveform B (points on waveform B at the same time as the peak values of waveforms C and D). At the same time, if the delay time τ and τ2 are determined so that the levels of waveforms C and D become 0 at the peak point of waveform B, then when waveform C and waveform RI are subtracted from waveform B in adder/subtracter 37, the addition/subtraction As shown in FIG. 3, the waveform E appearing at the output of the converter 37 has the same peak value level as the waveform B, has a small half-width, and has little waveform interference between adjacent bits.

Note that the transfer function H(ω) of the waveform equalization circuit 20 of the embodiment described above is given by the following equation.

H((1))=1 2 to 2(1-2, cosωr I
)Cos(1) r.

[However, ω=2πf, 0≦K, ≦1.0≦K2≦11
In this equation, τ1. τ2 is the amount of delay of each delay element shown in FIG. τ1 is 1 of the half-width of the solitary wave input waveform
/2, and τ2 is set equal to the sampling interval. Further, K, and K2 each represent the amount of attenuation of the attenuator, and are usually set to around 0.5 in many cases. Furthermore, K2 is a constant that determines interference at adjacent sample points, and is set to make this interference lid as small as possible. This value is given by Kz-Va/Vs when the amplitudes at adjacent sample positions in the input waveform are divided by .

FIG. 4 shows the gain of the waveform equalization circuit 20 of the embodiment shown in FIG.
The frequency characteristics (transfer characteristics) are shown by thick lines, and the gain-frequency characteristics of the waveform equalization circuit 70 shown in FIG. 7 are shown by thin lines for comparison. As can be seen from this figure, the output waveform of the waveform equalization circuit 20 in FIG. 2 and the output waveform of the waveform equalization circuit 70 in FIG. I can do it. Figure 2 Waveforms of various parts in the circuit shown in Figure 2 Transfer characteristics of the waveform equalization circuit in the circuit shown in Figure 2 Configuration of another embodiment of the invention

Claims (1)

[Claims] 1. A circuit for shaping an input waveform used in a demodulation method that samples the amplitude of an input signal at equal intervals on the time axis and demodulates data based on the sampled values, the circuit comprising: The transfer function H(ω) of is ω=2πf, 0≦K_1≦
1, 0≦K_2≦1, the formula, H(ω)=1-2K_
A waveform equalization circuit characterized by being represented by 2(1-2K_1cosωτ_1)cosωτ_2. 2. A first delay means (1) that produces a signal that delays the input signal by time (τ_1+τ_2), a second delay means (2) that produces a signal that delays the input signal by time τ_1, and a second delay means ( A third delay means (3) generates a signal delayed by a time τ_2 from the output signal of the input signal (2); a third delay means (3) generates a signal delayed by a time τ_1 from the input signal; A first addition/subtraction means (4) which adds two types of signals which are inverted by adding a weight of K_1 to the output signal of 3), and a signal obtained by delaying the output signal of this first addition/subtraction means (4) by a time of 2τ_2. A fourth delay means (5) that delays the input signal by a time (τ
_1+τ_2) The fourth delay means (5) is applied to the delayed signal.
A second addition/subtraction means (6) that adds two types of signals which are inverted by adding a weight of K_2 to a signal outputted from a signal outputted from the second inverter and a signal obtained by delaying this signal by a time of 2τ_2, respectively. 1. The waveform equalization circuit according to 1. 3. The waveform equalization circuit according to claim 1 or 2, wherein the value of the time τ_2 matches a sampling period.