JPH04125920A - Growth method of semiconductor thin film - Google Patents
Growth method of semiconductor thin filmInfo
- Publication number
- JPH04125920A JPH04125920A JP24659990A JP24659990A JPH04125920A JP H04125920 A JPH04125920 A JP H04125920A JP 24659990 A JP24659990 A JP 24659990A JP 24659990 A JP24659990 A JP 24659990A JP H04125920 A JPH04125920 A JP H04125920A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- thin film
- forming
- semiconductor thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000010408 film Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 12
- 239000013078 crystal Substances 0.000 abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 5
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 239000007789 gas Substances 0.000 abstract 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 abstract 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 abstract 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 abstract 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012776 electronic material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置の形成に必要な半導体薄膜の成長
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for growing semiconductor thin films necessary for forming semiconductor devices.
（従来の技術）
従来、Ｓｉ基板上にＳｉと格子定数の異なった半導体膜
、例えばＧａＡｓ膜を成長する方法としては、例エバハ
ル（Ｈｕｌｌ）他、アブライドフイジクスレターズ（Ａ
ｐｐｌ、 Ｐｈｙｓ、 Ｌｅｔｔｓ、）、４９、ｐ１７
１４、（１９８６）にある様にＳｉ基板上に直接成長す
る方法や、例えば、カラム（Ｋａｒａｍ）ら、エレクト
ロニックマテリアルコンファレンステクニカルプログラ
ムアブストラクト（Ｅｌｅｃｔｒｏｎｉｃ Ｍａｔｅｒ
ｉａｌｓ Ｃｏｎｆｅｒｅｎｃｅ Ｔｅｃｈｎｉｃａｌ
ＰｒｏｇｒａｍＡｂｓｔｒａｃｔ）Ｐ５２．（１９９
０）にある様にＳｉ表面を５ｉ０２膜で覆いその５ｉ０
２膜の一部領域を除去して露出しその露出部にのみ選択
的に成長する方法がある。(Prior Art) Conventionally, as a method for growing a semiconductor film having a different lattice constant from Si, such as a GaAs film, on a Si substrate, methods such as those of Eberhull (Hull et al.) and Abride Physics Letters (A.
ppl, Phys, Letts, ), 49, p17
14, (1986), or the method of direct growth on a Si substrate, for example, Karam et al., Electronic Materials Conference Technical Program Abstracts (Electronic Materials Conference Technical Program Abstracts)
ials Conference Technical
ProgramAbstract)P52. (199
0), the Si surface is covered with a 5i02 film and the 5i0
There is a method of removing and exposing a part of the two films and growing selectively only on the exposed part.
（発明が解決しようとする課題）
従来の技術では、Ｓｉ基板上にＳｉと格子定数の異なる
半導体薄膜を成長すると、成長した半導体薄膜中にＳｉ
との格子定数の違いに起因する多数の結晶欠陥が存在す
る。従来技術のうち後者の選択成長を利用した方法では
、成長面積を縮小する事によってこの様な結晶欠陥の減
少の効果があるが、得られる半導体薄膜の面積小さいし
結晶欠陥も残留しているという問題がある。(Problems to be Solved by the Invention) In the conventional technology, when a semiconductor thin film having a lattice constant different from Si is grown on a Si substrate, Si
There are many crystal defects caused by the difference in lattice constant between Among conventional techniques, the latter method using selective growth has the effect of reducing such crystal defects by reducing the growth area, but the area of the resulting semiconductor thin film is small and crystal defects remain. There's a problem.
（課題を解決するための手段）
本発明によれば、Ｓｉ基板表面に第１のＳｉ酸化膜また
はＳｉ窒化膜を形成する工程と、第１のＳｉ酸化膜また
はＳｉ窒化膜に第１の開口部を形成する工程と、第１の
開口部にのみ選択的にＳｉを成長する工程と、第１の開
口部と接するように多結晶Ｓｉ膜または非晶質Ｓｉ膜を
堆積する工程と、第２のＳｉ酸化膜またはＳｉ窒化膜を
形成する工程と、該第２のＳｉ酸化膜またはＳｉ窒化膜
に第２の開口部を形成する工程と、多結晶Ｓｉ膜または
非晶質Ｓｉ膜を除去して第１のＳｉ酸化膜またはＳｉ窒
化膜に挟まれた空洞を形成する工程と、該空洞部に選択
的にＳｉと格子定数の異なる半導体薄膜を成長する工程
とからなる半導体薄膜の成長方法が得られる。(Means for Solving the Problems) According to the present invention, a step of forming a first Si oxide film or a Si nitride film on a surface of a Si substrate, and a step of forming a first opening in the first Si oxide film or Si nitride film. a step of selectively growing Si only in the first opening; a step of depositing a polycrystalline Si film or an amorphous Si film in contact with the first opening; Step 2 of forming a Si oxide film or Si nitride film, forming a second opening in the second Si oxide film or Si nitride film, and removing the polycrystalline Si film or amorphous Si film. A method for growing a semiconductor thin film comprising the steps of: forming a cavity sandwiched between a first Si oxide film or a Si nitride film; and selectively growing a semiconductor thin film having a lattice constant different from that of Si in the cavity. is obtained.
（作用）
以下本発明によって、Ｓｉ基板上に結晶欠陥が少なく大
面積のＳｉとは格子定数の異なる半導体薄膜を成長する
事が可能となる作用について述べる。(Function) The following will describe the function of the present invention, which makes it possible to grow a semiconductor thin film with few crystal defects and a large area and a lattice constant different from that of Si on a Si substrate.
本発明者らが、Ｓｉ基板上にＳｉと格子定数の異なる半
導体薄膜を成長する過程を詳細に評価したところ、発生
する結晶欠陥の種類はそのほとんどが°“転位′″であ
った。転位はその他の結晶欠陥（積層欠陥や双晶欠陥）
とは異なり、−変異種物質との界面などに達するとそこ
で抜けてそれ以上は伝搬しない性質を持つ。従って、本
発明の様な構造を取る事によって、転位が上下のＳｉ酸
化膜あるいはＳｉ窒化膜との界面に抜けて、横方向には
伝搬しないため結晶欠陥の減少が期待される。さらに、
従来技術の選択成長と同様にＳｉとの接触面積が小さい
事も結晶欠陥の減少に有効である。しかも従来技術では
、選択成長を利用すると得られる半導体薄膜の面積が小
さくなるが、本発明の方法では横方向へ成長するため大
面積の成長が可能である。When the present inventors made a detailed evaluation of the process of growing a semiconductor thin film having a lattice constant different from that of Si on a Si substrate, it was found that most of the types of crystal defects that occur are °"dislocations". Dislocations are other crystal defects (stacking faults and twin defects)
Unlike, - it has the property that once it reaches the interface with the mutant material, it escapes there and does not propagate any further. Therefore, by adopting the structure of the present invention, a reduction in crystal defects is expected because dislocations escape to the interface between the upper and lower Si oxide films or Si nitride films and do not propagate laterally. moreover,
As with selective growth in the prior art, a small contact area with Si is also effective in reducing crystal defects. Moreover, in the conventional technique, when selective growth is used, the area of the semiconductor thin film obtained is small, but in the method of the present invention, growth is performed in the lateral direction, so that growth of a large area is possible.
（実施例）
以下本発明の実施例について図面を用いて詳細に説明す
る。第１図は本発明の詳細な説明するための構造図であ
る。(Example) Examples of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a structural diagram for explaining the present invention in detail.
単結晶Ｓｉ基板１０の表面に、第１のＳｉ酸化膜２０を
基板温度９００°Ｃ〜１１００°Ｃの熱酸化法で膜厚０
．２〜１．ｕｍ形成した。つぎに通常のフォトリソグラ
フィーとイオンエツチング技術で第１のＳｉ酸化膜に開
口部を形成してＳｉ基板表面を一部露出して、第１図（
ａ）に示す構造を得た。次に５ｉＨ２ＣＩ２／ＨＣＩ／
Ｈ２ガスを用いた基板温度８００〜１０００°Ｃの選択
成長で、開口部にのみＳｉをエピタキシャル成長し、第
１図（ｂ）の構造を形成した。次にＬＰＣＶＤ法で多結
晶５ｉ４０を膜厚０．０１μｍ〜１μｍ堆積し、フォト
リソグラフィーとイオンエツチング技術で成型して端部
が選択成長５ｉ３０と重なるようにした。次にＬＰＣＶ
Ｄ法で第２のＳｉ酸化膜５０を膜厚０．２〜１μｍ堆積
し、第２のＳｉ酸化膜に選択成長５ｉ３０から１０ｃｚ
ｍ離れた位置に開口部を形成して第１図（ｃ）に示す構
造を得た。次の基板温度８００〜９５０°ＣでＭＣＩガ
スを導入し、開口部から多結晶５ｉ４０をエツチングし
空洞領域を形成した。単結晶Ｓｉは多結晶Ｓｉよりエツ
チングレートが小さいので選択成長５ｉ３０のところで
エツチングを止めることができる。最後に基板温度４０
０°Ｃ〜７００°Ｃでトリメチルガリウム（ＴＭＧ）ま
たはトリエチルガリウム（ＴＥＧ）とアルシンガスを用
いた通常のＭＯＣＶＤ法による選択成長で、空洞部をＧ
ａＡｓ薄膜で埋め戻し、第１図（ｄ）に示す構造を得た
。得られた構造を走査電子顕微鏡および透過電子顕微鏡
を用いて、平面方向および断面方向から評価した。A first Si oxide film 20 is formed on the surface of a single crystal Si substrate 10 to a thickness of 0 by thermal oxidation at a substrate temperature of 900°C to 1100°C.
．． 2-1. um was formed. Next, using conventional photolithography and ion etching techniques, an opening is formed in the first Si oxide film to expose a portion of the Si substrate surface.
The structure shown in a) was obtained. Next 5iH2CI2/HCI/
By selective growth using H2 gas at a substrate temperature of 800 to 1000 DEG C., Si was epitaxially grown only in the openings to form the structure shown in FIG. 1(b). Next, polycrystalline 5i40 was deposited to a thickness of 0.01 μm to 1 μm using the LPCVD method, and molded using photolithography and ion etching techniques so that the ends overlapped with the selectively grown 5i30. Next, LPCV
A second Si oxide film 50 is deposited to a thickness of 0.2 to 1 μm using method D, and selective growth is performed on the second Si oxide film from 5i30 to 10cz.
Openings were formed at positions separated by m to obtain the structure shown in FIG. 1(c). Next, MCI gas was introduced at a substrate temperature of 800 DEG to 950 DEG C., and the polycrystalline 5i40 was etched from the opening to form a cavity region. Since monocrystalline Si has a lower etching rate than polycrystalline Si, etching can be stopped at selective growth 5i30. Finally, the substrate temperature is 40
The cavity is grown by selective growth using the usual MOCVD method using trimethyl gallium (TMG) or triethyl gallium (TEG) and arsine gas at 0°C to 700°C.
It was backfilled with an aAs thin film to obtain the structure shown in FIG. 1(d). The obtained structure was evaluated from the plane direction and cross-sectional direction using a scanning electron microscope and a transmission electron microscope.
その結果、ＧａＡｓがＳｉに接触する領域では多数の転
位が存在するが、Ｓｉ酸化膜上を横方向に成長するにつ
れて転位の密度は減少し、１μｍ離れた領域がらは欠陥
密度１０３個１ｃｍ２以下の良好なＧａＡｓ薄膜が得ら
れた。同様な現象はアルシンガスの代わりにフォスフイ
ンガスを用いたＧａＰ成長でも見られ、他にもＧａｒｂ
成長でも見られ、Ｓｉと格子定数の異なるすべての半導
体薄膜の適用に可能である。また、Ｓｉ酸化膜のかわり
にＳｉ窒化膜を用いても同様な結果が得られる。As a result, a large number of dislocations exist in the region where GaAs contacts Si, but the density of dislocations decreases as it grows laterally on the Si oxide film, and in the region 1 μm apart, the defect density is 103 defects less than 1 cm2. A good GaAs thin film was obtained. A similar phenomenon was observed in GaP growth using phosphine gas instead of arsine gas, and
It is also seen in growth, and is applicable to all semiconductor thin films with different lattice constants from Si. Furthermore, similar results can be obtained by using a Si nitride film instead of the Si oxide film.
（発明の効果）
以上本発明によって、Ｓｉ基板上に良好な結晶性を有し
て、大面積のＳｉと格子定数の異なる半導体薄膜を形成
する事が可能となり、０ＥＩＣ等の複数の機能を持つデ
バイス作製に有用な半導体基板の提供が可能となった。(Effects of the Invention) As described above, according to the present invention, it is possible to form a semiconductor thin film having good crystallinity on a Si substrate, having a large area and a lattice constant different from that of Si, and having multiple functions such as 0EIC. It has become possible to provide a semiconductor substrate useful for device fabrication.
第１図は、本発明の詳細な説明するための構造図である
。
１０ ・・・・・・ Ｓｉ基板
２０ ・・・・・・ 第１のＳｉ酸化膜３０ ・・
・・・・ 選択成長５ｉ
４０ ・・・・・・ 多結晶５ｉ
５０ ・・・・・・ 第２のＳｉ酸化膜６０ ・・
・・・・ ＧａＡｓ薄膜FIG. 1 is a structural diagram for explaining the present invention in detail. 10... Si substrate 20... First Si oxide film 30...
... Selective growth 5i 40 ... Polycrystalline 5i 50 ... Second Si oxide film 60 ...
...GaAs thin film
Claims (1)
成する工程と、該第１のＳｉ酸化膜またはＳｉ窒化膜に
第１の開口部を形成する工程と、該第１の開口部にのみ
選択的にＳｉを成長する工程と、多結晶Ｓｉ膜または非
晶質Ｓｉ膜を第１の開口部に接するように堆積する工程
と、第２のＳｉ酸化膜またはＳｉ窒化膜を形成する工程
と、該第２のＳｉ酸化膜またはＳｉ窒化膜に第２の開口
部を形成する工程と、多結晶Ｓｉ膜または非晶質Ｓｉ膜
を除去して第１のＳｉ酸化膜またはＳｉ窒化膜と第２の
Ｓｉ酸化膜またはＳｉ窒化膜に挟まれた空洞を形成する
工程と、該空洞部に選択的にＳｉと格子定数の異なる半
導体薄膜を成長する工程とからなる半導体薄膜の成長方
法。forming a first Si oxide film or Si nitride film on the surface of the Si substrate; forming a first opening in the first Si oxide film or Si nitride film; and forming a first opening in the first opening. a step of selectively growing Si; a step of depositing a polycrystalline Si film or an amorphous Si film in contact with the first opening; and a step of forming a second Si oxide film or Si nitride film. forming a second opening in the second Si oxide film or Si nitride film; and removing the polycrystalline Si film or the amorphous Si film to replace the first Si oxide film or Si nitride film. A method for growing a semiconductor thin film, comprising the steps of forming a cavity sandwiched between a second Si oxide film or a Si nitride film, and selectively growing a semiconductor thin film having a lattice constant different from that of Si in the cavity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24659990A JPH0654763B2 (en) | 1990-09-17 | 1990-09-17 | Method for growing semiconductor thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24659990A JPH0654763B2 (en) | 1990-09-17 | 1990-09-17 | Method for growing semiconductor thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04125920A true JPH04125920A (en) | 1992-04-27 |
| JPH0654763B2 JPH0654763B2 (en) | 1994-07-20 |
Family
ID=17150811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24659990A Expired - Fee Related JPH0654763B2 (en) | 1990-09-17 | 1990-09-17 | Method for growing semiconductor thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0654763B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5356510A (en) * | 1991-10-08 | 1994-10-18 | Thomson-Csf | Method for the growing of heteroepitaxial layers |
| US5360754A (en) * | 1992-04-02 | 1994-11-01 | Thomson-Csf | Method for the making heteroepitaxial thin layers and electronic devices |
| US5525536A (en) * | 1991-12-26 | 1996-06-11 | Rohm Co., Ltd. | Method for producing SOI substrate and semiconductor device using the same |
-
1990
- 1990-09-17 JP JP24659990A patent/JPH0654763B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5356510A (en) * | 1991-10-08 | 1994-10-18 | Thomson-Csf | Method for the growing of heteroepitaxial layers |
| US5525536A (en) * | 1991-12-26 | 1996-06-11 | Rohm Co., Ltd. | Method for producing SOI substrate and semiconductor device using the same |
| US5360754A (en) * | 1992-04-02 | 1994-11-01 | Thomson-Csf | Method for the making heteroepitaxial thin layers and electronic devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0654763B2 (en) | 1994-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7888244B2 (en) | Threading-dislocation-free nanoheteroepitaxy of Ge on Si using self-directed touch-down of Ge through a thin SiO2 layer | |
| EP0430280B1 (en) | Selective and non-selective deposition of Si1-x Gex on a Si substrate that is partially masked with Si O2 | |
| JP3093904B2 (en) | Method for growing compound semiconductor crystal | |
| JPH088214B2 (en) | Semiconductor device | |
| JPH0484418A (en) | Method of heteroepitaxial development of iii-v group compound semiconductor for different types of substrates | |
| JPH04303920A (en) | Insulating film/iii-v compound semiconductor stacked structure on group iv substrate | |
| US6594293B1 (en) | Relaxed InxGa1-xAs layers integrated with Si | |
| JPH04125920A (en) | Growth method of semiconductor thin film | |
| JP2743348B2 (en) | Epitaxial growth method | |
| JP3487393B2 (en) | Method of forming heteroepitaxial semiconductor substrate, compound semiconductor device having such heteroepitaxial semiconductor substrate, and method of manufacturing the same | |
| JP3060486B2 (en) | Method for forming SOI substrate | |
| JPH0263115A (en) | Selective growth of thin film | |
| JP2527016B2 (en) | Method for manufacturing semiconductor film | |
| JPH06260427A (en) | Selective growth method of semiconductor film | |
| JPH04186824A (en) | Semiconductor substrate and manufacture thereof | |
| JPH0419700B2 (en) | ||
| JPH05267175A (en) | Compound semiconductor substrate | |
| JP2599576B2 (en) | Method for growing two-dimensional thin film of group III-V compound semiconductor | |
| JPH03247597A (en) | Epitaxial growth method of iii-v compound semiconductor on silicon substrate | |
| JP3400085B2 (en) | Method for forming compound semiconductor layer | |
| JP3084989B2 (en) | Compound semiconductor substrate and method of manufacturing the same | |
| JP2527015B2 (en) | Method for manufacturing semiconductor film | |
| JPH01120011A (en) | Inp semiconductor thin film | |
| JPH09162122A (en) | Iii-v compound semiconductor wafer and production thereof | |
| JP2503255B2 (en) | Method for manufacturing compound semiconductor substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |