JPH0412429B2 - - Google Patents

Info

Publication number
JPH0412429B2
JPH0412429B2 JP58099775A JP9977583A JPH0412429B2 JP H0412429 B2 JPH0412429 B2 JP H0412429B2 JP 58099775 A JP58099775 A JP 58099775A JP 9977583 A JP9977583 A JP 9977583A JP H0412429 B2 JPH0412429 B2 JP H0412429B2
Authority
JP
Japan
Prior art keywords
signal
circuit
speed detection
pulse
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58099775A
Other languages
Japanese (ja)
Other versions
JPS59224569A (en
Inventor
Tooru Kaiko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9977583A priority Critical patent/JPS59224569A/en
Publication of JPS59224569A publication Critical patent/JPS59224569A/en
Publication of JPH0412429B2 publication Critical patent/JPH0412429B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01PMEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P13/00Indicating or recording presence, absence, or direction, of movement
    • G01P13/02Indicating direction only, e.g. by weather vane
    • G01P13/04Indicating positive or negative direction of a linear movement or clockwise or anti-clockwise direction of a rotational movement
    • G01P13/045Indicating positive or negative direction of a linear movement or clockwise or anti-clockwise direction of a rotational movement with speed indication

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Linear Or Angular Velocity Measurement And Their Indicating Devices (AREA)

Description

【発明の詳細な説明】 この発明は回転機の速度を軸端直結の2相イン
クリメンタルロータリーエンコーダで検出し速度
信号とするデイジタル速度検出装置に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital speed detection device that detects the speed of a rotating machine using a two-phase incremental rotary encoder directly connected to the shaft end and generates a speed signal.

従来、この種のデイジタル速度検出装置として
第1図に示すものがあつた。第2図は第1図の要
部の波形図である。第1図において1はロータリ
ーエンコーダ(図示していない)の出力信号を入
力とし回転体の回転方向を判別する回転方向判別
回路、2は発信回路でクロツク信号Cを発生す
る。3はタイミング回路でロータリエンコーダか
らのA信号とクロツク信号Cとを入力として出力
信号Mを発生する。4はラツチ及びリセツトパル
ス発生回路で信号Mとクロツク信号Cとによつて
信号Rを発生する。また5は速度検出パルスカウ
ンタで信号Rのパルス期間Ts内のパルス信号M
を計数する。7は第1バツフア回路、8は第2バ
ツフア回路である。
Conventionally, there has been a digital speed detection device of this type as shown in FIG. FIG. 2 is a waveform diagram of the main part of FIG. 1. In FIG. 1, reference numeral 1 denotes a rotational direction determining circuit which inputs an output signal from a rotary encoder (not shown) and determines the rotational direction of a rotary body, and 2 a transmitter circuit which generates a clock signal C. 3 is a timing circuit which receives the A signal from the rotary encoder and the clock signal C and generates an output signal M. Reference numeral 4 denotes a latch and reset pulse generating circuit which generates a signal R based on the signal M and the clock signal C. 5 is a speed detection pulse counter, which is a pulse signal M within the pulse period Ts of the signal R.
Count. 7 is a first buffer circuit, and 8 is a second buffer circuit.

次に第1図に示す従来回路の動作を第2図に示
した要部の波形図を参照して説明する。回転方向
判別回路1の入力端子A,Bには第2図に示すよ
うなロータリーエンコーダによつて検出された2
相波形が入力される。回転方向判別回路1からの
出力信号は前記2相波を受けると回転体の回転方
向によつて“1”又は“0”の2値化された出力
信号Dを出力する。また、発信回路2のクロツク
信号Cと前記ロータリーエンコーダの出力A信号
とを入力信号とするタイミング回路3は前記A信
号の立上りで発生したパルスがクロツク信号Cの
パルス発生タイミングと一致した時に信号Mが出
力される。そこで、前記M信号とクロツク信号C
を受けたラツチ及びリセツトパルス発生回路4か
らは信号Rが図示の如く出力され信号Rの発生周
期をTsとすると速度検出パルスカウンタ5では
Ts期間内の信号Mを計数して信号Pを出力し、
信号Rの立下りでリセツトされる。クロツクパル
スカウンタ6は同期区間Ts内のクロツク信号C
を計数して信号Nを出力し信号Rの立下りでリセ
ツトされる。前記クロツクパルスカウンタ6の出
力信号Nのうち、Nnで発生されるNd信号は
信号Mとクロツク信号Cの両信号を入力とするラ
ツチ及びリセツトパルス発生回路4に“1”又は
“0”のリセツト信号を伝達し前記信号Ndが
“1”であれば信号Mに同期した信号Rを出力す
る。但し、信号Ndのパルス幅はクロツクパルス
カウンタ6の出力信号のうち既設定計数値nで出
力されるパルス信号で与えられる。ラツチ及びバ
ツフア機能で構成される第1及び第2バツフア回
路7及び8は信号P,D及びNを信号Rの立上り
でラツチし夫々の出力に“H”又は“L”のデイ
ジタル速度信号を出力する。
Next, the operation of the conventional circuit shown in FIG. 1 will be explained with reference to the waveform diagram of the main part shown in FIG. The input terminals A and B of the rotation direction discrimination circuit 1 are connected to the input terminals 2 detected by a rotary encoder as shown in FIG.
A phase waveform is input. When the output signal from the rotation direction discrimination circuit 1 receives the two-phase wave, it outputs a binary output signal D of "1" or "0" depending on the rotation direction of the rotating body. Further, a timing circuit 3 which receives the clock signal C of the transmitting circuit 2 and the output signal A of the rotary encoder as input signals outputs the signal M when the pulse generated at the rising edge of the signal A coincides with the pulse generation timing of the clock signal C. is output. Therefore, the M signal and the clock signal C
The signal R is output from the latch and reset pulse generation circuit 4 as shown in the figure, and when the generation period of the signal R is Ts, the speed detection pulse counter 5 outputs the signal R as shown in the figure.
Count the signal M within the Ts period and output the signal P,
It is reset at the falling edge of signal R. The clock pulse counter 6 receives the clock signal C within the synchronization period Ts.
It counts and outputs the signal N, and is reset at the falling edge of the signal R. Of the output signals N of the clock pulse counter 6, the Nd signal generated by Nn is applied to the latch and reset pulse generation circuit 4 which receives both the signal M and the clock signal C as inputs to set it to "1" or "0". A reset signal is transmitted, and if the signal Nd is "1", a signal R synchronized with the signal M is output. However, the pulse width of the signal Nd is given by a pulse signal outputted from the output signal of the clock pulse counter 6 at a preset count value n. The first and second buffer circuits 7 and 8, which have latch and buffer functions, latch the signals P, D, and N at the rising edge of the signal R, and output "H" or "L" digital speed signals to their respective outputs. do.

上記速度検出方式では信号Nがクロツクパルス
カウンタ6の出力信号レベルnに到達後(Ndが
“1”になつた後)の信号Mと信号Rが同期して
いるため信号Rのパルス間隔Tsの期間中に信号
NにはNs(スレツシヨルドレベルnに対し、n
Nsのパルス数)がカウントされ信号Pには信号
Mと信号Rの同期区間中にPS(nN時の速度検
出パルスカウンタ5の出力信号)がカウントされ
る。この場合の回転体速度Sの演算結果Sfは Sf=KPs/Ns(但し、K=一定) で示される。上記の演算は第1及び第2バツフア
回路7及び8の出力信号“H”及び“L”の信号
を読み込んで第1図以外の回路で行われる。すな
わち、第3図の如く速度Sがa点で正転から逆転
に変ると信号Dはb点において“1”から“0”
に切り替わりその後の制御データは逆転として処
理されるが信号Rのパルス期間中に途中で信号D
が切り替つた時のTsdの期間は本来のエンコーダ
により検出した速度でないことが明らかでありこ
のTsd期間中の信号Nsdにより演算された速度
SfdはSfd=KPsd/Nsdとなり正常な速度検出データ ではない。
In the above speed detection method, since the signal M and the signal R are synchronized after the signal N reaches the output signal level n of the clock pulse counter 6 (after Nd becomes "1"), the pulse interval of the signal R is Ts. During the period of , the signal N has Ns (for threshold level n, n
The number of pulses Ns) is counted, and P S (the output signal of the speed detection pulse counter 5 at nN) is counted in the signal P during the synchronization period of the signals M and R. In this case, the calculation result Sf of the rotating body speed S is expressed as Sf=KPs/Ns (K=constant). The above calculation is performed in a circuit other than that shown in FIG. 1 by reading the "H" and "L" output signals of the first and second buffer circuits 7 and 8. That is, as shown in Figure 3, when the speed S changes from normal rotation to reverse rotation at point a, the signal D changes from "1" to "0" at point b.
The subsequent control data is processed as reverse, but the signal D is switched to during the pulse period of the signal R.
It is clear that the Tsd period when the switch is not the speed detected by the original encoder, and the speed calculated by the signal Nsd during this Tsd period
Sfd is Sfd=KPsd/Nsd, which is not normal speed detection data.

従来の速度検出方式は以上のように構成されて
いるので回転機の回転方向が正転から逆転に切替
わる時点で異常なデータとなり制御上問題となる
ことがあつた。
Since the conventional speed detection method is configured as described above, abnormal data may be generated when the rotation direction of the rotating machine is switched from normal rotation to reverse rotation, which may cause control problems.

この発明は上記のような従来のものの欠点を除
去するためになされたもので、上述の回転方向反
転時の異常データの前後の制御データが正常に検
出されていることに着目し、回転体が正転から逆
転に切替つた場合にも回転数変化に比例した速度
検出データが確実に得られるデイジタル速度検出
装置を提供することを目的としている。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it focuses on the fact that the control data before and after the abnormal data when the rotation direction is reversed is normally detected. It is an object of the present invention to provide a digital speed detection device that can reliably obtain speed detection data proportional to a change in rotational speed even when switching from normal rotation to reverse rotation.

以下、この発明の一実施例を図について説明す
る。図中、第1図ないし第3図と同一の部分は同
一の符号をもつて図示した第4図及び第5図にお
いて、4aはラツチ及びリセツトパルス発生回路
で信号Nd,C,Mの各信号を入力とし信号Ndが
“1”のとき信号Mに同期して発生する信号Ra及
び前記信号Raからわずかに遅延して発生する信
号Rを発生する。9は信号D及びRaを入力信号
とし前記信号Dが“1”から“0”、又は“0”
から“1”に変化した後、信号Raが入力される
と1個だけ信号Raに同期したパルスを出力信号
Rbに出力する速度検出パルスカウンタリセツト
回路、5aは信号Rのパルス信号期間Ts内の信
号Mをカウントする速度検出パルスカウンタで信
号Mのカウント値は信号Pに出力され信号Rの立
下りでリセツトされる他に、信号Rbのパルス信
号が入力されると出力信号Pがリセツトされる機
能が優先して作動する。
An embodiment of the present invention will be described below with reference to the drawings. In FIGS. 4 and 5, the same parts as in FIGS. 1 to 3 are designated by the same reference numerals. In FIGS. When the signal Nd is "1", a signal Ra is generated in synchronization with the signal M, and a signal R is generated with a slight delay from the signal Ra. 9 uses the signals D and Ra as input signals, and the signal D changes from "1" to "0" or "0".
After changing from 1 to 1, when signal Ra is input, only one pulse synchronized with signal Ra is output.
A speed detection pulse counter reset circuit outputs to Rb. 5a is a speed detection pulse counter that counts the signal M within the pulse signal period Ts of the signal R. The count value of the signal M is output to the signal P and is reset at the fall of the signal R. In addition to this, when the pulse signal of the signal Rb is input, the function of resetting the output signal P is activated with priority.

次に本発明の動作を第4図及び第5図を参照し
回転体の回転方向が変化した場合を例に説明す
る。まず、第5図は第3図と同一時点での第4図
の回路動作を示したものでTsd期間内のb点にて
信号Dが“1”から“0”に変化した時、前記
Tsd′期間の終りのタイミングで信号Rbを発生さ
せ速度検出パルスカウンタ5aが信号Mのパルス
をカウント信号Pに“1”を出力すべきところを
信号Rbでリセツトし、信号Pは“0”となる。
従つて信号Rb発生後、次の信号Ra発生までの間
では検出された速度SfdはSfd=KPsd/Nsd=0(但 し、Psd=0) となり、切り替り時点においては常に“0”が検
出される。
Next, the operation of the present invention will be described with reference to FIGS. 4 and 5, taking as an example the case where the rotational direction of the rotating body changes. First, FIG. 5 shows the circuit operation in FIG. 4 at the same time as in FIG. 3. When the signal D changes from "1" to "0" at point b within the Tsd period,
The signal Rb is generated at the end of the Tsd' period, and the speed detection pulse counter 5a counts the pulses of the signal M and outputs "1" to the signal P. However, the signal Rb resets the pulse of the signal M and outputs "1" to the signal P, and the signal P becomes "0". Become.
Therefore, after the signal Rb is generated until the next signal Ra is generated, the detected speed Sfd is Sfd = KPsd / Nsd = 0 (however, Psd = 0), and "0" is always detected at the time of switching. Ru.

従つて、上記検出期間Tsdの一つ手前の期間で
は正転、一つ後の期間では逆転を検出しており該
当期間では、実際の速度は前後の値より“0”に
近い正転又は逆転の値になつていると予想され、
ロータリエンコーダを使用した場合の通常いわれ
ている低速検出の限界を考慮すると、切替え点で
の速度を“0”と近似することはきわめて妥当で
あると云える。
Therefore, forward rotation is detected in the period before the detection period Tsd, and reverse rotation is detected in the period after the detection period Tsd, and the actual speed is closer to "0" than the values before and after the detection period Tsd. It is expected that the value of
Considering the limitations of low speed detection that are usually said to occur when a rotary encoder is used, it can be said that it is extremely appropriate to approximate the speed at the switching point to "0".

以上のようにこの発明によれば、ロータリーエ
ンコーダを利用した回転体の速度検出方式での
正、逆転時の切替え点で回転方向検出信号を
“0”に一旦強制的にリセツトする回路構成とし
たので、速度検出信号として回転時は勿論、回転
方向切替時を問わず実際の速度に極めて近似の値
が確実に得られる優れた効果がある。
As described above, according to the present invention, the circuit configuration is such that the rotation direction detection signal is once forcibly reset to "0" at the switching point between forward and reverse rotation in the speed detection method of a rotating body using a rotary encoder. Therefore, there is an excellent effect that a value extremely close to the actual speed can be reliably obtained as a speed detection signal not only during rotation but also when switching the rotation direction.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来のデイジタル速度検出装置の一
例を示すブロツク構成図、第2図及び第3図は第
1図の要部の信号波形図、第4図は本発明の一実
施例を示すデイジタル速度検出装置のブロツク構
成図、第5図は第4図の要部の信号波形図であ
る。 1…回転方向判別回路、2…発信回路、3…タ
イミング回路、4,4a…ラツチ及びリセツトパ
ルス発生回路、5,5a…速度検出パルスカウン
タ、6…クロツクパルスカウンタ、7…第1バツ
フア回路、8…第2バツフア回路、9…速度検出
パルスカウンタリセツト回路。なお図中同一符号
は同一又は相当部分を示す。
FIG. 1 is a block configuration diagram showing an example of a conventional digital speed detection device, FIGS. 2 and 3 are signal waveform diagrams of the main parts of FIG. 1, and FIG. 4 shows an embodiment of the present invention. FIG. 5 is a block diagram of the digital speed detection device, and FIG. 5 is a signal waveform diagram of the main part of FIG. 4. DESCRIPTION OF SYMBOLS 1... Rotation direction discrimination circuit, 2... Transmission circuit, 3... Timing circuit, 4, 4a... Latch and reset pulse generation circuit, 5, 5a... Speed detection pulse counter, 6... Clock pulse counter, 7... First buffer circuit , 8...Second buffer circuit, 9...Speed detection pulse counter reset circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 1 回転体の回転数を位相差90゜の2相パルス信
号として発生するロータリーエンコーダと、前記
ロータリーエンコーダの2相パルス信号により回
転方向を判別する回転方向判別回路と、前記2相
パルス信号の内1相のパルス信号に同期した信号
を発生するタイミング回路と、前記タイミング回
路の出力パルスに同期した所定間隔の信号を発生
するラツチ及びリセツトパルス発生回路と、前記
タイミング回路のパルス信号を計数して行き、前
記ラツチ及びリセツトパルス発生回路の発生する
信号によりリセツトされる速度検出カウンタと、
前記回転方向判別回路の判別信号が反転した場
合、前記速度検出カウンタの計数値を強制的に帰
零する速度検出パルスカウンタリセツト回路と、
前記速度検出カウンタの計数値によつて前記回転
体の回転速度を算出する回路とを備えたことを特
徴とするデイジタル速度検出装置。
1 A rotary encoder that generates the rotation speed of a rotating body as a two-phase pulse signal with a phase difference of 90 degrees, a rotation direction determination circuit that determines the rotation direction based on the two-phase pulse signal of the rotary encoder, and a rotation direction determination circuit that determines the rotation direction from the two-phase pulse signal of the rotary encoder, a timing circuit that generates a signal synchronized with a one-phase pulse signal; a latch and reset pulse generation circuit that generates a signal at predetermined intervals synchronized with the output pulse of the timing circuit; and a latch and reset pulse generation circuit that counts the pulse signal of the timing circuit. a speed detection counter that is reset by a signal generated by the latch and reset pulse generation circuit;
a speed detection pulse counter reset circuit that forcibly resets the count value of the speed detection counter to zero when the discrimination signal of the rotation direction discrimination circuit is inverted;
A digital speed detection device comprising: a circuit for calculating the rotational speed of the rotating body based on the count value of the speed detection counter.
JP9977583A 1983-06-02 1983-06-02 Digital speed detector Granted JPS59224569A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9977583A JPS59224569A (en) 1983-06-02 1983-06-02 Digital speed detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9977583A JPS59224569A (en) 1983-06-02 1983-06-02 Digital speed detector

Publications (2)

Publication Number Publication Date
JPS59224569A JPS59224569A (en) 1984-12-17
JPH0412429B2 true JPH0412429B2 (en) 1992-03-04

Family

ID=14256327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9977583A Granted JPS59224569A (en) 1983-06-02 1983-06-02 Digital speed detector

Country Status (1)

Country Link
JP (1) JPS59224569A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61158343A (en) * 1984-12-29 1986-07-18 Konishiroku Photo Ind Co Ltd Automatic double face copying device
JP2002104149A (en) * 2000-09-29 2002-04-10 Toyota Motor Corp Rotating state detecting device for wheel

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5482256A (en) * 1977-12-14 1979-06-30 Matsushita Electric Ind Co Ltd Counter circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5482256A (en) * 1977-12-14 1979-06-30 Matsushita Electric Ind Co Ltd Counter circuit

Also Published As

Publication number Publication date
JPS59224569A (en) 1984-12-17

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