JPH04122039A - Pad for multiple pin semiconductor element test - Google Patents

Abstract

PURPOSE:To eliminate defectives in an assembly process and to improve yield by carrying out die sorter test in a wafer state without restriction by a probe card. CONSTITUTION:A first pad layer 4 consisting of a conductive metal layer such as Al or Al alloy (Al-Si, Al-Si-Cu) is formed in a part of a multiple layer wiring layer or in a space part between an I/O buffer cell region and a periphery of a semiconductor chip as a multiple pin semiconductor device pad which is indispensable for connection with an external device. A second pad layer 5 consisting of conductive metal which functions for a die sorter test is formed with an increased pitch in addition to the first pad layer 4. A metallic fine line 6 such as Al is fused between the pad layer 5 and the first pad layer 4 by a contact bonding method to realize an electrical conduction state. Then, a usual die sorter process is carried out by a second pad layer 5.

Description

Detailed Description of the Invention [Purpose of the Invention (Industrial Application Field) The present invention relates to an LSI with a multi-pin structure (Large-e 5ca
Qe Integrated Ci-rcuit
), especially its die sorter (Die 5ort).
er) suitable for testing.

(Prior Art) The degree of integration of semiconductor devices is increasing more and more, and the same trend is occurring in so-called gate arrays. In this model, for example, active elements are placed in a region surrounding the center of a 1 cm square semiconductor wafer.
A cell (CeQQ) group is formed by incorporating one or more types selected from a group consisting of circuit components such as passive elements and resistors, and I10 buffer device cells ( Dev
ice CeQQ) is formed.

In the present invention, the term "semiconductor unino\" refers to an area divided by a scribe line (ScribQine) to be formed, and refers to a region divided by a scribe line (ScribQine) to be formed.
Breaking (Brak) before assembly process such as onding process
ing) process has not been completed.

Even in gate arrays with this structure, as the degree of integration is increasing, so-called outer leads (outer leads) are required to make electrical connections with other devices.
The number of ead) is also on the rise. On the other hand, transfer molding is used in the assembly process of semiconductor devices.
In addition to the er MoQd) method, the bump (
The so-called TAB (Tap) uses a Bu-mp) electrode.
-e Automated Bonding) method is exclusively adopted.

By the way, as mentioned above, cells for gate arrays are composed of one or more types selected from the group consisting of circuit components such as active elements, passive elements, and resistors, and these are subjected to the so-called die sorter (Di-e 5-orter) test. This is done in the form of semiconductor wafers, which are then sent to the assembly process. Is the cell library base (CeQQ Library Ba5e) used for designing cells for gate arrays? ') Lay 0ut design is used, which is the most important process in LSI design.
Mask pattern for SI
). In this cell library-based layout design, a common cell library is generally used for both two-layer and three-layer wiring methods. This is no exception for cells on the periphery of semiconductor chips;
The 10 buffer cells are formed using one and two wiring layers.

Moreover, in the gate array, the distance between the I10 buffer cell and the periphery of the semiconductor chip is 50 μm to 150 μm, and in this space, conductive metal such as AQ or AQ alloy (AQ-8L-Cu,
A pad (P ad) layer made of AQ-6L) is formed. The distance between the pad layers is formed at 120 μm to 150 μm, and the wiring layers are used to electrically connect the pad layers to the cell group and I1.
0 buffer cell is established. On the other hand, the characteristics of the cell group can be measured using a known probe card (Prob-e Ca
The products are separated into non-defective products and defective products by a die sorter test using RD) before proceeding to the subsequent assembly process.

(Question 8 to be solved by the invention) In die sorter testing, it is essential to contact the needle (NeedQe) of the probe card with the pad layer electrically connected to the active elements, passive elements, etc. formed on the semiconductor device to be tested. It is. However, since the needles cannot be formed to be 80 μm or less, there is a limit to the pitch of the pad layer, and as a result, it has been impossible to form a multi-bin semiconductor element, such as a cell group. Furthermore, it has been found that semiconductor devices assembled by the TAB method have so-called bump electrodes made of gold, which are crushed by contact with the needle and have an adverse effect on the characteristics of the semiconductor device.

The present invention was developed under these circumstances, and in particular, by installing the measurement pad separately from the one electrically connected to the semiconductor element, it is possible to perform electrical measurement, thereby freeing the user from the restrictions of the needle. The purpose of this invention is to provide a small pitch pad for a semiconductor device.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor cell group formed in a region surrounding a central portion of a semiconductor wafer, and an interface region of the semiconductor element group installed near the periphery of the semiconductor wafer. , a multilayer wiring layer that electrically connects the interface region and the semiconductor element group, and a pitch formed near the outer periphery of the semiconductor wafer or in the multilayer wiring layer is 150 μm
The features of the multi-bin semiconductor device testing pad according to the present invention are in the pad layer below.

(Function) Semiconductor cells such as integrated circuit elements and transistors are placed in the central part of a semiconductor wafer, such as in a gate array, and an interface area such as Ilo is placed on the surrounding semiconductor chip, and further outside of this, a group of semiconductor cells such as integrated circuit elements and transistors is placed. A method of forming related pads for multi-pin semiconductor devices is adopted. This is because the second pad layer is formed to be larger than the pitch of the die sorter testing needles, which frees us from this constraint, and the second pad layer and the multi-bin semiconductor device pad are electrically connected using thin metal wires. Therefore, a method was adopted in which the die sorter test was performed using the second pad layer. By forming the second pad layer, the pitch of the pad for a multi-pin semiconductor device can be formed to be extremely small, less than 150 μm, regardless of the die sorter test, thereby making it possible to increase the number of pins.

(Example) To explain with reference to the top opening of an example of the present invention,
Semiconductor wafer 1 made of silicon (SiQicon)
A semiconductor cell group 2 consisting of semiconductor elements such as integrated circuit elements and transistors is installed in the center of the figure.The semiconductor cell group 2 and wiring layer 3 shown in the figure are for illustration purposes only, and are not accurate. It's not something. Further, the semiconductor cell group 2 may also be formed using a library-based layout design, as in the conventional example.

An interface region (not shown) for integrated circuit elements, transistors, etc. is formed in the peripheral portion of the semiconductor wafer 1, and a multilayer wiring layer 3 is used for connection with the semiconductor cell group 2. That is, the electrode terminals provided in the semiconductor cell group 2 are coated with a conductive metal layer such as AQ or AQ gold alloy AQ-Si, AQ-
For example, sputtering (Si-Cu)
ing) step for electrical connection, and then depositing an interlayer insulating layer and then further forming a conductive metal layer as a wiring layer 3, such as AQ or AQ gold alloy AQ-S i, AQ-5i.
-Cu) is deposited to establish electrical connection with the semiconductor cell group 2. Of course, as the wiring layer, a multilayer wiring structure such as a three-layer wiring structure can be used in addition to a two-layer wiring structure. Incidentally, each wiring layer constituting the multilayer wiring layer is connected to an interface area (not shown) formed in a portion of the semiconductor wafer 1 located outside the cell group 2, that is, an I10 buffer cell, and Connect the power line (L-i
ne) etc. are also formed, and the corners (
A self-test device, such as an oscillator, is also installed in the corner.

In addition, conductive metal layers such as Al or Al are used as pads for multi-bin semiconductor devices that are essential for connection with external equipment.
1 alloy (AQ-S i, AQ-S 1-Cu) is a part of the multilayer interconnection layer or I10
It is formed in a space between the buffer cell region and the periphery of the semiconductor chip. Additionally, photolithography is installed near the scribe lines formed on semiconductor wafers.
Mark for Li-thography
Similarly, the first pad layer 4 can also be formed in a space of 120 to 150 μm between the scribe line and the I10 buffer cell region. This is 80 μm to 100 μm square with a pitch of less than 150 μm. However, a second pad layer 5 made of conductive metal that functions as a die sorter test is formed separately from the first pad layer 4 with a large pitch in preparation for manufacturing a probe card equipped with needles.

A plurality of positions can be selected as the installation location of the second pad layer 5. That is, the portion of the semiconductor wafer outside the scribe line is normal. Also, this means that the pitch is 150 μm.
For example, the film is deposited in a square area of about 200 μm or 80 μm to 100 μm by vacuum evaporation or sputtering. Further, there is an A between the second pad layer 5 and the first pad layer 4.
After the thin metal wires 6 such as Q are fixed by a pressure bonding method, for example, a bonding method to make them electrically conductive, a normal die sorter process is performed using the second pad layer 5. As a result, the semiconductor characteristics of the semiconductor cell group 2 can be investigated, and defective products are marked with a predetermined mark and moved to the assembly process. Prior to proceeding to the assembly process, the thin metal wire 6 is cut by, for example, a plaid (B 1 ad) so that it will not be affected at all during the assembly process, such as a pre-king process. be able to. In an example in which the first pad layer 4 and the second pad layer 5 are connected by a thin metal wire 6 along a dicing line (D-icing line), it is possible to cut the first pad layer 4 and the second pad layer 5 at the time of the pre-king process. As described above, the multi-pin semiconductor device testing pad according to the present invention can ignore the minimum pad pitch distance required by the probe card used for die sorter testing, making it possible to build in the large number of pins required for the semiconductor device. It has great features.

[Effects of the Invention] In the present invention, ■ Since the die sorter test is performed on the wafer without the constraints of a probe card, the yield (YieQd) can be improved because defective products can be removed in the assembly process, and ■ There is no constraint due to the probe card. Since the pitch of the pads can be determined by
■Since there is no need for the probe card to touch the pads inside the semiconductor chip, models that use the TAB method can prevent damage to the bump electrodes, improve reliability, and maintain semiconductor characteristics over a long period of time. can be demonstrated over a period of time.

[Brief explanation of the drawing]

The figure is a top view showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1: Semiconductor chip, 2: Cell group, 3: Wiring layer, 4: First pad, 5: Second pad, 6: Fine metal wire. Agent Patent Attorney Norihiro Ogo 1: f-bribe body/tsu 1 2: cell group 3-wiring layer 4: ii”ll nomad 5; note 2 nomad 6: gold! M line

Claims (1)

[Claims] A semiconductor cell group formed in a region surrounding a central portion of a semiconductor wafer, an interface region for the semiconductor element group installed near the periphery of the semiconductor chip, and a multilayer wiring electrically connecting the interface region and the semiconductor element group. A pad for testing a multi-pin semiconductor device, comprising a pad layer having a pitch of less than 150 μm and formed near the outer periphery of the semiconductor wafer or in the multilayer wiring layer.