JPH04120979A - Clamping circuit for video signal - Google Patents

Abstract

PURPOSE:To prevent the insertion or the invasion of an undesired clamping pulse to a vertical synchronizing signal and to improve the processing error in the case of using a line selector or of digital processing by stopping the supply of the clamping pulse to a clamping circuit while the vertical synchronizing signal is present thereon. CONSTITUTION:An input video signal is subjected to DC recovery by a pedestal clamping circuit composed of a transistor (TR) 1 based on a clamping pulse fed to its base via a capacitor C2. On the other hand, a vertical synchronizing signal V.SYNC is fed to the base of a TR 2 via a capacitor C3, and since the TR 2 flows a clamping pulse fed to its emitter to ground when the V.SYNC is fed to the TR 2, no clamping pulse intrudes to the vertical synchronizing signal. Thus, the vertical synchronizing signal having no undesired clamping pulse is obtained and the video signal is clamped to the low level of the clamp pulse within the period and SYNC tip clamping is implemented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a video signal clamp circuit, and more particularly to a video signal clamp circuit that prevents unnecessary ramp pulses from being mixed in during a vertical synchronization period.

(Prior Art) In order to keep the synchronization signal end (sync chip) and pedestal level constant, a clamp circuit is widely used that uses a clamp pulse to clamp the pedestal portion of the video signal.

FIG. 4 shows an example of a conventional video signal clamp circuit.

The video signal Video is connected to the emitter of the NPN transistor 1 via a capacitor C1, and an output signal is taken out from this emitter. A power supply +Vcc is supplied to the base and collector of the transistor 1 via a resistor R8, and the base is grounded via a resistor R2.

As shown in FIG. 5, the clamp pulse is output as a predetermined synchronized clamp pulse using a pulse signal that is synchronously separated from the horizontal synchronizing signal of the video signal and shifted in phase by a predetermined phase. In other words, the clamp pulse is inserted within the horizontal period (within the back porch).

By supplying this clamp pulse to the base of transistor 1 via capacitor C2, a pedestal level clamping operation is performed.

(Problems to be Solved by the Invention) As described above, the conventional video signal clamp circuit inserts a clamp pulse at the back porch timing position of the horizontal synchronization signal.

However, when the clamp pulse is inserted within the horizontal period (inside the back porch), the timing matches the pedestal position within this horizontal period, so normal ramp operation is performed, but the following problems occur within the vertical synchronization signal. .

That is, as shown in FIG. 6, the clamp pulses generated at a predetermined period may not coincide with the pedestal portion and may fall within the vertical synchronizing signal. An example in which a ramp pulse is inserted as an extra pulse is shown in FIG.

Such unnecessary insertion or mixing of clamp pulses is inappropriate when digitally processing a video signal and counting its vertical synchronizing pulses.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal clamp circuit that prevents insertion of a clamp pulse into a vertical synchronization signal.

(Means for Solving the Problems) In order to solve the above-mentioned problems, a video signal clamp circuit according to the present invention provides vertical synchronization in a video signal clamp circuit that clamps a video signal at a pedestal level based on a clamp pulse. The clamp circuit is configured to include a circuit that blocks supply of the clamp pulse to the clamp circuit based on a signal indicating the presence of the signal.

(Operation) In this invention, the clamp pulse is prevented from being inserted into the vertical synchronizing signal by blocking the supply of the clamp pulse to the clamp circuit using a signal indicating the presence of the vertical synchronizing signal.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a video signal clamp circuit according to the present invention.

In FIG. 1, elements given the same reference numerals as those in FIG. This is the difference from the conventional method.

The input video signal Video is DC-regenerated by a pedestal clamp circuit constituted by a transistor 1 based on a clamp pulse supplied to the base via a capacitor C2. On the other hand, the base of the transistor 2 is supplied with the vertical synchronizing signal 5YNC via the capacitor C1, and when the V5YNC is supplied, the transistor 2 connects the clamp pulse supplied to the emitter to the ground side. Therefore, the clamp pulse does not enter the vertical synchronization signal.

That is, as shown by the dotted line (diagonal line) in FIG. 2, in the case of the conventional circuit, the clamp pulses CPI and C20 normally work as ramp pulses because their timings coincide with the pedestal portion, but the clamp pulses CP2. CP3. C
Since P4 does not coincide with the timing of the pedestal portion, it does not work as a clamp pulse and enters the vertical synchronizing signal as an unnecessary pulse.

However, according to the embodiment of the present invention, the clamp pulse is bypassed to the ground side by the vertical synchronization signal, so it does not enter the vertical synchronization signal, and as shown in FIG. I get a signal. In the vertical synchronizing signal section where there is no clamp pulse, the clamp pulse is clamped at a low level, and as a result, a sync tip clamp operation is performed.

(Effects of the Invention) As explained above, the video signal clamp circuit according to the present invention prevents the clamp pulse from being supplied to the clamp circuit while a vertical synchronization signal is present, so that the vertical synchronization of the ramp pulse becomes unnecessary. It is possible to prevent insertion and mixing into the signal, and it is possible to improve the problem of processing errors when using a line selector or during digital processing.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a video signal clamp circuit according to the present invention, FIGS. 2 and 3 are diagrams for explaining the operation of the embodiment shown in FIG. 1, and FIG. FIGS. 5 to 7 are diagrams illustrating examples of conventional video signal clamp circuits, and are diagrams for explaining the operation of the conventional video signal clamp circuit shown in FIG. 4. 1.2...Transistor.

Claims (1)

[Scope of Claims] In a video signal clamp circuit that clamps a video signal at a pedestal level based on a clamp pulse, a circuit that blocks supply of the clamp pulse to the clamp circuit by a signal indicating the presence of a vertical synchronization signal. A video signal clamp circuit comprising: