JPH04119734A - Byte synchronizing circuit - Google Patents

Abstract

PURPOSE:To establish 8Xn-bit synchronization by discriminating synchronizing location of 8Xn-bit synchronization in response to the time sequence of synchronization establishment of a 8-bit synchronizing circuit and applying prescribed replacement to an 8Xn-bit parallel input data for each 8-bit. CONSTITUTION:An 8-bit synchronizing circuit 121 establishes 8-bit synchronization and other 8-bit synchronizing circuits 122-124 establish 8-bit synchronization similarly. In this case, the time of establishing the synchronization in the 8-bit synchronizing circuits 121-124 differs from the state of deviation between a 32-bit parallel input data Din and the time location to be synchronized. Then changeover of a port changeover circuit 11 is controlled by using a control signal DP of the port changeover circuit outputted from the 8-bit synchronizing circuits 121-124 at the synchronization establishment to establish 32(8X4)bit synchronization.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to synchronous digital multiplex transmission 'fA (SDH: 5
ynchronous Digital Hierar
chy), synchronous multiplex signal (STM-n signal)
The present invention relates to a byte synchronization circuit that establishes synchronization of 8×n bits when expanding the data into 8×n bits.

The STM-n signal has a frame format in which n STM-1 signals are multiplexed (n is any integer, but 1.4.16 is currently used), and is configured based on byte multiplexing. ing. Therefore, in order to perform the termination processing of the STM-n signal at low speed, the STM-n signal must be converted into a byte-by-byte parallel signal, that is, 8×n bits (n bits of 1 byte).
parallel signals).

[Conventional technology]

The byte synchronization circuit is usually placed before the frame synchronization circuit, and receives received digital data and a bit clock for which bit synchronization has been established, and performs byte synchronization in units of bytes embedded in the frame synchronization pattern. Extract the pattern (fixed pattern for frame synchronization) and
The configuration is such that the phase is correctly matched in units of n bits (n bytes).

FIG. 7 is a block diagram showing a configuration example of a conventional byte synchronization circuit.

Note that the circuit shown here has a configuration that synchronizes 32 (8×4) bit parallel data (4 bytes).

In the figure, 32-bit parallel input data Din and input clock C are received digital data and a pit clock with which bit synchronization has been established.

31 bits) The D latch circuit 71 receives parallel input data Di.
The lower 31 bits of n and the input clock CK are input,]
The time slot delayed output (D (62 2 32)) is parallelized to the parallel input data D in (D (31:O)) to become 63 pinto parallel data D (62:0).

Here, D (x:Y) represents a parallel signal consisting of bits from the χ bit to the y bit among the n signals consisting of 63 bits. However, the 0th bit indicates the least significant bit, and the 62nd bit indicates the most significant bit.

The 63-bit parallel data D (62:O) is processed by a 32-bit number construction circuit 72. ~723
Input to terminal A of □. A 32-bit frame synchronization pattern is input to the terminal B. 32-bit/7-bit coincidence detection circuit 72. The coincidence detection output of 723□ is output from the flip-flop 73. .about.733□, and their outputs are input to one input terminal of each of AND'r'-)741 to 743□. The other input terminals of each of the AND gates 75° to 75,7 are connected to respective 32-bit match detection circuits 72.
Input data of ~723□ is input, and the output data is outputted via an OR gate 75 as byte-synchronized parallel output data Dout.

Also, a 32-bit number construction circuit 72. The match detection outputs of ˜723□ are branched and input to the OR gate 77. The output of the OR gate 76 is inputted to the AND gate 77 together with the enable signal EN, and the output is applied to each flip-2
0 Tsubu 73. ~733□ is sent as a clock.

In the figure, the number shown with / on the signal line (■) indicates the number of parallel data in focus.

Next, the operation of this byte synchronization circuit will be explained.

In the 31-pin ID launch circuit 71, parallel input data D
The 31 bits of the first position excluding the most significant bit (MSB) of in are delayed by 1 time slot, and 63 bits of parallel data D (62:0) is generated together with the 32 bits of parallel input data input to the next time slot. generate, 0 to 31
32-bit parallel data D (62:31) with each shift amount up to bit shift, r-'l (6]:30
), ..., D (31:O) is obtained.

-L of 63-bit parallel data D (62:0)
The 32-bit data D (62:31) is input to the 32-pinto-number construction circuit 721, and the 32-bit parallel data D (6i
:30), . -On the other hand, 32
Bi...policy detection circuits 72, ~723. CCIT
A frame synchronization pattern (AIAIAIAI) consisting of four consecutive frame synchronization fixed patterns A1, which is one of the fixed patterns within the frame defined by T, is input, and parallel data D (62:31) and D (61 :30
) , . . . A match with D(31:O) is detected.

Now, the fixed pattern A1 for frame synchronization is (11110
1101, and the 32-bit parallel input data Din is shifted by 7 bits from the position to be synchronized, as shown in FIG. This minus number output is the OR gate 7
6. Each flip-flop 73 via an AND gate 77
．． ~73,2 clock input, and each flip-flop 73. ~733□, each 32-bit coincidence detection circuit 72.
~723□ output is set. At this time, since the coincidence detection is output from the 32-bit number construction circuit 727, the output of the flip-flop 737 becomes high level, and the corresponding AND gate 74. Parallel data D (56:25) input to is outputted via the OR gate 75.

In this way, synchronization of 4 bytes (8x4 bits) is established, and the AND gate 74? The data passing through becomes parallel output data Dout.

Furthermore, every time an out-of-synchronization is detected outside this byte synchronization circuit, the enable signal EN becomes high level.
The above synchronization detection operation is repeated.

[Problem to be solved by the invention]

The conventional byte synchronization circuit, as mentioned above,
For 8.times.n bit parallel data having each shift amount up to an n-bit shift, it was necessary to perform coincidence detection using 8.times.n 8.times.n bit-number construction circuits. The configuration example shown in FIG. 7 is for n=4, which requires 32 32-bit number construction circuits, and the circuit scale increases dramatically as the number of parallel bits increases.

In addition, the 8Xn pinot (n byte) synchronous circuit is dedicated to 8XnXn pits for n-byte multiplexed STM-n signals, and when 0 STM-1 signals are used, each ST
It was impossible to use it as an 8-bit synchronous circuit for the M-1 signal.

The present invention realizes 8XnXn pit detection and adjustment of input data expanded in parallel into 8xn bits on a small circuit scale, and further enables the use of an 8xn bit synchronous circuit as n independent 8-bit synchronous circuits. The purpose of this invention is to provide a byte synchronization circuit.

[Means to solve the problem]

The invention according to claim 1 provides a byte synchronization circuit that establishes byte-by-byte synchronization for byte-multiplexed 8×n-bit parallel input data of an STM-n signal in SDH. a port switching circuit that receives input data in 8 bits each from n input ports and switches the output to n output ports in 8-bit units according to a predetermined control signal; A delay circuit that gives a predetermined delay to the least significant 7 bits among ×n bits, and each 8-bit data outputted by 8 bits each from the n output ports of the port switching circuit are defined as the lower side, and the 8 bits are For the most significant 8-bit data of the data, the 7-bit data output from the delay circuit is configured as the upper side, and for each of the other 8-bit data, the upper 7-bit data is configured as the upper side. n 8-bit data that takes in 15-bit data, establishes 8-bit synchronization for each, outputs it as 8 x n-bit parallel output data, and outputs the predetermined control signal indicating the time order of synchronization establishment. and a synchronous circuit.

The invention according to claim 2 provides 8×n bits of parallel input data of STM-n signals in SDH, or n STM-n signals.
In a byte synchronization circuit that establishes byte-by-byte synchronization for 8 x n bits of parallel input data of the TM-1 signal, 8 bits of parallel input data of 8 x n bits are taken in from n input ports, 8 bits each. a port switching circuit that switches outputs to the n output ports in 8-bit units according to a predetermined control signal, and disables the switching operation according to a predetermined external signal; n delay circuits that provide a predetermined delay to the lower 7 bits of each 8-bit data output from the output port, and the most significant of the 8×n bits output from the port switching circuit. The 7-bit data output from the delay circuit for 8-bit data is used as one input, the 7-bit data output from the delay circuit for the lowest 8-bit data is used as the other input, and the 7-bit data output from the delay circuit for the lowest 8-bit data is used as the other input. One selection circuit selects and outputs one of them, and one input is the 7-bit data output from the delay circuit for the other 8-bit data among the 8×n-bit output of the port switching circuit, and each n-1 selection circuits that take upper 7-bit data as the other input and selectively output one of them in response to the predetermined external signal; and 7-bit data output from each of the selection circuits as the upper side. , takes in n pieces of 15-bit data, each consisting of the corresponding 8-bit data as the lower-order side, establishes 8-bit synchronization for each, outputs it as 8 x n-bit parallel output data, and determines the time order of the synchronization establishment. and n 8-bit synchronous circuits that output the predetermined control signal indicating When operating as n independent 8-bit synchronous circuits, the port switching circuit is disabled by the external signal, and the input data of one of the selection circuits is selectively output. composition.

[For production]

According to the first aspect of the invention, 8×n bits of parallel input data are expanded into 8-bit units to generate 15-bit data, and 8-bit synchronization is established using n 8-bit synchronization circuits. At this time, the synchronization position of 8×n bits is determined according to the time order of synchronization establishment of each 8-bit synchronization circuit, and the 8×nXn A pit can be established. That is, an 8×n bit synchronous circuit can be realized by n 8-bit synchronous circuits.

The invention set forth in claim 2 combines the configuration of the invention set forth in claim 1 with the configuration of the invention set forth in claim 1 when expanding 8×n bits of parallel input data into 8-bit units, and
By selecting a configuration that generates 5-bit data, it can be used as an 8 x n-bit synchronous circuit, and
It becomes possible to use n 8-bit synchronous circuits independently.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment corresponding to the invention set forth in claim 1.

Note that the embodiment circuit shown here has a configuration that synchronizes 32 (8×4) bit parallel data (4 bytes), similarly to the description of the conventional circuit.

In the figure, 32-pin parallel input data Din is divided into 8-bit units starting from the most significant bits and sent to the port switching circuit 1.
1 to each input port #1 to #4. An input clock CK and an enable signal EN are input to the port switching circuit 11, and the output data output from each of the output ports #1 to #4 is sent to the corresponding 8-bit synchronization circuit 12. ~124 are input.

Also, of the output data of output port #4 of the port switching circuit 11, 7 bits (except for the most significant bit) (MSB)
The least significant 7 bits of 32-bit parallel input data) are 7
The output, which is input together with the input clock CK to the bit D latch circuit 13 and delayed by one time slot, is input to the 8-bit synchronization circuit 121 as the upper bit of the output data of output port #1.

Also, of the output data of output port #1, 7 bits of data (D(14:8)) excluding the MSB are 8 bits as the upper pin of the output data of output port #2 (D(7:0)). It is input to the synchronization circuit 122.

Similarly, 7-bit data excluding the MSB of the output data of output port #2 is sent to the 8-bit synchronous circuit 12, and 7-bit data excluding the MSB of the output data of output port #3 is sent to the 8-bit synchronous circuit 12. is input.

In addition, each 8-bit synchronization circuit 12. The enable signal EN is input to ~124, the output data (8 bits) is parallelized, and the byte-synchronized parallel output data (32
bit) Output as Dout. Further, each of the 8-bit synchronous circuits 121 to 124 outputs a port switching circuit control signal DP, which is input to the port switching circuit 11 as a 4-bit signal.

FIG. 2 is a block diagram showing an example of the configuration of the 8-bit synchronization circuit 12.

In the figure, 15-bit parallel data D (14:0)
are 8-bit number construction circuits 21° to 21. is input to terminal A of. An 8-bit frame synchronization pattern A1 is input to the terminal B. The coincidence detection outputs of the 8-bit number construction circuits 211 to 218 are sent to the flip-flops 22. ~22s, respectively, and their outputs are held at AND gates 23~23. is input to one input terminal of each. ANDGATE 23. The input data of each of the 8-bit coincidence detection circuits 21t to 2ts is input to the other input terminal of each of the circuits 21t to 238, and the output data thereof is outputted via the OR gate 24.

In addition, the 8-bit number construction circuit 21. The coincidence detection outputs 218 to 218 are branched and input to the OR gate 25. The output of the OR gate 25 is taken out as the port switching circuit control signal DP, and is also input to the AND gate 26 together with the enable signal EN, and the output is sent to each flip-flop 22 . ~22, is sent out as a clock.

The operation of the 8-bit synchronization circuit 12 shown in FIG. 1 will be explained below.

This 8-bit synchronization circuit 12. The input data is the output data of the output port #1 of the port switching circuit 11 (D(7:O
)) is the lower 8 bits, and the output data (D (14:8)) of the 7-bint D latch circuit 13 is the upper 7 bits.

Among the 15-bit parallel data D (14:0), the upper 8 pinto data D (14 near) is 8 bits ~
・Several Exit Route 21. 8-bit parallel data D (13:6
), ..., D(7:I)) are 8 bits - number construction circuit 2
]z~21s is input. On the other hand, the frame synchronization pattern AI is input to the 8-bit number configuration circuits 21 and 21-1, and the parallel data D (14 near) and D (1
3:6), . . . , D(7:O) is detected.

Now, the frame synchronization pattern A1 is rllllol, 1
0], and the 32-bit parallel input data Din is the eighth
As shown in the figure, if there is a shift of 7 bits from the position to be synchronized, the 8-bit number construction circuit 217 detects the coincidence. This minus number output is transmitted to each flip-flow knob 22 . ~
228 clock inputs, each flip-flop 22
1 to 2211 each have an 8-bit coincidence detection circuit 21. ~21.
The output of is sent. At this time, since the coincidence detection is output from the 8-bit number configuration circuit 217, the flip-flop 22. output becomes high level, and the parallel data D (8:1
) is output via the OR gate 24.

In this way, the 8-bit synchronization circuit 12. Then, 8-bit synchronization is established, and other 8-bit synchronization circuits 12□ to 12
4, 8-bit synchronization is established in the same way. In addition, 32
Bit synchronization will be described later.

At this time, the times at which synchronization is established in each of the 8-bit synchronization circuits 121 to 124 differ depending on the state of deviation of the 32-bit parallel input data Din from the position to be synchronized. FIG. 3 is a diagram explaining the situation.

In FIG. 3, the parallel input data Din is expressed as serial input data in order to make it easier to understand the bit positions and input order. In the figure, the numbers in parentheses indicate the number of bits of parallel input data.

The time when 32-bit parallel input data Din is input is T.
o, T+, and Tz, data input at time T0 is DA, data input at time T is DA, and data input at time T2 is DA.

Here, if the 32-bit parallel input data Din is shifted by 7 bits from the position to be synchronized as shown in FIG. 8, and the beginning of the data including the frame synchronization pattern is input at time T1, the frame synchronization pattern AlAlAlAl is , corresponds to the shaded area shown in FIG.

By the way, at time T, the 8-bit synchronization circuit 121
Then, the lower 7 of the 32-bit data at the previous time T0
The upper 8 bits and 7 bits of the 32-bit data at time T are 1 of the upper 7 bits and 1 of the lower 8 bits, respectively.
5-bit input data a.

becomes. Similarly, in the 8-bit synchronization circuits 12□ to 124, predetermined 15 bits at time T1 are input data a2
~a4.

Therefore, at time T1, each of the 8-bit synchronous circuits 12° to 12.
To establish 8-bit synchronization, it must be ('aa, ~
Frame synchronization pattern A1 must be detected within 15 bits of a4.

However, the 8-bit synchronous circuit 12. Since the frame synchronization pattern A1 is not detected in the input data a,
Bit synchronization circuit 12. 8-bit synchronization is not established at time TI. On the other hand, 8-pin synchronization circuit 12□~124
Since the frame synchronization pattern A1 is detected in the input data a2 to a4, the 8-bit synchronization circuits 12□ to 12
4, 8-bit synchronization is established at time T1.

Furthermore, an 8-bit synchronization circuit 12. Then, frame synchronization pattern A is included in the input data b corresponding to the next time T2.
Since I is detected, the 8-bit synchronization circuit 121 detects time T.
8-bit synchronization is established at 2.

Each of the 8-bit synchronous circuits 12 described above. FIG. 4 shows the timing for establishing 8-bit synchronization at times 124 to 124. As shown in the figure, the 8-bit synchronous circuits 12□ to 124 simultaneously
To establish focus synchronization, an 8-bit synchronization circuit 12. is 8
Establishment of bit synchronization is delayed by one time slot.

The timing at which this 8-bit synchronization is established varies depending on the deviation of the 32-bit parallel input data Din from the position to be synchronized. That is, in the case of a focus shift of 1 to 8 bits, the 8-bit synchronization circuits 12□ to 124 simultaneously establish 8-bit synchronization, and in the case of a shift of 9 to 16 bits,
First, 8-bit synchronous circuit 12! , 124 simultaneously establish 8-bit synchronization, and in the case of a deviation of 17 to 24 bits, the 8-bit synchronization circuit 124 establishes 8-bit synchronization first, and
In the case of a deviation of 5 to 31 bits or in the case of no deviation, the 8-bit synchronization circuit 12. ~12. simultaneously establishes 8-bit synchronization.

Therefore, when 8-bit synchronization is established in any 8-bit synchronization circuit, the 32-bit synchronization position can be determined based on the synchronization established state of the other 8-bit synchronization circuits. That is,
Each 8-pin synchronization circuit 12. 32 (8X
4) Bit synchronization can be established, as described below.

FIG. 5 is a block diagram showing an example of the configuration of the port switching circuit 11.

In the figure, a 4-bit port switching circuit control signal DP is input to a port switching determination circuit 3.

This port switching determination circuit 31 includes a flip-flop 32 that holds the port switching circuit control signal DP for each bit.
1 to 324, a NOR gate 33 that calculates the NOR of the outputs of the flip-flops 32 and 324, and a NOR gate 3
The output of each flip-flop 32. .about.322 clock, and each flip-flop 32.~322 from the enable signal EN. It is composed of a flip-flop 35 and an AND gate 36 that generate .about.324 reset signals. Note that the inverter 37 and the OR gate 38 are
Although this configuration corresponds to the embodiment described later, it does not affect the operation of this embodiment.

Input data of input port #1 is input to port selector 41. The input data of input ports #2 to #4 are input to the selector 42 via one input end of each of the selectors 422 to 424 and 8-bit D latch circuits 43□ to 434, respectively.
Connected to the other input terminal of each of □ to 424, and connected to the selector 42
The outputs of □ to 424 are input to the port selector 41.

The output of the port switching determination circuit 31 is transmitted to the port selector 41.
It is connected to the switching control terminal of each of the selectors 422 to 424 via the code conversion circuit 44. Each output of the port selector 41 is connected to output ports #1 to #4, respectively.

The operation of the port switching circuit 11 will be explained below.

The port switching determination circuit 31 receives the port switching circuit control signal D.
When 1 pin of P indicates establishment of synchronization, each 8-bit synchronization circuit 12. The synchronization establishment state of ~124 is determined.

That is, when 1 bit of the port switching circuit control signal DP indicates establishment of synchronization, each flip-flop 32. ~3
24 holds the synchronization establishment state of each of the 8-bit synchronization circuits 12 to 124. The 4-bit control signal held by the port switching determination circuit 31 is input to the code conversion circuit 44, and is converted into a 3-bit control signal according to the input signal and output signal conversion logic shown in Table 1.

Table 1 When the input signal of the code conversion circuit 44 is (00003,
That is, 8-bit synchronization circuit 12. If synchronization has not been established in any of the nodes 124 to 124, [000] is output so as not to cause any delay to the input data.

Furthermore, when the input signal is (0001), that is, when only the 8-bit synchronization circuit 124 has established synchronization, a delay is given to the input data from input port #4 (0
01) Outputs.

Also, when the input signal is [0011], that is, when the 8-bit synchronization circuit 12:+, 124 establishes synchronization, the input data from input ports #3 and #4 are delayed [011]. Output.

Also, when the input signal is [0111], that is, when the 8-bit synchronization circuits 12□ to 124 establish synchronization,
[111) is output so as to give a delay to the input data from input ports #2 to #4.

Further, when the input signal is (1111), that is, when the 8-bit synchronization circuits 12 to 124 establish synchronization, (000) is outputted so as not to cause any delay to the input data.

The 3-bit control signal output by the code conversion circuit 44 is
Each selector 42□ to 424 corresponds to each focus, and each selector 42□ to 424 selects input data when the control signal is rQ, and selects input data when the control signal is "1".
The above-mentioned delay processing is performed to select the delayed outputs of the l-D latch circuits 43□ to 434. Note that this is to avoid data loss due to synchronization establishment processing.

Furthermore, if a delay is given to the input data at this time, the order of the input data will be changed, so the port selector 41 performs processing to rearrange the data in the correct order.

Table 2 shows the correspondence between input ports and output ports for the 4-bit control signal held by the port switching determination circuit 31.

In the case of this embodiment in which the parallel input data Din in Table 2 has the deviation shown in FIG.
124, the port switching circuit control signal DP becomes (0111), so a delay is added to the data input from the input ports #2 to #4 of the port switching circuit 11, and furthermore, the port switching circuit control signal DP becomes (0111). By transmitting the data of input port #1 to the lower order of input ports #2 to #4, 32-pinto synchronization can be established.

FIG. 6 is a block diagram showing the configuration of an embodiment corresponding to the invention set forth in claim 2.

This embodiment shows a configuration for use not only as a 32-bit synchronous circuit but also as four independent 8-bit synchronous circuits.

In the figure, 32-bit parallel input data Din is divided into 8 bits from the most significant bits and input to the port switching circuit 1.
1 to each input port #1 to #4. The port switching circuit 11 has an input clock CK and an enable signal EN.
and external select signal SEL are input, and the 8-bit output data (D(7:O)) output from each of the output ports #1 to #4 is transmitted to the corresponding 8-bit synchronization circuit 12. ~12° is input.

Also, among the output data of output ports #1 to #4 of the port switching circuit 11, 7 bits excluding the most significant bit (MSB) are inputted to the 7-bit D latch circuits 13° to 134 together with the input clock CK. The time slot delayed outputs (D(14:8)) are sent to the selectors 14.
~144. Selector 14.
The output of the 7-bit D latch circuit 134 is connected to the other input terminal of the 7-bit D latch circuit 134, and the most significant pitch among the output data of the output ports #1 to #3 is connected to the other input terminals of the selectors 14□ to 144. 7 bits except l-(MSB) are input.

The external select signal SEL is sent to each selector 14. ~144 selection control is performed, and its output (D (14:8)) is the upper 7 bits of the 8-bit data output by each output port #1 to #4, and the 8-bit synchronization circuit 121 outputs a total of 15 bits of data. ~124 are input.

In addition, an enable signal EN is input to each of the 8-bit synchronization circuits 121 to 124, and the output data (8 bits) is parallelized, and byte-synchronized parallel output data (32
bit) Output as Dout. In addition, each 8-bit synchronization circuit 12. -124 each output a port switching circuit control signal DP, which is input to the port switching circuit 11 as a 4-bit signal.

Here, when used as a 32-bit synchronous circuit,
Set the external select signal SEL for the 32-bit synchronization circuit. In other words, the external select signal S at /S4 level
EL becomes low level via the inverter 37 in the configuration of the port switching circuit 11 shown in FIG. 5, and the port switching determination circuit 31 is enabled.

Further, when this external select signal SEL becomes a noise level, the selector 14. selects the output of the 7-bit D launch circuit 134, and selectors 142 to 144 select the MSB of the output data of output ports #1 to #3, respectively.
Select 7 bits excluding .

The above configuration is the same as the embodiment configuration shown in FIG.
Similarly, it can be operated as a 32-bit synchronized circuit.

Next, a case where the circuit is used as an 8-bit synchronous circuit will be explained.

In this case, the external select signal SEL is set for the 8-bit synchronous circuit. In other words, the low level external select signal SEL becomes high level through the inverter 37, and goes through the OR gate 38 to each flip-flop 3.
2. ~324 is input to the clear terminal CR, and the port switching determination circuit 31 is disabled. therefore,
In the port switching circuit 11, input/output ports #1 to #4 are respectively set to through.

Further, when the external select signal SEL becomes low level, the selector 14. ~144 are each 7-bit D bit 1,000 circuits 13. -134 outputs are selected.

Therefore, the 8-bit synchronization circuit 12. -124 each have a 7-bit D-later circuit 13. The data output by ~134 (D(14:8)) is the upper 7 bit data,
Data output by each output port #1 to #4 (D(7:O
)) as lower 8 bit data and 15 bit data D
(14:O) is input, and 8-bit synchronization is established independently.

In this way, by switching the external select signal SEL, it is possible to select between a 32-bit synchronous circuit and four independent 8-bit synchronous circuits.

〔Effect of the invention〕

As mentioned above, the present invention provides an SDH STMn signal with 8
Synchronization of ×n bits of parallel input data can be achieved by using n 8-bit synchronization circuits and a port switching circuit that switches data in units of 8 bits. Each 8-bit synchronization circuit has eight 8-bit number construction circuits for detecting coincidence of 8-bit frame synchronization patterns, and n 8-bit synchronization circuits provide 8×n circuits, but the conventional 8× Compared to a configuration in which an n-bit synchronous circuit requires 8Xn bit-number construction circuits, the circuit scale can be significantly reduced.

Further, by disabling the port switching circuit, it can be constructed as n independent 8-bit synchronization circuits, and can also be used as a synchronization circuit for nine STM-1 signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment corresponding to the invention set forth in claim 1. FIG. 2 is a block diagram showing an example of the configuration of an 8-bit synchronization circuit. FIG. 3 is a diagram explaining the difference in synchronization establishment time in each 8-bit synchronization circuit. FIG. 4 is a diagram showing synchronization establishment timing of each 8-bit synchronization circuit. FIG. 5 is a block diagram showing a configuration example of a port switching circuit. FIG. 6 is a block diagram showing the configuration of an embodiment corresponding to the invention set forth in claim 2. FIG. 7 is a block diagram showing a configuration example of a conventional byte synchronization circuit. FIG. 8 is a diagram showing an example of 32-bit parallel input data. 11... Port switching circuit, 12... 8-bit synchronization circuit, 13... 7-bit D latch circuit, 14... Selector, 21... 8-bit number configuration circuit, 22... Flip-flop P, 23...and gate, 24...
OR gate, 25... OR gate, 26... AND gate, 31... Port switching determination circuit, 32... Flip-flop, 33... NOR gate, 34... AND gate, 35... Flip-flop , 36...
AND gate, 41...port selector, 42...
Selector, 43...8-bit D latch circuit, 44...
・Code conversion circuit, Din...Parallel input data, Do
ut...parallel output data, CK...input clock,
EN...Enable signal, SEL...External select signal, DP...Port switching circuit control signal. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (2)

[Claims] (1) In a byte synchronization circuit that establishes byte-by-byte synchronization for byte-multiplexed 8×n-bit parallel input data of STM-n signals in SDH, 8×n-bit parallel input data is A port switching circuit that takes in 8 bits from each input port and switches the output to n output ports in 8 bit units according to a predetermined control signal, and 8 bits of output from the port switching circuit.
xn bits, a delay circuit that provides a predetermined delay to the least significant 7 bits, and 8 bits from each of the n output ports of the port switching circuit.
Each 8-bit data output bit by bit is the lower side,
For the most significant 8-bit data among the 8-bit data, the 7-bit data output from the delay circuit is configured as the upper side, and for each of the other 8-bit data, the upper 7-bit data is configured as the upper side. n pieces of 15-bit data, each establishing 8-bit synchronization, outputting it as 8 x n-bit parallel output data, and outputting the predetermined control signal indicating the time order of synchronization establishment. A byte synchronization circuit comprising: an 8-bit synchronization circuit. (2) 8 x n-bit parallel input data of STM-n signals in SDH, or 8 x n-bit parallel input data of n STM-1 signals
A byte synchronization circuit that establishes byte-by-byte synchronization for n-bit parallel input data takes in 8 x n-bit parallel input data from n input ports, 8 bits each, and processes them according to a predetermined control signal. , a port switching circuit that switches outputs to the n output ports in units of 8 bits and disables the switching operation according to a predetermined external signal; and 8 bits each from each of the n output ports of the port switching. n delay circuits that give a predetermined delay to the lower 7 bits of each of the output 8-bit data; and a delay circuit for the most significant 8-bit data of the 8×n-bit output of the port switching circuit. 7 to be output
One selection circuit that takes bit data as one input, takes 7-bit data output from the delay circuit for the lowest 8-bit data as the other input, and selects and outputs either one according to the predetermined external signal. Among the 8×n bits of output from the port switching circuit, the 7-bit data output from the delay circuit for the other 8-bit data is used as one input, and the upper 7-bit data of each is used as the other input, n-1 selection circuits that selectively output one of them in response to the predetermined external signal, and 7-bit data output from each selection circuit as the upper side and the corresponding 8-bit data as the lower side. Taking in n pieces of 15-bit data, establishing 8-bit synchronization for each, outputting it as 8×n-bit parallel output data, and outputting the predetermined control signal indicating the time order of establishing the synchronization.n When operating as an 8×n bit synchronous circuit, the port switching circuit is enabled by the external signal,
When the configuration is such that the input data of the other of the selection circuits is selectively output, and the data is operated as n independent 8-bit synchronous circuits, the port switching circuit is disabled by the external signal, and the input data of one of the selection circuits is disabled. A byte synchronization circuit characterized in that it is configured to selectively output input data.