JPH04117674A - Waveform conversion circuit for read information signal - Google Patents

Abstract

PURPOSE:To execute normal binarization immediately after the end of abnormality even when the abnormality is generated by converting a read information signal to a digital signal and suppressing the fluctuation of a threshold value within a prescribed range by inverting the digital signal for every prescribed time when the change of the digital signal is longer than the prescribed time. CONSTITUTION:An RF signal from a player is supplied to one input terminal of a comparator 1, the threshold value is supplied to the other input terminal, the input RF signal is digitized, turned to the output of the comparator 1 and supplied to an edge detection circuit 3, and the change of the digital signal is detected. Corresponding to the detection, a reset signal is supplied from the edge detection circuit 3 to an inversion command circuit 4. When the change of the digital signal is longer than the prescribed time, the fluctuation of the threshold value is suppressed within the prescribed range by inverting the digital signal for every prescribed time so as to execute proper signal conversion. Thus, even when any abnormality is generated in the read information signal, normal binarization can be executed immediately after the end of the abnormality.

Description

Detailed Description: TECHNICAL FIELD The present invention relates to a waveform conversion circuit for a read information signal obtained in a performance device of a recording medium carrying an information signal.

BACKGROUND ART A CD that obtains information signals by playing a disc on which information signals such as audio signals and video signals are recorded as digital non-signals.
Recording medium performance devices (hereinafter simply referred to as players) such as players and LDD players are widely known.

By the way, at the time of recording, an information signal is converted into a recording signal, but this conversion needs to be performed so as to satisfy the following conditions.

(2) The maximum inversion interval of the recording signal is set to be finite in order to enable clock extraction during playback.

(2) During playback, the recording signal should not contain DC components in order to prevent effects on servo systems such as focus and tracking and to remove low-frequency noise components.

During playback, the recorded signal recorded in this way is read by a pickup, and the read information signal obtained by amplification, that is, the RF multiplied signal, is converted into a binary (1, 0) digital signal by a waveform conversion circuit including a comparator. Convert to

In this comparator, a threshold voltage (hereinafter simply referred to as a threshold) is provided, and the level of the read information signal is compared with this to perform binarization. Incidentally, there may be an RF multiplied signal offset, that is, a DC component, and therefore it is necessary to automatically adjust this threshold value in accordance with the offset.

A conventional waveform conversion circuit will be explained with reference to FIG. The RF multiplied signal supplied to one input of the comparator 1 is compared with the threshold supplied to the other input, and is converted into a digital signal and output. The output digital signal is
Next-stage signal processing circuit (not shown) and DC component detection circuit 2
A threshold value corresponding to the detected DC component is output and supplied to the comparator 1. The DC component detection circuit 2 is constituted by a low-pass filter, and its time constant is set to a value sufficiently larger than the above-mentioned maximum inversion interval.

However, when RF double signal dropout occurs,
The output of comparator 1 may continue to be 1 (or 0) for a long time. Then, the DC component detection circuit 2 supplied with this output erroneously detects this as a DC component, resulting in an abnormal increase (or decrease) in the threshold value. In FIG. 7(a), the comparator output in FIG. 7(b) becomes 1 for a long time due to dropout caused by the RF multiplied signal. Therefore, the threshold value changes as shown in FIG. 7(a), and normal conversion is not performed. Therefore, the seventh
As shown in Figure (C), there is a problem in that an error signal is generated from the start of dropout, and the error signal continues for a while even after dropout ends.

SUMMARY OF THE INVENTION [Object of the Invention] Therefore, an object of the present invention is to provide a waveform conversion circuit that performs normal binarization immediately after the abnormality ends even if an abnormality such as a dropout occurs in a read information signal. It's about doing.

[Structure of the invention]

The waveform conversion circuit of the first invention of the present application includes a comparison means for comparing the information signal obtained by playing a recording medium carrying the information signal with a determined maximum inversion interval with a threshold value and outputting a binary digital signal. , a waveform conversion circuit comprising: DC component detection means for detecting a DC component in the digital signal and setting the threshold according to the detected DC component,
edge detection means that detects edges of the digital signal and outputs a reset signal each time; and outputs an inversion command signal that starts counting clock signals in response to the reset signal and changes at a constant cycle when a predetermined count value is reached. and a relay means that inverts the digital signal while receiving the inversion command signal and relays the digital signal to the DC component detection means.

The waveform conversion circuit of the second invention of the present application includes a comparison means for comparing the information signal obtained by playing a recording medium carrying an information signal with a determined maximum inversion interval with a threshold value and outputting a binary digital signal. , a waveform conversion circuit comprising: DC component detection means for detecting a DC component in the digital signal and setting the threshold according to the detected DC component,
The threshold value set by the DC component detection means is relayed to the comparison means, and when a dropout occurrence signal is received, the threshold value at that time is held, and when the dropout occurrence signal ends, the holding is performed. The configuration consists of relay means for canceling.

[Action of the invention]

The waveform conversion circuit of the first invention of the present application inverts the digital signal at predetermined intervals when the change in the digital signal is longer than a predetermined time when converting a read information signal obtained from a recording medium into a digital signal. In this way, the variation of the threshold value is suppressed within a predetermined range, and appropriate signal conversion is performed.

When converting a read information signal obtained from a recording medium into a digital signal, the waveform conversion circuit of the second invention of the present application receives a dropout occurrence signal and converts the read information signal to a digital signal when a dropout occurs in the read information signal. The threshold value is held, and the holding is released when the dropout occurrence signal ends.

In this way, even if dropout occurs, appropriate signal conversion to a digital signal is performed.

Embodiments Hereinafter, embodiments of the first invention of the present application will be described in detail based on the drawings.

In FIG. 1, an RF multiplied signal from a player is supplied to one input terminal of a comparator 1, a threshold value is supplied to the other input terminal, and the input RF signal is digitized and becomes the output of the comparator 1.

The output of the comparator 1 is supplied to an edge detection circuit 3 to detect changes in the digital signal. In response to this detection, a reset signal is supplied from the edge detection circuit 3 to the inversion command circuit 4. A clock signal is also supplied to the inversion command circuit 4, and counting is started using the reset signal as a trigger. When the count value reaches a predetermined count value, the logic "1°" is output as the inversion command signal.

This inversion command signal is issued at every predetermined count value unless a reset signal is supplied, and is supplied to the relay circuit 5. On the other hand, the digital signal is also supplied to the relay circuit 5, and is supplied to the DC component detection circuit 2 while being inverted while the inversion command signal is present. In the DC component detection circuit 2, the threshold value which is the output is increased or decreased depending on the supplied input of 1 or O.

A specific example of the circuit shown in FIG. 1 is shown in FIG. The edge detection circuit 3 is constituted by an EXOR gate, a resistor, and a capacitor, and applies reset signal pulses to the clear terminal of the inversion command circuit 4 at the rising and falling edges of the supplied digital signal.

The counter circuit 4 has a clock enable terminal.
This is a binary counter, and when the player is playing, the clock enable is 1, and if a reset signal is not given, the output Qo is inverted every time eight input clock signals are counted. If a reset signal is given during counting operation, counting will be stopped. In the case of this embodiment, since the pulse width of the reset signal is sufficiently shorter than the period of the clock signal, counting is started again from the clock signal immediately after the end of the reset signal.

This situation is shown in FIGS. 3(a) to 3(e).

Here, let us assume that the maximum inversion interval of the recording signal is 4 times the clock signal.
When the RF multiplication signal is normal, the output of the comparator 1 is inverted within the maximum inversion interval, a reset signal is given to the inversion command circuit 4 for each inversion, and the clock count value does not exceed 4. However, when a dropout occurs, the output of the comparator is not inverted during that period, and counts from OH to FH as shown in FIG. 3(d), and the output Qo is inverted every time 8 is counted.

Here, the output Qo is inverted every time 8 is counted because the circuit can be easily implemented, but the output Qo is inverted every time a predetermined number greater than 4 and other than 8 is counted. You can do it like this.

The relay circuit 5 is composed of one EXOR gate.

Its two inputs are the comparator output shown in FIG. 3(b) and the counter output Q shown in FIG. 3(e).

As shown in FIG. 5(f), the output of the relay circuit 5 is inverted every predetermined count value (8 counts) during the dropout period and is supplied to the DC component detection circuit 2.

The DC component detection circuit 2 includes an inverter, an operational amplifier, a resistor, and a low-pass filter consisting of a capacitor. The output of the DC component detection circuit 2, that is, the threshold value is shown in FIG.
As shown in g), when the input is 1, it increases, and when the input is 0, it decreases. Therefore, by appropriately selecting the time constant of the low-pass filter, the fluctuation of the threshold value can be set within a certain range.

Figure 3 (g) shows an enlarged view of the fluctuation of the threshold value.
When expressed on a scale equivalent to that in FIG. 7(a) to C), it becomes as shown in FIG. 4(a) to C). As shown in (a) of the figure, the threshold value hardly changes during the dropout period, and as shown in (b) and (c) of the figure, the error signal disappears as soon as the dropout ends.

Furthermore, since the variation range of the threshold value can be made small, the time constant of the low-pass filter of the DC component detection circuit 2 can be made small. As a result, although it is not as severe as dropout, the response to DC component fluctuations caused by dirt on the disk or the like becomes faster.

When the player is not playing, or is not playing normally even in play mode, the comparator output is stuck at 0 or 1 for a very long period of time, or the duty ratio of the counter output Qo is not exactly 50%. In this case, the threshold value gradually shifts and becomes stuck to the power supply or ground. In such a case, even if the correct RF multiplied signal is input, the threshold value will not return to the correct value again.

To prevent this, when the player is not operating normally, the tarot enable of the counter 4 is set to 0 to stop counting.

FIG. 5 is a configuration diagram of an embodiment of the second invention of the present application. In the figure, a threshold value hold circuit 5 is provided as a relay means between the DC component detection circuit 2 and the comparator 1, and when a dropout occurs, the threshold value at that time is held and a fixed threshold value is supplied to the comparator 1. , convert it into a digital signal.

At the end of dropout, the hold is released and the normal fluctuation threshold is set. Therefore, the threshold becomes independent of and unaffected by dropout.

In this case, the edge detection circuit 3 and the inversion command circuit 4 are used to detect dropout, as in the embodiment of the first invention of the present application.
or other dropout detection means.

As described in detail of the invention, in the waveform conversion circuit according to the first invention of the present application, when converting a read information signal obtained from a recording medium into a digital signal, if the change in the digital signal is longer than a predetermined time, , the digital signal is inverted at predetermined intervals to suppress fluctuations in the threshold value within a predetermined range, and even if an abnormality occurs in the read information signal such as a dropout, normal binarization is performed immediately after the abnormality ends. It is.

Furthermore, since the fluctuation range of the threshold value can be reduced, the time constant of the DC component detection means can be reduced, resulting in faster response to DC component fluctuations caused by dirt on the disk, etc., and less errors. It is possible.

Furthermore, in the above embodiment, since drop-at detection and reversal command generation are realized by one counter, the circuit is extremely simple. Furthermore, since all circuits other than the DC component detection circuit are constructed of digital circuits, it is suitable for IC implementation.

When converting a read information signal obtained from a recording medium into a digital signal, the waveform conversion circuit of the second invention of the present application receives a dropout occurrence signal and converts the read information signal to a digital signal when a dropout occurs in the read information signal. It is possible to maintain the threshold value and eliminate the influence of dropout on the threshold value. Thereafter, when the dropout occurrence signal ends, the hold is released, and normal binarization is performed immediately after the dropout ends.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the invention according to the first embodiment of the present application, Figure 2 is the circuit diagram of Figure 1, Figures 3 (a) to (g) are operational waveform diagrams of Figure 2, and Figure 4 is the circuit diagram of Figure 1. FIG. 3 is a diagram of operation waveforms with different time axes, FIG. 5 is a block diagram of an embodiment of the second invention of the present application, and FIG.
The figure is a block diagram of a conventional example, and FIG. 7 is an operation waveform diagram of FIG. 6. Explanation of symbols of main parts 1... Comparator 2... DC component detection circuit 3... Edge detection circuit 4... Inversion command circuit 5...・Relay circuit

Claims (2)

[Claims] (1) Compare the information signal obtained by playing a recording medium that carries an information signal with a determined maximum reversal interval with a threshold value.
A waveform conversion circuit comprising a comparison means for outputting a digital signal of a value, and a DC component detection means for detecting a DC component in the digital signal and setting the threshold value according to the detected DC component, the waveform conversion circuit comprising: edge detection means that detects edges of a digital signal and outputs a reset signal each time; and an inversion command signal that changes at a constant cycle when the time interval from one reset signal to the next reset signal exceeds a predetermined time. and a relay means that inverts the digital signal while receiving the inversion command signal and relays the digital signal to the DC component detection means. . (2) Compare the information signal obtained by playing a recording medium that carries an information signal with a determined maximum reversal interval with a threshold value;
A waveform conversion circuit comprising a comparison means for outputting a digital signal of a value, and a DC component detection means for detecting a DC component in the digital signal and setting the threshold value according to the detected DC component, the waveform conversion circuit comprising: The threshold value set by the DC component detection means is relayed to the comparison means, and when a dropout occurrence signal is received, the threshold value at that time is held, and the holding is released when the dropout occurrence signal ends. 1. A waveform conversion circuit comprising a relay means for