JPH04117675A - Waveform conversion circuit for read information signal - Google Patents

Abstract

PURPOSE:To execute normal binarization immediately even when any abnormality is generated by detecting the edge of a digital signal and inverting the digital signal by an inversion command signal changing in a fixed cycle and having a duty ratio higher than 50% when the time interval of an edge signal exceeds prescribed time. CONSTITUTION:An RF signal is supplied to one input of a comparator 1. As the output, a digital signal 14 is supplied to an edge detection circuit 3 and a repeater circuit 5 and in the edge detection circuit 3, the edge signal is outputted and supplied to an inversion command circuit 4 corresponding to the rise and fall edges of the digital signal. When the time interval from the first edge signal to the next edge signal exceeds the prescribed time, the inversion command circuit 4 outputs the inversion command signal changing in the fixed cycle and having the duty ratio higher than 50%, detects a direct current component while inverting the digital signal and executes binarization by setting a threshold value corresponding to the direct current component. Thus, even when any abnormality is generated in a read signal, normal binarization is executed immediately after the end of the abnormality.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a waveform conversion circuit for a read information signal obtained in a performance device for a recording medium that carries information signals.

Background Art A CD that obtains information signals by playing a disc on which information signals such as audio signals and video signals are recorded as digital signals.
Recording medium performance devices (hereinafter simply referred to as players) such as players and LDD players are widely known.

By the way, at the time of recording, an information signal is converted into a recording signal, but this conversion needs to be performed so as to satisfy the following conditions.

(1) In order to enable clock extraction during reproduction, the maximum inversion interval of the recording signal is set to be finite.

(2) During reproduction, the recording signal is made free of DC components in order to prevent effects on servo systems such as focusing and tracking and to remove low frequency noise components.

During playback, the recorded signal recorded in this way is read by a pickup, the read information signal obtained by amplification, that is, the RF multiplied signal, is AC coupled, and then converted into a binary value (1, 1, 0)
into a digital signal.

In this comparator, a threshold voltage (hereinafter simply referred to as a threshold) is provided, and the level of the read information signal is compared with this to perform binarization. As mentioned above, since the original information signal does not contain a DC component, it is necessary to fill-pack the DC component and automatically adjust the threshold so that the DC component of the comparator output becomes O. .

A conventional waveform conversion circuit will be explained with reference to FIG. A.C.
Via the coupling 6, the RF multiplied signal supplied to one input of the comparator 1 is compared with the threshold supplied to the other input, converted into a digital signal, and output. The output digital signal is supplied to a next-stage signal processing circuit (not shown) and a DC component detection circuit 2, and a threshold value corresponding to the detected DC component is output and supplied to a comparator 1. The DC component detection circuit 2 is constituted by a low-pass filter or the like, and its time constant is set to a value sufficiently larger than the above-mentioned maximum inversion interval.

However, as shown in FIG. 9(a), when the RF multiplied signal dropout occurs, if the dropout period is long with respect to the time constant of the AC coupling 6, the dropout as shown in FIG. 9(b) occurs.
As shown in the figure, the output of comparator 1 continues to be 0 for a long time. Then, the DC component detection circuit 2 supplied with this output erroneously detects this as a DC component, so that the threshold value is abnormally lowered as shown in FIG. Therefore, as shown in FIG. 9(C), an error signal is generated from the start of dropout, and the error signal continues for a while even after dropout ends.

SUMMARY OF THE INVENTION [Object of the Invention] Therefore, an object of the present invention is to provide a waveform conversion circuit that can perform normal binarization immediately after the abnormality ends even if an abnormality such as a dropout occurs in a read signal. It's about doing.

[Structure of the invention]

The waveform conversion circuit according to the first invention of the present application includes a comparison means for comparing the information signal obtained by playing a recording medium carrying an information signal with a determined maximum inversion interval with a threshold value and outputting a binary digital signal. , a waveform conversion circuit comprising: 8 means for detecting a DC component in the digital signal and setting the threshold value according to the detected DC component; edge detection means that outputs an edge signal each time; and when the time interval from one edge signal to the next edge signal exceeds a predetermined time, the edge detection means changes at a constant cycle and the duty ratio is 50%.
The inversion command means outputs the above reversal command signal, and the relay means inverts the digital signal while receiving the reversal command signal and relays the digital signal to the DC component detection means. There is.

The waveform conversion circuit according to the second invention of the present application includes a comparison means for comparing the information signal obtained by playing a recording medium carrying the information signal with a determined maximum inversion interval with a threshold value and outputting a binary digital signal. , a waveform conversion circuit having a DC component detecting means for detecting a DC component in the digital signal and setting the threshold value according to the detected DC component, the waveform converting circuit comprising: detecting an edge of the digital signal and converting it each time; an edge detection means that outputs an edge signal; and when the time interval from one edge signal to the next edge signal exceeds a predetermined time, the edge detection means changes at a constant cycle and has a duty ratio of 50%.
Reversal command means for outputting the above reversal command signal; dropout detection means for detecting dropout of the digital signal; and correction signal generation means for generating a correction signal according to the duration of the dropout when the dropout is completed. means, during the dropout period, the digital signal is inverted by the inversion command signal, and the digital signal is relayed to the DC component detection means, and during the correction signal generation period, the DC current is generated in the opposite direction to that during the dropout detection period. It has a configuration consisting of relay means for outputting a signal that causes a DC component to the DC component detection means.

The waveform conversion circuit according to the third invention of the present application includes a comparison means for comparing the information signal obtained by playing a recording medium carrying an information signal with a determined maximum inversion interval with a threshold value and outputting a binary digital signal. , a waveform conversion circuit having a DC component detecting means for detecting a DC component in the digital signal and setting the threshold value according to the detected DC component, the waveform converting circuit comprising: detecting an edge of the digital signal and converting it each time; an edge detection means for outputting an edge signal; an inversion command means for outputting an inversion command signal that changes at a constant cycle when the time interval from one edge signal to the next edge signal exceeds a predetermined time; dropout detection means for detecting a dropout of the signal; correction signal generation means for generating a correction signal according to the duration of the dropout when the dropout ends; and relay means for relaying the digital signal to the DC component detection means while inverting the signal, and is configured to reduce the time constant of the DC component detection means during the correction signal generation period.

[Action of the invention]

In the waveform conversion circuit according to the first aspect of the present invention, an information signal obtained by playing a recording medium carrying an information signal with a determined maximum inversion interval is compared with a threshold value to output a binary digital signal. When an edge of this digital signal is detected and the time interval from one edge signal to the next edge signal exceeds a predetermined time, an inversion command signal that changes at a constant cycle and has a duty ratio of 50% or more is sent to A DC component is detected while inverting the digital signal, and a threshold is set according to the detected DC component to perform binarization.

In the waveform conversion circuit according to the second aspect of the present invention, an information signal obtained by playing a recording medium carrying an information signal with a determined maximum inversion interval is compared with a threshold value to output a binary digital signal. By detecting the edges of this digital signal,
When the time interval from one edge signal to the next edge signal exceeds a predetermined time, an inverted command signal that changes at a constant cycle and has a duty ratio of 5096 or more is output. Further, dropout of the digital signal is detected and a dropout signal is generated. When this dropout ends, a correction signal is generated depending on the duration of the dropout. The relay means given these inversion command signals, dropout signals, and correction signals inverts the digital signal according to the inversion command signal during the dropout period and relays it to the DC component detection means, and during the correction signal generation period, the relay means outputs the dropout signal. A signal that produces a DC component in the opposite direction to that during the detection period is relayed to the DC component detection means. The DC component detection means sets a threshold value according to the DC component in the relayed signal and performs binarization.

In the waveform conversion circuit according to the third invention of the present application, an information signal obtained by playing a recording medium carrying an information signal with a determined maximum inversion interval is compared with a threshold value to output a binary digital signal. The edges of this digital signal are detected, and when the time interval from one edge signal to the next edge signal exceeds a predetermined time, an inversion command signal that changes at a constant cycle is output. Further, dropout of the digital signal is detected and a dropout signal is generated.

When this dropout ends, a correction signal is generated depending on the duration of the dropout. The relay means, which has been given this inversion command signal, inverts the digital signal and relays it to the DC component detection means.

The DC component detection means decreases its time constant during the period in which it receives the correction signal, sets a threshold value according to the DC component in the relayed digital signal, and performs binarization.

Embodiments Hereinafter, embodiments of the first invention of the present application will be described in detail based on the drawings.

FIG. 1 shows the configuration of an embodiment of the first invention of the present application. In the figure, the RF multiplied signal is supplied to one input of a comparator 1 via an AC coupling 6.

The digital signal output from the comparator 1 is supplied to an edge detection circuit 3, a relay circuit 5, and a next-stage signal processing circuit (not shown). In the edge detection circuit 3, an edge signal is outputted according to the rising and falling edges of the supplied digital signal and is supplied to the inversion command circuit 4. The inversion command circuit 4 is composed of an OR gate 4a and a loadable counter (presettable counter) 4b, and is loaded with a preset value as an initial value by an edge signal or a carry signal from the counter 4b itself. This preset value may be a fixed value or a value that changes depending on the digital signal output (dotted line).

In the counter 4b, a reference clock signal supplied separately is counted, and at a predetermined count value, an inverted command signal of 1 or O is outputted and supplied to the relay circuit 5. Note that the preset value is set so that the duty ratio of 1 and O is 50% or more. In the relay circuit 5,
The supplied digital signal is inverted by the inversion command signal and supplied to the DC component detection circuit 2. In the DC component detection circuit, the threshold value which is the output is increased or decreased depending on the supplied input of 1 or 0.

A specific example of the circuit shown in FIG. 1 is shown in FIG. Since the digital signal output from the comparator 1 is inverted within the maximum inversion interval, the edge signal from the edge detection circuit is also synchronized with the inversion. The counter 4b is a hexadecimal binary counter, and the load value is currently set to 4. counter 4
The inversion command signal from the output QO of b rises at count value 8 and falls at 16. Here, if the maximum inversion interval is four cycles of the clock, the count value will never reach 8 or more. That is, since the edge interval at which the reversal command signal rises is set longer than the maximum reversal interval, that is, the maximum interval of edge signals, the reversal command signal will not be output unless dropout occurs.

As shown in FIG. 3(a), when a dropout occurs in the negative direction of the RF multiplied signal, the output of the comparator 1 remains at 0 for that period and does not change as shown in FIG. 3(b). Therefore, during that period, the edge signal is not output, and the inversion command signal from Qo becomes 1 when the count value is 8, as shown in (d) of the same figure.
The count value becomes 16 and becomes O. Since a carried signal is output at count value 16, preset value 4 is loaded via OR gate 4a and counting is performed again.

As a result, an inverted command signal with a duty ratio of 66% is supplied to the relay circuit 5 as shown in the figure. The relay circuit 5 is EXO
It is a simple circuit with only one R gate, and its output is shown in the same figure (
As shown in e), it is the exclusive OR of the comparator output and the counter output.

The output of this relay circuit 5 is an inverter, an operational amplifier,
The signal is supplied to a DC component detection circuit 2, which is a low-pass filter consisting of a resistor and a capacitor. The output of the DC component detection circuit 2, that is, the threshold value, gradually increases during the dropout period, as shown in FIG. 2(f). Although the figure shows the variation of the threshold value in an enlarged manner, if it is expressed on a scale equivalent to that in FIGS. 9(a) to C), it becomes as shown in FIGS. 4(a) to C). As is clear from the figure (a), the threshold value also follows the RF multiplied signal level fluctuation after the end of dropout, and is correctly converted into a digital signal as shown in the figure (b). Therefore, the error signal disappears as soon as the dropout ends, as shown in FIG. 4(C).

Although this embodiment has described dropout in the negative direction, the result is the same in the positive direction as well, although the polarity is reversed. Further, the value of the duty ratio is determined based on the dropout amplitude, the AC coupling time constant, and the gain and time constant of the DC component detection circuit so that it becomes a threshold value after the dropout ends or an appropriate value.

If there are various dropout amplitudes, an amplitude limiter may be placed before the AC coupling 6 shown in FIGS. 1 and 2 in order to keep the amplitudes substantially constant. This is No. 2 of this application. The same applies to the third invention.

Also, if the dropout amplitude differs between positive and negative,
As shown by the dotted line in FIG. 1, the duty ratio may be changed depending on the sign of the dropout to adapt the amount of change in the threshold value to the positive or negative amplitude. For example, if the amplitude of a positive dropout is smaller than that of a negative one, if the preset part of Figure 2 is changed to the one shown in Figure 10, the load value of counter 4b will be 3 when there is a positive dropout. , 3, 4 when dropout occurs. ...8,9...15. 3.
Since counting is performed as 4..., the duty ratio of the inversion command signal is approximately 61.5%, and the threshold value can be changed with a gentler slope than in the case of negative dropout. This is also No. 2 of the present application. The same applies to the third invention.

5 to 7 show an embodiment of the second invention of the present application. In the first invention of the present application, if the time constant of the low-pass filter of the DC component detection circuit 2 is considerably larger than the time constant of the AC coupling 6, it takes time for the threshold value to return to its original value after dropout. Until then, no elaborate digital conversion can be performed. Therefore, at the end of dropout, the DC component detection circuit 2 sends a correction pulse that changes the threshold in the opposite direction to that during the dropout period.
Enter. FIG. 5 is a configuration diagram thereof, and the comparator 1, DC component detection circuit 2, edge detection circuit 3, and AC coupling 6 are the same as those in FIG. 1. 6 shows a specific example of the circuit shown in FIG. 5, and FIGS. 7(a) to 7(e) show operating waveforms of this circuit.

The reversal command circuit 4 includes a load control circuit 4C in addition to a counter 4b similar to that shown in FIG. Furthermore, a dropout detection circuit 7 and a correction pulse generation circuit 8 are added to FIG. Accordingly, the relay circuit also connects the D flip-flop 5.
A and selector 5b circuits are added. Therefore, here, the inversion command circuit 4, the dropout detection circuit 7,
The correction pulse generation circuit 8 and the relay circuit 5 will be explained with reference to the drawings.

The edge signal from the edge detection circuit 3 is supplied to a load control circuit 4c and a dropout detection circuit 7. 7th
When a dropout occurs as shown in Figure (a), a preset value is loaded as an initial value in the dropout detection circuit 7 by an edge signal. This preset value is larger than the preset value of the counter 4b, and if the next edge signal is not supplied within the maximum inversion interval, the Qo of the counter 4b becomes 1, but before that, the output QO of the dropout detection circuit 7 becomes 1. (in this case 5)
) has been done. In this way, even when the next edge signal is supplied with the maximum inversion interval, the Q of the dropout detection circuit 7 will be
o becomes 1, but Qo of the counter 4b does not become 1, so the inversion command signal and correction pulse are not generated and normal operation continues. Further, Qo of the dropout detection circuit 7 becomes O at the edge signal at the end of dropout. In this way, from the Qo of the dropout detection circuit 7, as shown in FIG.
A dropout detection signal as shown in is output.

The carry Co of the up/down counter of the correction pulse generating circuit 8 becomes 1 at count values 15 and 0 during count up and count down, respectively. Since Go is connected to the enable CE via an inverter, when the count value reaches 15 when counting up and the count value O when counting down, it enters a hold state and stops counting. When the dropout detection signal is 0, it is a countdown, so normally the count value stops at 0. When the dropout detection signal reaches 1, the count is up and the length of the dropout period is counted using the QD of the counter 4b as a clock. When the dropout period ends and the dropout detection signal becomes 0, the counter 4b similarly counts down using Q6 as a clock until the count value reaches 0. Here Co
By ANDing the respective inversions of and the dropout detection signal, a correction pulse having a length corresponding to the countdown period signal, that is, the dropout detection period is obtained. FIG. 7(C) shows the waveform of the correction pulse.

The digital signal is supplied to the relay circuit 5, but when no correction pulse is applied, it is supplied from the A side of the selector 5b to one input of the EXOR gate. The dropout detection signal is supplied to the clock terminal of the D flip-flop 5a, the digital signal in the dropout period is latched, and an inverted digital signal of opposite polarity is supplied to the B side of the selector 5b. Correction pulse is selector 5
When applied to b, the connection is switched from the A side to the B side and this inverted digital signal is fed to the EXOR gate.

By doing this, when the dropout detection signal is 1 and when the correction pulse is 1, the inverted control signal (the Q of the counter 4b) has the same duty ratio.

output) or input to the EXOR gate.
The duty ratios of the outputs of the gates are reversed, and the threshold values change in opposite directions.

The load control circuit 4c controls the counter 4 during the correction pulse period.
It receives only a predetermined count value from counter 4b, otherwise receives an edge signal or a predetermined count value, generates a load signal and a preset value, respectively, and loads the preset value into the counter 4b. Therefore, from the output Qo of the counter 4b, an inversion command signal with a predetermined duty ratio is applied to the other input of the EXOR gate 5c of the relay circuit 5 during the dropout period and the correction pulse period, respectively.

The load control circuit is realized by a gate circuit made of various gates or PLA. For example, when the counter 4b operates as follows, a gate circuit that realizes the following theoretical formula may be used.

However, L is a load signal, A, B, C, D are 4 bits representing preset values (D is MSB), QA, Qs, Qc,
Qo is the output of the counter 4b (Qo is MSB), P is a digital signal, E is an edge signal, and CP is a correction pulse.

L -E -CP+ Qs-Qc-Qo (CP +
QA ) D -0 Qc-CP conflict P Qc = CP + p QA-CP-P + CP -P From the EXOR gate 5c, the above-mentioned digital signal or inverted digital signal is output while being inverted by the inversion command signal, and as shown in FIG. A waveform as shown in d) is supplied to the DC component detection circuit 2. Therefore, the output of the DC component detection circuit 2 as shown in FIG. 7(e), that is, the threshold value, is supplied to the comparator 1, and proper digital conversion is immediately performed after the dropout is completed.

In this example, the dropout period and the correction pulse period are set to have approximately the same length, but they do not necessarily have to be the same as long as proper digital conversion is performed. Also,
Although the inversion command signal was used as the clock for the up-down counter, other clocks may be used since the up-down counter simply measures time.

Next, the third invention of the present application will be explained. FIG. 11 shows an embodiment of the present invention, in which a comparator 1, an edge detection circuit 3
, reversal command circuit 4, relay circuit 5 and AC coupling 6
is the same as in FIG. 1, and the dropout detection circuit 7 and correction pulse generation circuit 8 are the same as in FIG. 5, respectively. The DC component detection circuit 2 has an analog switch and a resistor added compared to those in FIGS. 2 and 6, and the analog switch turns ON when the correction pulse reaches 1, and changes the time constant during the correction pulse period. Make it smaller. Therefore, the threshold value quickly converges to an appropriate value during the correction pulse period, and the conversion to a digital signal can be performed correctly immediately after the end of dropout.

Here, the inversion command circuit 4 is the same as in FIG. 1, but the duty ratio of the inversion command signal does not necessarily have to be 5096 or more. That is, the present invention can be applied even when the duty ratio of the inversion command signal is 50% and the threshold value is kept substantially constant during the dropout period.

This application No. 1. In the second and third inventions, when the player is not operating normally, for example when the player is not playing or when a very long dropout occurs due to track skipping, the edge signal is not detected for a long period of time. Sometimes. If the reversal command circuit 4 is always operating at this time, the rise or fall of the threshold value will become too large and R
No F-fold signal waveform conversion is performed at all. In this case, it becomes impossible to detect the edge signal, and even if the correct RF multiplied signal is input again, the threshold value will not return to the proper value.

The enable terminals shown in FIGS. 2, 6, and 11 are terminals to prevent such situations, and stop the operation of the counter of the reversal command circuit 4 when the player is not operating normally. to prevent excessive rise or fall of the threshold. Furthermore, instead of using the enable terminal, a limiter may be inserted between the DC component detection circuit 2 and the comparator 1 to limit the range of change in the threshold value. Note that even when the duty ratio of the inversion command signal is 50%, the DC component does not become completely O, so the threshold value shifts over a long period of time, so similar measures are required.

As described in detail of the invention, the waveform conversion circuit according to the first invention of the present application compares an information signal obtained by playing a recording medium carrying an information signal with a predetermined maximum inversion interval with a threshold value, and converts the information signal into a binary value. Outputs a digital signal.

When an edge of this digital signal is detected and the time interval from one edge signal to the next edge signal exceeds a predetermined time, an inversion command signal that changes at a constant cycle and has a duty ratio of 50% or more is sent to The DC component is detected while inverting the digital signal, and a threshold value is set according to the DC component. Even if an abnormality such as a dropout occurs in the read signal, the normal 2nd current signal is immediately restored after the abnormality ends.
It is possible to convert it into a value.

In the waveform conversion circuit according to the second invention of the present application, an information signal obtained by playing a recording medium carrying an information signal with a determined maximum inversion interval is compared with a threshold value, and a binary digital signal is output. Detects the edge of this digital signal and outputs an inverted command signal that changes at a constant cycle and has a duty ratio of 50% or more when the time interval from edge signal 1 to the next edge signal exceeds a predetermined time. do. Further, dropout of the digital signal is detected and a dropout signal is generated. When this dropout ends, a correction signal corresponding to the duration of the dropout is generated. The relay means given the inversion command signal, dropout signal and ← correction signal inverts the digital signal according to the inversion command signal during the dropout period and relays it to the DC component detection means, and during the correction signal generation period, the relay means A signal that generates a DC component in the opposite direction to that during the out detection period is relayed to the DC component detection means. The DC component detection means sets a threshold value according to the DC component in the relayed signal, and even if an abnormality such as a dropout occurs in the read signal, the normal binary value is immediately detected after the abnormality ends. It is possible to make changes.

The waveform conversion circuit according to the third invention of the present application compares an information signal obtained by playing a recording medium carrying an information signal with a determined maximum inversion interval with a threshold value, and outputs a binary digital signal. The edge of this digital signal is detected, and when the time interval from one edge signal to the next edge signal exceeds a predetermined time, an inversion command signal that changes at a constant cycle is output. Further, dropout of the digital signal is detected and a dropout signal is generated. When this dropout ends, a correction signal is generated depending on the duration of the dropout. The relay means, which has been given this inversion command signal, inverts the digital signal and relays it to the DC component detection means. The DC component detection means decreases its time constant during the period in which it receives the correction signal, so that the threshold value quickly converges to the appropriate value, and even if an abnormality such as a dropout occurs in the read signal, after the abnormality ends. Normal binarization can be performed immediately.

Furthermore, in the embodiment of the first invention of the present application, dropout detection and reversal command generation are realized by one counter, so the circuit is extremely simple. In addition, Section 1 of this application. The embodiments of the second and third inventions are all constructed of digital circuits except for the DC component detection circuit, and are therefore suitable for IC implementation.

[Brief Description of the Drawings] Figure 1 is a block diagram showing an embodiment of the first invention of the present application, Figure 2 is a specific circuit diagram of Figure 1, and Figures 3 and 4 are the operations of Figure 2. Waveform diagram, FIG. 5 is a block diagram of the embodiment of the second invention of the present application, FIG. 6 is a specific circuit diagram of FIG. 5, FIG. 7 is an operation waveform diagram of FIG. 6, and FIG. 8 is a conventional diagram. Example block diagram,
9 is an operation waveform diagram of FIG. 8, FIG. 10 is a circuit diagram of the portion shown in FIG. 2 in another embodiment of the first to third inventions of the present application, and FIG. 11 is an implementation of the third invention of the present application. FIG. 2 is an example block diagram. Explanation of symbols of main parts 1... Comparator 2... DC component detection circuit 3... Edge detection circuit 4... Inversion command circuit 5... Relay circuit 6... AC coupling 7... Dropout detection circuit 8...
Correction pulse generation circuit

Claims (5)

[Claims] (1) Compare the information signal obtained by playing a recording medium that carries an information signal with a determined maximum reversal interval with a threshold value.
A waveform conversion circuit comprising a comparison means for outputting a digital signal of a value, and a DC component detection means for detecting a DC component in the digital signal and setting the threshold value according to the detected DC component, the waveform conversion circuit comprising: edge detection means for detecting an edge of a digital signal and outputting an edge signal each time;
reversal command means for outputting a reversal command signal that changes at a constant cycle and has a duty ratio of 50% or more when the time interval from 1 to the next edge signal exceeds a predetermined time, and while receiving the reversal command signal; A waveform conversion circuit for a read information signal, comprising a relay means for inverting the digital signal and relaying the digital signal to the DC component detection means. (2) Compare the information signal obtained by playing a recording medium that carries an information signal with a determined maximum reversal interval with a threshold value;
A waveform conversion circuit comprising a comparison means for outputting a digital signal of a value, and a DC component detection means for detecting a DC component in the digital signal and setting the threshold value according to the detected DC component, the waveform conversion circuit comprising: edge detection means for detecting an edge of a digital signal and outputting an edge signal each time;
an inversion command means for outputting an inversion command signal that changes at a constant cycle and has a duty ratio of 50% or more when a time interval from 1 to the next edge signal exceeds a predetermined time, and detects dropout of the digital signal. dropout detection means; correction signal generation means for generating a correction signal according to the duration of the dropout when the dropout ends; and during the dropout period, the digital signal is inverted by the inversion command signal and relay means for relaying the digital signal to the minute detection means and outputting a signal to the DC component detection means such that during the correction signal generation period, a DC component is generated in the opposite direction to that during the dropout detection period. A waveform conversion circuit for the read information signal. (3) Claim 2 characterized in that the magnitude of the DC component in the opposite direction differs depending on the polarity of the digital signal.
A waveform conversion circuit for the read information signal described above. (4) Compare the information signal obtained by playing a recording medium that carries an information signal with a determined maximum reversal interval with a threshold value;
A waveform conversion circuit comprising a comparison means for outputting a digital signal of a value, and a DC component detection means for detecting a DC component in the digital signal and setting the threshold value according to the detected DC component, the waveform conversion circuit comprising: edge detection means for detecting an edge of a digital signal and outputting an edge signal each time;
reversal command means for outputting a reversal command signal that changes at a constant cycle when the time interval from 1 to the next edge signal exceeds a predetermined time; dropout detection means for detecting dropout of the digital signal; correction signal generating means for generating a correction signal according to the duration of the dropout when the dropout ends, and relaying the digital signal to the DC component detection means while inverting the digital signal while receiving the inversion command signal. 1. A waveform conversion circuit for a read information signal, characterized in that the time constant of the DC component detection means is reduced during a correction signal generation period. (5) The read information signal waveform conversion circuit according to claim 1, wherein the duty ratio of the inversion command signal differs depending on the polarity of the digital signal.