KR100585055B1 - Defect Detection Device and Method of Optical System - Google Patents

Abstract

Disclosed are a defect detection apparatus and method for an optical system. The defect detecting apparatus of the optical system according to the present invention includes a defect amplifying means for inverting and amplifying a high frequency signal applied from an optical pickup by a predetermined multiple, and a bottom hold for following a bottom of the amplified high frequency signal and outputting a defect peak envelope signal. A multiplexer which inputs a circuit, a defect peak envelope signal and predetermined error signals, selects and outputs a defect peak envelope signal in response to a predetermined selection signal, and outputs a defect peak envelope signal output from the multiplexer N (> 0). A digital signal processor core for generating an analog / digital conversion means for converting into a digital signal of bits and a selection signal and generating a defect detection signal using an N-bit digital signal, a filtered signal of the digital signal, and a direct current offset. Characterized in having a.

Description

Defect Detection Device and Method of Optical System

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to optical systems such as Compact Disc Players (CDPs), Digital Versatile Disc Players (DVDPs), and the like, and more particularly, to detect defects using digital signal processing methods. It relates to a defect detection apparatus and method for an optical system.

Generally, in optical systems such as CD players, DVDPs, and DVD ROMs, defect components on discs such as scratches, fingerprints, or interruptions can greatly reduce the stability of the system because they transform servo error signals such as focus error signals or tracking error signals. Will be affected. Therefore, by detecting the section having the defect component and holding the servo during the section, the effect due to the defect component is minimized.

FIG. 1 is a circuit diagram illustrating a defect detection apparatus of a conventional optical system, and includes a defect amplifier 100, a first bottom hold circuit 110, a second bottom hold circuit 150, and an offset setting unit 170. ) And the defect comparator 190, wherein the first bottom hold circuit 110 includes a diode D11, a capacitor C11, a current source I11, and an emitter follower 112. The second bottom hold circuit 150 includes a diode D12, a resistor R12, a capacitor C12, a resistor R14, and an emitter follower 152, and the offset setting unit 170 includes a capacitor C170. ), Resistor R17 and voltage source V2.

2 (a) to 2 (d) are waveform diagrams for explaining each signal of the conventional defect detection apparatus shown in FIG. 1, and 2 (a) shows a high frequency signal RF0 applied from an optical pickup. 2 (b) shows the high frequency signal amplified by the defect amplifier 100, and FIG. 2 (c) shows the first bottom hold circuit 110 and the second bottom hold circuit 150 of FIG. 2 (d) represents the defect detection signal DEFECT output from the defect comparator 190.

The defect amplifier 100 shown in FIG. 1 inputs the high frequency signal RF0 shown in FIG. 2 (a) applied from the optical pickup, and inverts and amplifies twice to generate the signal shown in 2 (b). . The amplified high frequency signal is applied to the first bottom hold circuit 110 and the second bottom hold circuit 150, respectively, and bottom hold the high frequency signal. Here, the time constants are differently set by the capacitors C11 and C12 of the first bottom hold circuit 110 and the second bottom hold circuit 150. That is, the short time constant of the bottom hold signal is obtained for the disk mirror defect of 0.1 mm sec or more, and the long time constant is obtained for the mirror level longer than the defect. The outputs of the first and second bottom hold circuits 110 and 150 are input to the offset setting unit 170, and DC offsets are set by the capacitor C17, the resistor R17, and the voltage source V2, respectively. It is applied through the positive input terminal and the negative input terminal of the defect comparator 190. The first bottom hold signal 22 applied through the positive input terminal and the second bottom hold signal 24 applied through the negative input terminal are shown in FIG. The defect comparator 190 compares the signals applied through the respective input terminals, and outputs the result of the comparison as a defect detection signal DEFECT shown in FIG. That is, a pulse having a high level is generated in a section in which the first bottom hold signal 22 is larger than the second bottom hold signal 24, and continues to maintain a low level in other sections. The defect detection signal DEFECT output from the defect comparator 19 is applied to the focus or tracking servo.

That is, the conventional defect detection apparatus takes up a large part of the overall chip size because all of the defect detection apparatuses are implemented as analog circuits. In addition, since the capacitors C12 and C17 have large capacities of approximately 0.01 uF and 0.33 uF, the capacitors C12 and C17 cannot be implemented inside the IC, and two capacitors are provided outside the IC. Therefore, there is a problem that an additional pin for connecting the IC and an external device is required.

It is an object of the present invention to provide a defect detection apparatus of an optical system that detects a defect in a digital manner using a digital signal processor.

Another object of the present invention is to provide a defect detection method performed in the defect detection apparatus.

In order to achieve the above object, the defect detection apparatus of the optical system according to the present invention is a defect amplification means for inverting and amplifying a high frequency signal applied from an optical pickup by a predetermined multiple, and a defect peak envelope following the bottom of the amplified high frequency signal. Bottom hold circuit that outputs a signal, a defect peak envelope signal and a predetermined peak error signal, and a multiplexer that selects and outputs a defect peak envelope signal in response to a predetermined selection signal, and a defect peak envelope output from the multiplexer An analog / digital conversion means for converting the signal into an N (> 0) bit digital signal, and a selection signal, and generating a defect detection signal using the N bit digital signal, the filtered signal of the digital signal, and a direct current offset. It is preferably composed of digital signal processor cores to generate.

In order to achieve the above another object, the defect detection method according to the present invention comprises the steps of: generating a bottom-holded defect peak envelope signal in response to a selection signal applied from a digital signal processor core; Converting the signal into a second signal, storing the converted value as a first signal, low-pass filtering the first signal, and storing the difference between the filtered signal and the DC offset as a second signal, is the second signal greater than the first signal? Determining (a) if the first signal is greater than the second signal, determining that it is not a defect section, (b) setting the defect detection signal to a first level if it is not a defect section, (c) if the first signal is less than or equal to the second signal, determining that it is a defect section, (d) determining whether to detect a defect in the defect section, and if it is desired to detect the defect, detection It is preferable to set the signal to the second level, and (e) setting the defect detection signal to the first level so as not to detect the defect in the defect section.

Hereinafter, a defect detection apparatus for an optical system according to the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a circuit diagram of a preferred embodiment for explaining a defect detection apparatus of an optical system according to the present invention, which includes a defect amplifier 300, a bottom hold circuit 310, a multiplexer 320, and an analog / digital converter. 330 and a DSP (Digital Signal Processor) core 350, where the bottom hold circuit 310 comprises a diode D31, a capacitor C31, a current source I31 and an emitter follower 315. It consists of.

The defect amplifier 300 shown in FIG. 3 applies the high frequency signal RF0 output from the optical pickup to the negative input terminal and inputs the voltage V1 to the positive input terminal as a high frequency signal inverted and amplified twice. Output The amplified signal detects an envelope signal by following only the bottom in the bottom hold circuit 310, and outputs the detected signal as a defect peak envelope signal DPKENV. That is, the amplified high frequency signal applied to the bottom hold circuit 310 is differentiated by the coupled capacitor C31, amplified by a predetermined gain in the emitter follower 315, level shifted, and the defect peak envelope. It is output as a signal DPKENV. The bottom held defect peak envelope signal DPKENV is applied to one of the inputs of the multiplexer 320. That is, the multiplexer 320 is implemented as an 8x1 multiplexer, but may be implemented in other ways. In addition to the defect peak envelope signal DPKENV, the multiplexer 320 may have a servo error signal such as a focus error signal (PE) and a tracking error signal (TE) and a half value of a power supply voltage. Signals processed by the DSP such as the reference signal VREF are applied to the inputs I1 to I8. The analog / digital converter 330 converts the analog peak peak envelope signal DPKENV output from the bottom hold circuit 310 into a digital signal. That is, the multiplexer 320 selects the defect peak envelope DPKENV output from the bottom hold circuit 310 in response to the selection signal SEL output from the DSP core 350, and the analog / digital converter 330. ) Converts the selected signal into a digital signal and outputs it to make a signal form that can be processed by the digital signal processor (DSP). In addition, the DSP core 350 detects a defect by inputting a defect peak envelope signal converted into a digital signal and performing a predetermined algorithm for defect detection therein using a preset DC offset. Therefore, it is detected whether a component of the input signal is a defect, generates a defect detection signal DFCT, and outputs the generated signal through the output terminal OUT. The defect detection signal DFCT generated inside the DSP core 350 is not only output to the outside and applied to the servo, but also used for other processing therein.

Here, the multiplexer 320, analog / digital converter 330, and DSP core 350 shown in FIG. 3 are circuits used in digital servo, and are used to process servo error signals such as focus and tracking. Defect processing is performed by allocating an extra time that does not process the servo error signal. That is, the DSP core 350 periodically processes the tracking or focus error signals input to the multiplexer 320 by applying a selection signal SEL implemented with different bits to the multiplexer 320 or decodes them at an extra time. Effect detection can be performed. Referring to FIG. 3, the digital value output from the analog / digital converter 330 is implemented with 9 bits, but may be implemented with N (> 0) bits, and the selection signal SEL output from the DSP core 350. It is possible to implement the data of M (> 0) bits rather than 3 bits.

FIG. 4 is a flowchart for explaining a detection method performed by the defect detection apparatus shown in FIG. 3. The defect peak envelope signal is selected according to a selection signal applied from a DSP core, and the selected signal is digitally converted. Storing as the first signal S1, and storing the difference between the low-pass filtered signal of the first signal S1 and the DC offset as the second signal S2 (steps 410 to 420) and the first signal S1. Generating a defect detection signal by comparing the second signal S2 with the second signal S2 and determining whether or not the defect period is determined according to the result of the comparison, and setting the detected defect signal to the first level or the second level. Step 425 ~ 455).

FIG. 5 is a flowchart of a preferred embodiment for explaining the defect detection signal generation steps (steps 425 to 455) of the defect detection method shown in FIG. 4, wherein the first signal S1 is the second signal S2. If larger than), it is determined that the defect is not in the defect interval, and the defect flag signal is set to 0, and then the defect detection signal is set to 0 (steps 510 to 529), and the first signal S1 is the second signal. If it is smaller than or equal to (S2), it is determined as a defect section, and the current level of the defect section is determined to generate a defect detection signal having a first level or a second level depending on whether or not the defect is detected. Steps 530 through 590 are performed.

6 (a) to 6 (e) are waveform diagrams for explaining respective signals of the defect detection apparatus shown in FIG.

Referring to FIG. 6, 6 (a) represents a high frequency signal RF0 to be applied, 6 (b) represents a high frequency signal amplified by the defect amplifier 300, and 6 (c) is illustrated in FIG. 3. Indicates the defect peak envelope signal DPKENV output from the bottom hold circuit 310, 6 (d) indicates the defect flag signal DFCTflag generated by the DSP core 350, and 6 (e) indicates the DSP. The defect detection signal DFCT generated in the core 350 is shown. Here, reference numeral 62 denotes the second delay time delayH, and reference numeral 64 denotes the first delay time delayL.

Hereinafter, the operation and detection method of the defect detection apparatus according to the present invention will be described in detail.

First, the high frequency signal RF0 shown in FIG. 6 (a) input to the defect amplifier 300 is inverted and amplified twice by the defect amplifier 300 to be amplified as shown in FIG. 6 (b). As a generated signal. The double inverted-amplified defect signal follows the bottom only in the bottom hold circuit 310 and is output as an analog defect peak envelope signal DPKENV shown in Fig. 6C. In the DSP core 350, if the defect detection is to be performed, the select signal SEL implemented with N bits, preferably 3 bits, corresponding to the defect signal is applied to the multiplexer 320 so that the select signal SEL causes the bottom hold circuit ( The defect peak envelope signal DPKENV output from 310 is selected. Accordingly, the multiplexer 320 selects and outputs a defect peak envelope signal DPKENV among the applied signals in response to the selection signal SEL (operation 410). This signal is applied to the analog / digital converter 330, and the digital converter 330 converts the applied analog defect peak envelope signal DPKENV as an N-bit digital signal. At this time, the digitally transformed defect peak envelope signal is stored as the first signal S1 (step 415). The digital signal S1 is filtered by a low pass filter in the DSP core 350 and stores a value obtained by subtracting the DC offset from the filtered signal as the second signal S2 (step 420). Here, the digital filter implemented in the DSP core 350 is preferably implemented as an infinite impulse response filter (IIR), and is processed in a digital manner rather than an analog manner. In addition, since the DC offset is also set to a digital value in advance, the value can be easily changed as necessary. At this time, the digitally-converted first signal S1 is compared with a value obtained by subtracting the first signal S1 and subtracting the DC offset, that is, the second signal S2 which is a difference between the filtered signal and the DC offset. If it is determined whether the second signal S2 is greater than the first signal S1 (step 425), and if the second signal S2 is larger, it is determined that the defect is not a defect (step 430). . Therefore, in order to perform the processing in the case of non-defect, the defect detection signal DFCT is set to a first level, that is, 0 through a predetermined process to be described in detail below (step 435). That is, the defect detection signal DFCT is set to have a zero value in the non-defective section. If the first signal S1 is less than or equal to the second signal S2 in step 425, it is determined as a defect (step 440). Therefore, in operation 440, it is determined whether the defect is to be detected (operation 445), and the defect detection signal DFCT is set to a second level, that is, only when the defect detection is to be performed (operation 455). ). That is, in order to not detect defects, the detected defect signal is set to a first level, that is, 0 even in the defect period (step 450).

First, with reference to the embodiment shown in Figure 5 will be described in more detail with respect to the process in the case of non-defect, that is, steps 430 to 435. That is, if it is determined in step 510 that it is not the defect period, it is determined whether the defect flag signal signal DFCTflag shown in FIG. 6 (d) is 1 or 0 (step 520). Here, the defect flag signal DFCTflag is a signal indicating a section in which the defect is started and does not include the extension time of the defect process. If the defect flag signal DFCTflag is 1, it indicates that the first time is entered into a routine for processing a process that is not a defect, and thus a first delay is performed in the count buffer cnt in the DSP core 350. The time delayL is stored (operation 522), and the defect flag signal DFCTflag and the defect detection determination signal DFCTenb are set to zero. Here, the first delay time delayL represents an extension time of the defect processing after the completion of the defect, and even if the defect is actually terminated, there is a certain time delay until the high frequency signal RF0 recovers normally. Denotes a first delay time delayL. Here, if the defect flag signal DFCTflag and the defect detection determination signal DFCTenb are set to 0, the counting value cnt stored in the counter buffer is decreased (step 526), and it is determined whether the value is zero. Determination (step 528). Therefore, when the counting value cnt becomes 0, the defect detection signal DFCT shown in 6 (e) is set to 0 and ends (step 529). Similarly, if the defect flag signal signal DFCTFLAG is 0 in step 520, the counting value is decreased from the time point (step 526). If the counting value cnt is 0, the defect detection signal DEFT is zero. (Steps 528 to 529).

If it is determined in step 510 that the current defect section is present, it is determined whether the current defect detection signal DFCT is 1 or 0 (step 530). Here, the defect detection signal DFCT is a signal representing a section including a predetermined time for stabilization of the high frequency signal after the completion of the defect. If the current defect detection signal DFCT is 0, the routine enters a routine consisting of steps 540 to 570 to set the detected defect signal to 1. In this case, it is determined whether or not the defect is to be detected even in the section determined as the defect, and it may be determined whether the defect detection determination signal DFCTenb is 0 or 1 (step 540). Here, the defect is detected when the defect detection determination signal DFCTenb is 0. When the defect detection determination signal DFCTenb is 1, the defect detection is not desired and the operation is terminated at the current routine.

At this time, if the defect detection determination signal DFCTenb is 0, it is determined whether the defect flag signal DFCTflag is 1 (step 550). At this time, if the defect flag signal DFCTflag is 0, it indicates that the detection routine has entered the detection routine for the first time after it is determined to be the defect period. Thus, the second delay time delayH is stored in the count value cnt of the counter buffer. The defect flag signal DFCTflag is set to 1 (step 555). Here, the second delay time (delayH) represents an extension time for the defect processing when the defect starts, this section is a section for outputting a distorted high frequency signal, not a normal high frequency signal, although the high frequency signal has not disappeared Indicates. Accordingly, the counting value cnt of the counting buffer is decreased (step 560), and it is determined whether the reduced value becomes 0 (step 565). In addition, if the defect flag signal DFCTflag is 1 in operation 550, the counting value cnt is decreased based on the current time point, and it is determined whether the reduced value becomes 0 (operation 565). Therefore, if the counting value cnt is 0, the defect detection signal DFCT is set to 1, and the defect detection maximum time DFCTmax is stored in the counting value cnt (step 570). This defect detection maximum time (DFCTmax) is a time limit for preventing malfunction of the system due to continuous defects when defects occur continuously. Therefore, it is necessary to store a preset value in the counter buffer.

On the other hand, steps 580 to 590 are routines for setting the maximum time for the defect processing when the defect detection signal DFCT is already set to 1 during the defect period and counting value based on the current time point ( cnt) is reduced (step 580), and it is determined whether the reduced counting value cnt becomes 0 (step 585). Therefore, when the counting value cnt becomes 0, the defect detection is no longer performed. Therefore, the defect detection determination signal DFCTenb is set to 1, and the defect detection signal DFCT is set to 0 (590). step). As described above, when the defect detection determination signal DFCTenb is set to 1, the defect detection signal DFCT is not set to 1 even if it is determined to be a defect section.

As described above, the defect can be detected by analog-to-digital conversion of the bottom-held signal of the applied high frequency signal (RFO) by digital processing in the DSP, and the multiplexer 320 and analog shown in FIG. The digital converter 330 and the DSP core 350 time-process and process the blocks used to process the focus and tracking errors in the digital servo, so that no additional hardware is required.

According to the present invention, by replacing a part of a conventional defect detection device composed of an analog circuit with some circuits of a digital servo, not only the size of the entire circuit can be reduced, but also external elements such as a conventional capacitor can be digitally circuitd. Replacing internally has the effect of reducing the number of pins and external components of the circuit. In addition, by processing the low pass filter and the DC offset digitally, the value can be easily changed by the microcomputer command as necessary.

1 is a circuit diagram for explaining a defect detection apparatus of a conventional optical system.

2 (a) to 2 (d) are waveform diagrams for explaining respective signals of the defect detection apparatus shown in FIG.

3 is a circuit diagram of a preferred embodiment for explaining the defect detection apparatus of the optical system according to the present invention.

FIG. 4 is a flowchart for explaining a defect detection method performed in the apparatus shown in FIG. 3.

FIG. 5 is a flowchart of a preferred embodiment for explaining a defect detection signal generation step of the defect detection method shown in FIG. 4.

6 (a) to 6 (e) are waveform diagrams for explaining respective signals of the defect detection apparatus shown in FIG.

Claims (6)

Defect amplifying means for inverting and amplifying a high frequency signal applied from the optical pickup by a predetermined multiple; A bottom hold circuit that follows a bottom of the amplified high frequency signal and outputs a defect peak envelope signal; A multiplexer which inputs the defect peak envelope signal and predetermined error signals, and selects and outputs the defect peak envelope signal in response to a predetermined selection signal; Analog / digital conversion means for converting the defect peak envelope signal output from the multiplexer into a digital signal of N (> 0) bits; And A digital signal processor core for generating the selection signal and generating a defect detection signal using the N-bit digital signal, the filtered signal of the digital signal, and a direct current offset. Detection device. The method of claim 1, wherein the bottom hold circuit, A diode coupled to the cathode and the high frequency signal amplified by the predetermined multiple; A capacitor connected between the anode of the diode and a reference power supply; A current source coupled between a power supply voltage and an anode of said diode; And And an emitter follower having a positive input terminal connected to an anode of the diode and an output terminal and a negative input terminal connected to the anode of the diode. 3. The defect detection of an optical system according to claim 2, wherein the digital signal processor core detects the defect by allocating an extra time other than the time used to process the tracking error signal or the focus error signal. Device. Generating a bottom held defect peak envelope signal in response to the selection signal applied by the digital signal processor core; Converting the defect peak envelope signal into a digital signal and storing the converted value as a first signal; Low pass filtering the first signal and storing the difference between the filtered signal and the DC offset as a second signal; Determining whether the second signal is greater than the first signal; (a) determining that the first signal is not a defect section when the first signal is greater than the second signal; (b) setting a defect detection signal to a first level if the defect period is not present; (c) if the first signal is less than or equal to the second signal, determining that it is a defect period; (d) determining whether to detect the defect in the defect period, and if the defect is to be detected, setting the defect detection signal to a second level; And and (e) setting the defect detection signal to the first level so as not to detect the defect in the defect period. The method of claim 4, wherein the steps (a) to (b), Determining whether the defect flag signal is zero; (f) decreasing the counting value when the defect flag signal is 0 and setting the defect detection signal to 0 when the counting value is 0; If the defect flag signal is not zero, storing a first delay time in a counter buffer; And And setting the defect flag signal and the defect detection determination signal to 0 and returning to step (f). The method of claim 5, wherein (c) to (e), (g) determining whether the defect detection signal is 1; If the defect detection signal is 1, decreasing a counting value; If the counting value is 0, setting the defect detection determination signal to 1 and setting the defect detection signal to zero; (h) determining whether the defect detection determination signal is 0 when the defect detection signal is not 1 in step (g), and ending when the defect detection determination signal is not 0; Determining whether the defect flag signal is 1 when the defect detection determination signal is 0 in step (g); Reducing the counting value when the defect flag signal is 1 and setting the defect detection signal to 1 when the counting value is 0 and storing the maximum number of defect detection times in the counter buffer; (i) if the defect flag signal is not 1, storing a second delay time in the counter buffer and setting the defect flag signal to 1; And Reducing the counting value of the counter buffer after step (i) and setting the defect detection signal to 1 after the counting value is 0, and storing the defect detection maximum time in the counter buffer. The defect detection method characterized by the above-mentioned.