JPH0411766A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a malfunction due to a junction leakage by forming one diffusion layer of high and low impurity concentration layers and the other of a low impurity concentration layer. CONSTITUTION:A gate insulating film 3 is formed on the surface of an active region surrounded by a field insulating film 2, and word lines WL1, WL2 are formed of a polyside layer in which a high melting point metal silicide film is superposed on a polycrystalline Si film doped with an impurity. Here, a sidewall spacer 4 is made of SiO2, diffused layers 5, 6 are formed in a self- alignment manner to the line WL1 in a p-type Si substrate 1, the layer 5 has an n<-> type low impurity concentration part 5a at the lower side of the spacer 4, and the other part is an n<+> type. The layer 6 is formed of low and high impurity concentration layers, and a MOS transistor is formed of the line WL1 and the layers 5, 6. Then, a malfunction due to a junction leakage can be prevented while improving hot carrier resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and is particularly suitable for application to a semiconductor memory having a one-transistor/l-capacitor type memory cell.

[Summary of the invention]

The present invention provides a semiconductor memory having a memory cell composed of one MIS transistor and one capacitor, in which the source region or drain Ml! of the MIS transistor is provided. By configuring one of the diffusion layers constituting i with a high impurity concentration layer and a low impurity concentration layer, and the other with a low impurity concentration layer, it is possible to improve hot carrier resistance and reduce defects due to junction leakage. This is designed to prevent this from occurring.

[Conventional technology]

In the recent highly integrated MOS dynamic RAM,
(2) A transistor/capacitor type memory cell is used. And MO3I- which constitutes this memory cell
In order to improve hot carrier resistance, the transistor is made of LDD (lightly d).

It is common to have a ped/drain structure.

Figure 6 shows the MOS transistors constituting the memory cell.
A conventional stacked capacitor cell (st
(acked capacitor cell) type MOS
Dynamic RAM is shown. As shown in FIG. 6, in this conventional MOS dynamic RAM, a field insulating film 102 is selectively formed on the surface of, for example, a p-type silicon (St 2 ) substrate 101. Gate insulating film 1 on the surface of the active region
03 is formed. WL,', WL,'' indicate word lines. Sidewall spacers 104 are formed on the side walls of these word lines WL,'', WL*'. On the other hand, in the p-type St substrate 101, word lines WL,
For example, n-type diffusion layers 105° and 106 are formed in a self-aligned manner with respect to ”.These diffusion layers 105° and 10
6, n-type low impurity concentration portions 105a and 106a are formed below the sidewall spacer 104, for example. A MOS transistor with an LDD structure is formed by the word 1iWL,'' and these diffusion layers 105 and 106.

Reference numeral 107 indicates an interlayer insulating film, 108 indicates a polycrystalline Si film doped with an impurity such as phosphorus (P), 109 indicates an insulating film, and 110 indicates a polycrystalline Si film doped with an impurity such as P. . Here, the polycrystal 5i) 1108 is in contact with the diffusion layer 106 through the contact hole C1'. A stacked capacitor is formed by these polycrystalline Si film 108, insulating film 109, and polycrystalline Si film 110. Here, polycrystalline 5ill10
8 and polycrystalline Si film 110 respectively constitute a lower electrode (charge storage node) and an upper electrode (cell plate) of this stacked capacitor. Further, reference numeral 111 indicates an insulating film between the eyebrows, and BL' indicates a bit line. Here, this bit line BL' is connected to the diffusion layer 1 through the contact hole Cz'.
I have contacted 05.

The LDD structure MOS transistor of the conventional MOS dynamic RAM described above is formed as follows. That is, as shown in FIG. 6, the word lines WL,',
After forming up to WL,', these word lines WL,',
Using WL, ' as a mask, an n-type impurity such as P is ion-implanted into the P-type Si substrate 101 at a low concentration.
Next, after forming, for example, a SiO2 film on the entire surface by CVD, this SiO□ film is etched by reactive ion etching (RI).
E) Etching is performed in a direction perpendicular to the substrate surface to form sidewall spacers 104 on the side walls of word lines WL+' and WLz'. Next, using the sidewall spacers 104 and the word lines WL, , WLz' as masks, the p-type Si substrate 101 is filled with, for example, arsenic (As).
) is ion-implanted at a high concentration. After this, heat treatment is performed to electrically activate the implanted impurities.

As a result, diffusion layers 105 and 106 having low impurity concentration portions 105a and 106a are formed below the sidewall spacer 104, and an LDD structure MOS transistor is formed.

[Problem to be solved by the invention]

In the conventional MOS dynamic RAM manufacturing method described above, when forming an LDD structure MOS transistor, the sidewall spacer 104 is formed by etching the Sin film using the RIE method. However, since this RIE causes damage to the surface of the p-type Si substrate 1, the diffusion layer 105 formed in the subsequent process
．． 106 junction leak is likely to occur, and this is caused by MO
There was a risk that the S dynamink RAM would become defective.

This junction leakage is particularly caused by the diffusion layer 1 on the charge storage node side.
06 becomes a problem.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory which can prevent defects due to junction leakage while improving hot carrier resistance.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a semiconductor memory having a memory cell constituted by one MIS transistor and one capacitor. Alternatively, one of the diffusion layers (5, 6) constituting the drain region is composed of a high impurity concentration layer and a low impurity concentration layer, and the other is composed of a low impurity concentration layer.

[Effect]

According to the semiconductor memory of the present invention configured as described above, by using the diffusion layer (6) constituted by the low impurity concentration layer as the diffusion layer on the charge storage node side of the MIS transistor constituting the memory cell, There is no need to form a sidewall spacer on the sidewall of the gate electrode of this MIS transistor on the charge storage node side. Therefore, there is no possibility that the substrate surface on the charge storage node side will be damaged by RIE, so that it is possible to suppress the occurrence of junction leakage in the diffusion layer on the charge storage node side due to RIE. On the other hand, one of the diffusion layers constituting the source region or drain region of the MIS transistor constituting the memory cell is composed of a high impurity concentration layer and a low impurity concentration layer, and the other is composed of a low impurity concentration layer. Similar to the conventional LDD structure MIS transistor,
It is possible to improve hot carrier resistance.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This embodiment is an embodiment in which the present invention is applied to a stacked capacitor cell type MOS dynamic RAM.

FIG. 1 shows a MOS dynamic RAM according to this embodiment, and FIG. 2 shows a MOS dynamic RAM according to this embodiment.
An equivalent circuit of an AM memory cell is shown.

As shown in FIG. 1, in the MOS dynamic RAM according to this embodiment, a field insulating film 2 such as a SiO□ film is selectively formed on the surface of a p-type Si substrate 1, thereby providing isolation between elements. It is being done. On the surface of the active region surrounded by the field insulating film 2, 5i
A gate insulating film 3 such as an OT film is formed. WL
,,wt,z indicate word lines. These word lines WL
,,WL.

is polycrystalline Si doped with impurities such as P.
It can be formed by a polycide film or a polycide film in which a high melting point metal silicide film such as a tungsten silicide (WSiz) film is superimposed on a polycrystalline Si film doped with impurities. Reference numeral 4 indicates a sidewall spacer 4 made of, for example, a SiO□ film. On the other hand, p-type Si
A diffusion layer 5.6 is formed in the substrate 1 in a self-aligned manner with respect to the word line W L +. Here, the diffusion layer 5 has, for example, an n-type low impurity concentration portion 5a in a portion below the sidewall spacer 4, and the other portions are, for example, n-type. On the other hand, the diffusion layer 6 is, for example, n
- consists of a low impurity concentration layer. And word line WL
, and these diffusion layers 5 and 6, the MO of LDD structure
An S transistor is formed. In this case, the sidewall spacer 4 is formed only on the sidewall of the word line WL of the five diffusion layers.

Reference numeral 7 indicates an insulating film such as a SiO□ film, and 8 indicates a glabellar insulating film such as a phosphosilicate glass (PSC) film. Further, reference numeral 9 is a polycrystalline Si film doped with an impurity such as P, and 10 is an SiOg film and an S
O N O (
Oxide-Nitride-Oxide) film, S
N O (Ni
11 is a polycrystalline Si film doped with an impurity such as P, for example. Here, the polycrystalline Si film 9 is connected to the contact hole C3.
It is in contact with the diffusion layer 6 through. A stacked capacitor is formed by the polycrystalline film 19, the insulating film IO, and the polycrystalline Si film 11. here,
Polycrystalline Si film 9 and polycrystalline Si film 11 constitute a lower electrode (charge storage node) and a lower electrode (cell plate) of this stacked capacitor, respectively.

Further, reference numeral 12 is a glabella insulating film such as a PSG film, for example.
BL indicates the focus line. Here, this bit line BL is
It contacts the diffusion layer 5 through the contact hole C2.

Next, M O according to this embodiment configured as described above
A method for manufacturing the S dynamic RAM will be explained.

As shown in FIG. 3A, first, a field insulating film 2 is selectively formed on the surface of a p-type Si substrate 1 by a thermal oxidation method to perform isolation between elements. A gate insulating film 3 is formed on the surface of the active region by thermal oxidation. Next, a first layer of polycrystalline Si film is formed on the entire surface by CVD method, and this polycrystalline sit! After doping impurities such as P by thermal diffusion or ion implantation to lower the resistance, the polycrystalline Si film is patterned into a predetermined shape by etching to form word lines WL, , WL.
.

form. In addition, when forming these word lines WL, WL2 with a polycide film, after forming a high melting point metal silicide film on the above-mentioned impurity-doped polycrystalline Si film, these high melting point metal silicide films and In the 0th order for patterning the polycrystalline Si film, the word line WL
, , WL as a mask, for example, P is placed in the p-type Si substrate 1.
N-type impurities such as are ion-implanted at a low concentration. As a result, for example, the n-type diffusion layers 6 and 13 are connected to the word line WL.
Next, an insulating film 7 such as a Sin film is formed on the entire surface by the CVD method, which is formed in a self-aligned manner with respect to I. Thereafter, a resist pattern 14 having a predetermined shape is formed on this insulating film 7 by lithography.

Next, RIE is performed using this resist pattern 14 as a mask.
The insulating film 7 is etched in a direction perpendicular to the substrate surface by a method. As a result, as shown in FIG. 3B, the diffusion layer 13
Sidewall spacers 4 are formed only on the sidewalls of word lines WL in the example.

Next, after removing the resist pattern 14, an n-type impurity such as As is ion-implanted into the p-type Si substrate 1 at a high concentration using the sidewall spacers 4 and the word lines WL, . . . WL2 as masks. After this, heat treatment is performed to electrically activate the implanted impurities. As a result, as shown in FIG.
An n-type diffusion layer 5 is formed in the lower portion of the wafer.

Next, as shown in FIG. 1, after forming an interlayer insulating film 1I18 on the entire surface by CVD, predetermined portions of the interlayer insulating film 8, the insulating film 7, and the gate insulating film 3 are removed by etching to form a contact hole C1. Form. Next, a second layer of polycrystalline Si film 9 is formed on the entire surface by CVD method, and this polycrystalline Si film 9 is doped with an impurity such as P by thermal diffusion method or ion implantation method to lower the resistance. After this, the polycrystalline Si film 9 is patterned into the shape of the lower electrode by etching. Next, an upper insulating film 10 is formed on this second layer of polycrystalline Si film.

Next, a third layer of polycrystalline Si film 1 is deposited on the entire surface using the CVD method.
1 is formed, and this polycrystalline Si film 11 is doped with an impurity such as P by thermal diffusion or ion implantation to lower its resistance, and then the polycrystalline Si film 11 is etched to form an upper electrode. pattern.

Next, after a glabellar insulating film 12 such as a PsG film is formed on the entire surface by CVD, predetermined portions of the interlayer insulating film 12 and the interlayer insulating film 8 are etched away to form a contact hole C2. Next, after forming, for example, an aluminum (AI) film on the entire surface by, for example, sputtering, this ^1 film is patterned into a predetermined shape by etching to form a bit line BL. Thereafter, a passive basis film (not shown) is formed to complete the intended MOS dynamic RAM.

As described above, according to this embodiment, the sidewall spacer 4 is not formed on the sidewall of the word line WL, which constitutes the gate electrode of the MOS transistor constituting the memory cell, on the side of the charge storage node. There is no possibility that the RIE for forming the spacer 4 will damage the substrate surface on the charge storage node side. Therefore, junction leakage of the diffusion layer 6 on the side of the charge storage node can be effectively prevented. Furthermore, since one diffusion layer 5 of the MOS transistor constituting this memory cell has a low impurity concentration region 5a, and the other diffusion layer 6 is constituted by a low impurity concentration layer, the MO3 of the conventional LDD structure
Similar to the I-transistor, the hot carrier resistance can be improved.

By the way, as the insulating film 10 of the stacked capacitor in the above-mentioned MOS dynamic RAM, Si 3
NO (Nitrid) consisting of N4 film and SiO film.
It is considered preferable to use an e-Oxide film from the viewpoint of reliability. However, the polycrystalline Si that is the lower electrode
Even if you try to form this No film on the film, low pressure CVD
(LPCVD) method on the polycrystalline Si film 9.
When forming the Si3Nm film as the lower layer of the film, this Si3
As a result of oxygen entering the interface between the Na film and the polycrystalline Si film 9, a poor quality stogM film with a thickness of about 10 layers grows between the Si3N film and the polycrystalline Si film 9. It ends up. That is, in the conventional method for forming a No film, an ONO film is actually formed, and it is difficult to form a No film. Next, a method for forming a No film on a polycrystalline Si film will be described.

In the first method, the so-called RTN (rapidt
For example, Si3N, which has a thin film thickness of about a few layers, is deposited on a polycrystalline Si film by a herbal tridation method.
Forms a film instantly. Here, this RTN is performed, for example, by instantaneously heating the polycrystalline Si film 9 to a high temperature using a halogen lamp or the like in an ammonia (NH:I) gas atmosphere at room temperature. Since the Si3Nm film is instantaneously formed on the polycrystalline Si film in this way, this Six
There is no possibility that a 5ift film will be formed between the N 4 film and the polycrystalline Si film 9. S i formed by this RTN
As described above, the thickness of the 3Na film is small, on the order of several tens of layers, so 5i3N4IIl having a thickness of, for example, several tens of layers is formed on this 5i3Na film by the LPCVD method. Thereafter, a Si0g film is formed on this 5i3Na film by thermal oxidation. As a result, a No film is formed.

In the second method, first plasma enhanced CVD (
For example, 5isNaW1 having a film thickness of about 10 layers is formed on polycrystalline 5ille by a PECVD method or a photo-CVD method. According to this PECVD method and photoCVD method, 200°C
Since 5isNall can be formed at a low temperature of about 100% or lower, there is no possibility that a 5iO1 film of poor quality will be formed between this 5isNa film and the polycrystalline Si film 9. A 5ixNa film having a thickness of, for example, several tens of layers is formed on the Nm film. Thereafter, a Si0g film is formed on the Si, N, and No films to form a No film.

By the way, with the increasing integration of MOS dynamic RAM, the method of bit line contact and charge storage node contact of memory cells is SAC (self-aligned).
contact) has become mainstream. This SAC is normally used in both the memory cell section and the peripheral circuit section. On the other hand, when using this SAC, in order to increase the insulation strength between the lower wiring and the upper wiring, a thick SiO□ film for a spacer is formed on the lower wiring to increase the width of the sidewall spacer for the SAC. needs to be made larger. Therefore, this sidewall spacer for SAC is
When used as a sidewall spacer for forming a MOS transistor with a DD structure, the width of the sidewall spacer for the LDD structure becomes larger than necessary, which causes a problem of a reduction in the performance of the MOS transistor. was.

This problem can be solved by using SAC in the memory cell section and not using SAC in the peripheral circuit. The method will be explained with reference to FIGS. 4A to 4.

As shown in FIG. 4A, first, a field insulating film 22 is selectively formed on the surface of a P-type Si substrate 21 to perform device isolation, and then the surface of the active region surrounded by this Ryeld insulating film 22 is A gate insulating film 23 is formed thereon. Next, CVD
For example, a polycrystalline Si film 24 is formed as a material for forming a gate electrode on the entire surface by a method, and then this polycrystalline Si film 24 is
SiO□ film 2 for SAC spacer is deposited on top by CVD method.
After forming the 5ift film 5, a resist pattern 26 is formed on the 5ift film 25 in the memory cell portion.

Next, using this resist pattern 26 as a mask, SiO
□By etching the film 25, the 5iOz film 25 is left only in the memory cell area, as shown in FIG. 4B. Next, after removing the resist pattern 26, the resist pattern 27 for forming the gate electrode is removed. form.

Next, using this resist pattern 27 as a mask,
The g film 25 and the polycrystalline Si film 24 are etched in a direction perpendicular to the substrate surface by, for example, RIE.

As a result, as shown in FIG. 4C, the gate electrode 28
．． 29 is formed. In this case, on the gate electrode 28 of the memory cell portion, a Si having the same shape as the gate electrode 28 is formed.
There are 25 NG films and 5 films.

Next, after removing the resist pattern 27, an n-type impurity such as P is ion-implanted at a low concentration into the p-type St substrate 21 using the gate electrodes 28 and 29 as a mask. As a result, n-type diffusion layers 30 and 31 are formed in a self-aligned manner with respect to the gate electrode 28, and n-type diffusion layers 32 and 33 are formed in a self-aligned manner with respect to the gate electrode 29. It is formed. Thereafter, for example, a SiO□ film 34 is formed over the entire surface by CVD.

Next, this SiO□ film 34 is etched in a direction perpendicular to the substrate surface by RIE method. With this, the fourth
As shown in 11gD, the gate electrode 28 of the memory cell portion
A large-width sidewall spacer 35 is formed on the sidewall of the 5ift 825, and a small-width sidewall spacer 36 is formed on the sidewall of the gate electrode 29 in the peripheral circuit section. Next, these side wall spacers 3536, SiO□ film 25 and gate voltage ff12
For example, A is placed in the P-type Si substrate 21 using 8.29 as a mask.
N-type impurities such as s are ion-implanted at a high concentration. Thereafter, heat treatment is performed to electrically activate the implanted impurities, if necessary. With this, side wall spacer 3
For example, an n-type low impurity concentration region 37a is provided in the lower part of the
, 38a are formed in a self-aligned manner with respect to the gate electrode 28, and at the same time, for example, an
- type low impurity concentration portions 39a, 40a, for example
°-type diffusion layers 39 and 40 are formed in a self-aligned manner with respect to the gate electrode 29. The gate electrode 28 and the diffusion layers 37 and 38 form an LDD structure MOS in the memory cell section.
While the transistor is formed, the gate electrode 29 and the diffusion layers 39 and 40 form the M of the LDD structure in the peripheral circuit section.
An OS transistor is formed.

As described above, according to this example, the MOS in the peripheral circuit section
Since the width of the sidewall spacer 36 formed on the side wall of the gate electrode 29 of the transistor is small, it is possible to prevent the performance of the MOS transistor in this peripheral circuit portion from deteriorating. Furthermore, the width of the sidewall spacer 35 formed on the side wall of the gate electrode 28 of the MOS transistor in the memory cell section is wide (therefore, the performance of this MOS transistor is lowered, but the MOS transistor in this memory cell section is a switching element). to be used only as
The sidewall spacer 3
Deterioration in the performance of the MOS transistor due to the increase in the width of 5 does not pose a problem.

As described above, it is possible to improve the performance of the MOS dynamic RAM.

FIG. 7 shows a conventional semiconductor device using SAC.
As shown in the figure, in this semiconductor device, p-type Si
A gate insulating film 202 is formed on a substrate 201.

Reference numerals 203 and 204 indicate first layer wiring. A 5iOt film 205 for a SAC spacer is formed on these first layer wirings 203 and 204. Then, these first layer wirings 203, 204 and the 5iOz film 2
A side wall spacer 206 is formed on the side wall of 05. Reference numeral 207 indicates, for example, an n-type diffusion layer.

This diffusion layer 207 has, for example, an n-type low impurity concentration portion 207a below the sidewall spacer 206. Reference numeral 208 indicates, for example, an n-type diffusion layer constituting a low impurity concentration portion of the n-type diffusion layer (not shown).

C1' indicates a contact hole for SAC, and the second layer wiring 209 is in contact with the diffusion layer 207 through this contact hole C3'. Reference numeral 210 indicates an insulating film between the eyebrows. C1' indicates a contact hole, and the third layer wiring 211 contacts the first layer wiring 204 through this contact hole C4''.

As shown in FIG. 7, in this conventional semiconductor device using SAC, a thick SiO□ film 205 for the SAC spacer is left on the first layer wiring 204. The third layer wiring 211 is added to the third layer wiring 204.
The height difference at the contact hole C4' portion for contacting is 2 times steeper. As a result, the third layer wiring 2
11 is formed using AI or the like, the step coverage of the third layer wiring 211 in the contact hole C4' portion becomes poor and the third layer wiring 211
It is easy for the stage to break and there is a problem in terms of reliability. Therefore,
Next, a method for solving this problem will be explained with reference to FIGS. 5A to 5.

That is, in this example, as shown in FIG. 5A,
For example, on the p-type Si-based Fi 51, the gate insulating film 52 and the first
For example, polycrystalline Si#5 as a material for forming layer wiring.
3 and Sin for the SAC spacer.

After sequentially forming the films 54, a resist pattern 55 having a predetermined shape is formed on the Sing M2S 4.

Next, using this resist pattern 55 as a mask, SiO
□After etching the film 54, the resist pattern 55 is removed. As a result, as shown in FIG. 5B, the SA
The 5iCh film 54 is left only near the C portion. After this,
A resist pattern 56 for forming the first layer wiring is formed.

Next, using this resist pattern 56 as a mask, SiO
After etching the second film 54 and the polycrystalline Si film 53, the resist pattern 56 is removed. As a result, first layer wirings 57 and 58 are formed as shown in FIG. 5C. Next, using the first layer wirings 57 and 58 and the SiO□ film 54 left on these first layer wirings 57 and 58 as a mask, a film such as P is injected into the p-type Si substrate 51. N-type impurity ions are implanted at a low concentration. As a result, n-type diffusion layers 59 and 60, for example, are formed in a self-aligned manner with respect to the first layer arrangement 157 and 58. After that, for example, a Si○2 film 6 is applied to the entire surface using the CVD method.
1 film shape 1.

Next, this 5iO1 film 61 is etched in a direction perpendicular to the substrate surface by, for example, RIE. With this, the fifth
As shown in the figure, first layer wiring 57,58 and Si
A side wall spacer 62 is formed on the side wall of the O□M54. After this, this side wall spacer 62, S
Using the ing film 54 and the first layer wirings 57 and 58 as masks, n-type impurities such as As are ion-implanted into the p-type Si substrate 51 at a high concentration. After this, heat treatment is performed to electrically activate the implanted impurities. As a result, an n-type diffusion layer 6 having, for example, an n-type low impurity concentration portion 63a under the sidewall spacer 62 is formed.
3 are formed in self-alignment with the first layer wirings 57 and 58. Next, a second layer wiring 64 is formed to contact the diffusion layer 63 through the SAC contact hole C3. Next, a glabellar insulating film 65 is formed on the entire surface, and after reflowing the glabellar insulating film 65 to flatten the surface, a predetermined portion of the interlayer insulating film 65 is etched away to form a contact hole C4. Next, a third layer wiring 66 is formed to contact the first layer wiring 58 through this contact hole C4. As a result, the intended semiconductor device is completed.

As described above, according to this example, the portion of the SiO2 film 54 for the SAC spacer near the contact portion of the third layer wiring 66 with respect to the first layer wiring 58 is removed by etching in advance. Therefore, the level difference in the contact hole C4 portion for contacting the third layer wiring 66 with the first layer wiring 5 can be made gentler, and therefore, the step in the contact hole C4 portion for contacting the third layer wiring 66 with the first layer wiring 5th can be made gentler. 3
It is possible to prevent the occurrence of breakage in the wiring 66 of the layer. Thereby, the reliability of the semiconductor device can be improved.

The method according to this example can be applied to various semiconductor devices using SAC, such as MOS dynamic RAM, MOS static RAM, and EPROM.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the above-mentioned embodiment, the case where the present invention is applied to a stacked capacitor cell type MOS dynamic RAM was explained, but the present invention is applicable to a MOS using a one-transistor capacitor type memory cell other than a stacked capacitor cell. It is also possible to apply to dynamic RAM.

〔Effect of the invention〕

As explained above, according to the present invention, one of the diffusion layers constituting the source region or the drain region of the MIS transistor constituting the memory cell is composed of a high impurity concentration layer and a low impurity concentration layer, and the other is composed of a high impurity concentration layer and a low impurity concentration layer. Since it is composed of an impurity concentration layer, it is possible to effectively prevent junction leakage of the diffusion layer on the side of the charge storage tank node, and to improve the hot carrier resistance similarly to the conventional MIs transistor with the LDD structure. You can also do it. As a result, it is possible to prevent defects due to joint leakage while improving water resistance and wear resistance.

[Brief explanation of drawings]

FIG. 1 shows a MOS dynamic R according to an embodiment of the present invention.
FIG. 2 is a sectional view showing an AM according to an embodiment of the present invention.
A circuit diagram showing an equivalent circuit of a memory cell of an OS dynamic RAM, FIG. 3A to FIG. A to 4th diagrams are cross-sectional views for explaining step-by-step how to solve the problem of MOS dynamic RAM using SAC, and FIGS. 5A to 5th diagram are SA
FIG. 6 is a cross-sectional view showing a conventional MOS dynamic RAM, and FIG. 7 is a cross-sectional view explaining the problem of a semiconductor device using SAC. FIG. Explanation of main symbols in the drawings 1: p-type Si substrate, 2: field insulating film, 3: gate insulating film, WL+, WLz: word line, 4: side wall spacer, 5.6: diffusion layer, 7: insulating film , 9, 11: polycrystalline Si film, C6°C2: contact hole, BL: bit line.

Claims (1)

[Claims] In a semiconductor memory having a memory cell constituted by one MIS transistor and one capacitor, one of the diffusion layers constituting the source region or drain region of the MIS transistor is formed by forming a high impurity concentration layer. A semiconductor memory comprising a low impurity concentration layer and a low impurity concentration layer, the other comprising a low impurity concentration layer.