JPH04117446U - Semiconductor device measurement jig - Google Patents

Semiconductor device measurement jig

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Publication number
JPH04117446U
JPH04117446U JP127791U JP127791U JPH04117446U JP H04117446 U JPH04117446 U JP H04117446U JP 127791 U JP127791 U JP 127791U JP 127791 U JP127791 U JP 127791U JP H04117446 U JPH04117446 U JP H04117446U
Authority
JP
Japan
Prior art keywords
semiconductor element
strip
semiconductor device
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP127791U
Other languages
Japanese (ja)
Inventor
直子 小林
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP127791U priority Critical patent/JPH04117446U/en
Publication of JPH04117446U publication Critical patent/JPH04117446U/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

(57)【要約】 【構成】半導体素子の形にくり抜かれた溝a5を持つ素
子固定台a6と、中央に半導体素子の形の穴4が明いて
いる低損失誘電体の基板7と、基板7の上面に貼られた
GND板a8と、基板7の下面に取り付けられた2本の
ストリップ導体2と、ストリップ導体2上に設けられた
バンプ3とから構成され、2本のストリップ導体2と基
板7とGND板a8とで2本のストリップラインa1を
形成している。そして、半導体素子を素子固定台a6の
溝a5にはめ込み、GND板a8及びストリップ導体2
の取り付けられた基板7を半導体素子の上部から重ねて
バンプ3により半導体素子のピンを素子固定台a6に押
し付ける。 【効果】上記の構成により、半導体素子のピンに対して
なんら負荷を与えずにピンとストリップラインとを正確
に接触させることができ、また、ネジ止めの必要が無
く、半導体素子の着脱が容易に行え、さらに、使用時に
基板の穴により半導体素子を冷却することができる。
(57) [Summary] [Structure] An element fixing base a6 having a groove a5 cut out in the shape of a semiconductor element, a low-loss dielectric substrate 7 with a hole 4 in the shape of a semiconductor element in the center, and a substrate 7. It consists of a GND plate a8 pasted on the top surface of the board 7, two strip conductors 2 attached to the bottom surface of the board 7, and bumps 3 provided on the strip conductors 2. Two strip lines a1 are formed by the substrate 7 and the GND plate a8. Then, the semiconductor element is fitted into the groove a5 of the element fixing base a6, and the GND plate a8 and the strip conductor 2
The board 7 on which is attached is stacked on top of the semiconductor element, and the pins of the semiconductor element are pressed against the element fixing base a6 by the bumps 3. [Effect] With the above configuration, it is possible to accurately contact the pins of the semiconductor element with the strip line without applying any load to the pins of the semiconductor element, and there is no need for screwing, making it easy to attach and detach the semiconductor element. Furthermore, the holes in the substrate allow the semiconductor device to be cooled during use.

Description

【考案の詳細な説明】[Detailed explanation of the idea]

【0001】0001

【産業上の利用分野】[Industrial application field]

本考案は、半導体素子測定冶具に関し、特に半導体素子測定治具のストリップ ラインと半導体素子のピンとの取付け方法に関する。 The present invention relates to a semiconductor device measuring jig, particularly a strip of semiconductor device measuring jig. This invention relates to a method of attaching a line to a pin of a semiconductor element.

【0002】 ストリップラインは、少なくとも1枚の薄いストリップ導体を有する平行2導 体線路で、一般にその平行2導体線路の片側のストリップ導体と他の側の接地導 体との間に低損失誘電体平板がはさまれた構造をとっている。0002 A stripline is a line of two parallel conductors with at least one thin strip conductor. A strip conductor on one side of a parallel two-conductor line and a ground conductor on the other side. It has a structure in which a low-loss dielectric flat plate is sandwiched between the body and the body.

【0003】0003

【従来の技術】[Conventional technology]

従来の半導体素子測定冶具について図面を参照して説明する。 A conventional semiconductor device measuring jig will be described with reference to the drawings.

【0004】 図3は従来例の半導体素子測定冶具のブロック図、図4(a),(b)は従来 例の半導体素子測定冶具の接触部拡大図である。0004 Figure 3 is a block diagram of a conventional semiconductor device measurement jig, and Figures 4 (a) and (b) are conventional FIG. 2 is an enlarged view of a contact portion of an example semiconductor device measuring jig.

【0005】 図3及び図4に示す従来例の半導体測定冶具は、溝b14を有し半導体素子の くぼみ位置に合わせてネジ穴12が明けられた素子固定台b16と、素子固定台 b16上面に貼られたGND板b15と、GND板b15上に取り付けられたス トリップ導体と接地導体とその間にはさまれた低損失誘電体平板からなるストリ ップラインb17と、2本のネジ10により半導体素子を素子固定台b16に固 定する固定板11とで構成されている。[0005] The conventional semiconductor measuring jig shown in FIGS. 3 and 4 has a groove b14 and is used to measure the semiconductor element. An element fixing base b16 with screw holes 12 drilled in accordance with the recessed positions, and an element fixing base GND plate b15 pasted on the top surface of b16 and the strip attached on GND plate b15 A strip consisting of a trip conductor, a ground conductor, and a low-loss dielectric flat plate sandwiched between them. Fix the semiconductor element to the element fixing base b16 using the supply line b17 and two screws 10. It is composed of a fixed plate 11 that is fixed.

【0006】 図4(a)のように半導体素子に取り付けられている2本のピンを各々ストリ ップラインb17に重なるように溝b14上に置く。固定板11を半導体素子上 に置き、半導体素子のくぼみに合わせてネジ10を降ろし、素子固定台b16の ネジ穴12へねじ込む。その時、ピンがストリップラインb17上からずれてし まうので、ピンセット等で半導体素子をつまみながら微調整が必要となる。[0006] As shown in Figure 4(a), the two pins attached to the semiconductor element are Place it on the groove b14 so as to overlap the top line b17. Place the fixing plate 11 on the semiconductor element. , lower the screw 10 to match the recess of the semiconductor element, and then tighten the screw 10 on the element fixing base b16. Screw into screw hole 12. At that time, the pin shifted from the top of strip line b17. Since it moves, it is necessary to make fine adjustments while pinching the semiconductor element with tweezers or the like.

【0007】 また、図4(b)のようにピンが反っていた場合など、固定板で押さえつけて もピンとストリップラインb17との間に隙間があき、接触不良で測定ができな い場合がある。そのような場合、ピンを下方に反らし、ストリップラインb17 と接触するようにしてやらなければならず、これにより、半導体素子のピンに不 要な負荷を与えてしまうことがある。[0007] Also, if the pin is warped as shown in Figure 4(b), hold it down with a fixing plate. There is also a gap between the pin and strip line b17, making it impossible to measure due to poor contact. There are cases where In such a case, bend the pin downward and strip line b17 This must be done in such a way that it makes contact with the pins of the semiconductor device. This may cause an unnecessary load.

【0008】[0008]

【考案が解決しようとする課題】[Problem that the idea aims to solve]

上記した従来の半導体素子測定冶具は、半導体素子を素子固定台に固定する際 に位置合わせが困難であり、また、半導体素子に取り付けられたピンとストリッ プラインとの接触をよくするために、ピンを下方に反らして固定台に固定するの で、ピンに不要な負荷を与え、半導体素子に影響を与えることがあるという欠点 がある。 The conventional semiconductor device measuring jig described above is used when fixing a semiconductor device to a device fixing table. It is difficult to align pins and strips attached to semiconductor devices. In order to make better contact with the prine, bend the pin downward and fix it to the fixing base. The disadvantage is that it puts unnecessary load on the pin and may affect the semiconductor device. There is.

【0009】 さらに、半導体素子を固定台に固定すると風通しが悪く、使用時に半導体素子 を冷却することができないという欠点がある。[0009] Furthermore, if the semiconductor device is fixed to a fixed stand, ventilation is poor, and the semiconductor device is The disadvantage is that it cannot be cooled.

【0010】 本考案の目的は、半導体素子の形にくり抜かれた溝を持つ素子固定台と、中央 に半導体素子の形の穴が明いている低損失誘電体の基板と、基板と基板の上面に 貼られた接地導体と基板の下面に取り付けられた少なくとも2本のストリップ導 体とから成る少なくとも2本のストリップラインと、ストリップラインのストリ ップ導体上に設けられたバンプとを備え、半導体素子の少なくとも2本のピンを 少なくとも2本のストリップラインに合わせ、バンプでピンを素子固定台に押し 付け、半導体素子を測定することにより、上記の欠点を解消し、半導体素子のピ ンに対してなんら負荷を与えずピンとストリップラインとを正確に接触させるこ とができ、また、ネジ止めの必要が無く、半導体素子の着脱が容易に行え、さら に、使用時に基板の穴により半導体素子を冷却することができる半導体素子測定 冶具を提供することにある。0010 The purpose of this invention is to provide an element fixing base with a groove cut out in the shape of a semiconductor element, and a central A low-loss dielectric substrate with a hole in the shape of a semiconductor element on the top surface of the substrate and the top surface of the substrate. A affixed ground conductor and at least two strip conductors attached to the underside of the board. at least two striplines consisting of a body and a strip of striplines; bumps provided on the bump conductor, and at least two pins of the semiconductor element. Align with at least two strip lines and push the pin onto the element fixing base with a bump. By attaching and measuring the semiconductor device, the above drawbacks can be overcome and the pinpoint of the semiconductor device can be improved. It is possible to accurately contact the pin and the strip line without applying any load to the pin. In addition, there is no need for screws, and semiconductor elements can be easily attached and detached. For semiconductor device measurement, semiconductor devices can be cooled by holes in the substrate during use. The aim is to provide jigs.

【0011】[0011]

【課題を解決するための手段】 本考案の半導体素子測定冶具は、半導体素子の形にくり抜かれた溝を持つ素子 固定台と、中央に半導体素子の形の穴が明いている低損失誘電体の基板と、基板 と基板の上面に貼られた接地導体と基板の下面に取り付けられた少なくとも2本 のストリップ導体とから成る少なくとも2本のストリップラインと、ストリップ ラインのストリップ導体上に設けられたバンプとを備え、半導体素子の少なくと も2本のピンを少なくとも2本のストリップラインに合わせ、バンプでピンを素 子固定台に押し付け、半導体素子を測定している。[Means to solve the problem] The semiconductor device measuring jig of the present invention is a device that has a groove cut out in the shape of a semiconductor device. A fixed base, a low-loss dielectric substrate with a hole in the shape of a semiconductor element in the center, and a substrate. and a ground conductor affixed to the top side of the board and at least two ground conductors attached to the bottom side of the board. at least two striplines consisting of a strip conductor of and a bump provided on the strip conductor of the line, at least one of the semiconductor elements. Align the two pins with at least two strip lines, and align the pins with bumps. Semiconductor elements are measured by pressing them against the child fixing table.

【0012】0012

【実施例】【Example】

次に、本考案の実施例について図面を参照にして詳細に説明する。 Next, embodiments of the present invention will be described in detail with reference to the drawings.

【0013】 図1は本考案の一実施例の半導体素子測定冶具のブロック図、図2は本実施例 の半導体素子測定冶具の接触部拡大図である。[0013] Fig. 1 is a block diagram of a semiconductor device measuring jig according to an embodiment of the present invention, and Fig. 2 is a block diagram of a semiconductor device measuring jig according to an embodiment of the present invention. FIG. 3 is an enlarged view of the contact portion of the semiconductor device measuring jig.

【0014】 図1及び図2に示すの半導体素子測定冶具は、半導体素子の形にくり抜かれた 溝a5を持つ素子固定台a6と、中央に半導体素子の形の穴4が明いている低損 失誘電体の基板7と、基板7の上面に貼られたGND板a8と、基板7の下面に 取り付けられた2本のストリップ導体2と、ストリップ導体2上に設けられたバ ンプ3とから構成される。そして、上記の2本のストリップ導体2と基板7とG ND板a8とで2本のストリップラインa1を形成している。[0014] The semiconductor device measurement jig shown in FIGS. 1 and 2 is hollowed out in the shape of a semiconductor device. A low-loss device with an element fixing base a6 having a groove a5 and a hole 4 in the shape of a semiconductor element in the center. A dielectric substrate 7, a GND plate a8 pasted on the top surface of the substrate 7, and a GND plate a8 attached to the bottom surface of the substrate 7. The two attached strip conductors 2 and the bar provided on the strip conductors 2 3. Then, the above two strip conductors 2, the substrate 7 and G Two strip lines a1 are formed with the ND plate a8.

【0015】 ここで、半導体素子を素子固定台a6の半導体素子の形にくり抜いた溝a5に はめ込み、GND板a8及びストリップ導体2の取り付けられた基板7を半導体 素子の上部から重ねる。この時、図2に示すようにバンプ3が半導体素子のピン を素子固定台a6に押し付けるので、ピンに対して負荷を与えずにストリップラ インa1のストリップ導体2とピンとが確実に接触する。また、基板7上に穴4 が明いているので、使用時に半導体素子が冷却される。[0015] Here, place the semiconductor element in the groove a5 cut out in the shape of the semiconductor element on the element fixing base a6. Insert the board 7 with the GND plate a8 and the strip conductor 2 attached to the semiconductor Overlap from the top of the element. At this time, as shown in FIG. 2, the bump 3 is connected to the pin of the semiconductor element. Since the pin is pressed against the element fixing base a6, the strip plate can be removed without applying any load to the pin. The strip conductor 2 of the in-a1 and the pin are in reliable contact. Also, there is a hole 4 on the board 7. Since it is bright, the semiconductor element is cooled during use.

【0016】[0016]

【考案の効果】 以上説明したように、本考案の半導体素子測定冶具は、半導体素子を素子固定 台の半導体素子の形にくり抜いた溝にはめ込み、GND板及びストリップライン の取り付けられた基板を半導体素子の上部から重ね、この時、バンプが半導体素 子のピンを素子固定台に押し付け、また、基板上に穴を明けることにより、ピン に対してなんら負荷を与えずにピンとストリップラインとを正確に接触させるこ とができ、また、ネジ止めの必要が無く、半導体素子の着脱が容易に行え、さら に、使用時に半導体素子を冷却することができるという効果がある。[Effect of the idea] As explained above, the semiconductor device measuring jig of the present invention is capable of fixing a semiconductor device. Fit into the groove cut out in the shape of the semiconductor element on the stand, GND plate and strip line. The board with the bumps attached is stacked on top of the semiconductor element, and at this time, the bumps are By pressing the child pin against the element fixing base and by drilling a hole on the board, the pin It is possible to accurately contact the pin and the stripline without applying any load to the In addition, there is no need for screws, and semiconductor elements can be easily attached and detached. Another advantage is that the semiconductor element can be cooled during use.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本考案の一実施例の半導体素子測定冶具のブロ
ック図である。
FIG. 1 is a block diagram of a semiconductor device measuring jig according to an embodiment of the present invention.

【図2】本実施例の半導体素子測定冶具の接触部拡大図
である。
FIG. 2 is an enlarged view of the contact portion of the semiconductor device measuring jig of this embodiment.

【図3】従来例の半導体素子測定冶具のブロック図であ
る。
FIG. 3 is a block diagram of a conventional semiconductor device measuring jig.

【図4】従来例の半導体素子測定冶具の接触部拡大図で
ある。
FIG. 4 is an enlarged view of a contact portion of a conventional semiconductor device measuring jig.

【符号の説明】[Explanation of symbols]

1 ストリップラインa 2 ストリップ導体 3 バンプ 4 穴 5 溝a 6 素子固定台a 7 基板 8 GND板a 10 ネジ 11 固定板 12 ネジ穴 14 溝b 15 GND板b 16 素子固定台b 17 ストリップラインb 1 strip line a 2 strip conductor 3 Bump 4 holes 5 Groove a 6 Element fixing stand a 7 Board 8 GND plate a 10 screws 11 Fixed plate 12 Screw hole 14 Groove b 15 GND board b 16 Element fixing base b 17 Strip line b

─────────────────────────────────────────────────────
──────────────────────────────────────────────── ───

【手続補正書】[Procedural amendment]

【提出日】平成4年3月26日[Submission date] March 26, 1992

【手続補正1】[Procedural amendment 1]

【補正対象書類名】明細書[Name of document to be amended] Specification

【補正対象項目名】考案の名称[Name of item to be corrected] Name of invention

【補正方法】変更[Correction method] Change

【補正内容】[Correction details]

【考案の名称】 半導体素子測定治具[Name of the invention] Semiconductor device measurement jig

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 半導体素子の形にくり抜かれた溝を持つ
素子固定台と、中央に半導体素子の形の穴が明いている
低損失誘電体の基板と、前記基板と前記基板の上面に貼
られた接地導体と前記基板の下面に取り付けられた少な
くとも2本のストリップ導体とから成る少なくとも2本
のストリップラインと、前記ストリップラインのストリ
ップ導体上に設けられたバンプとを備え、前記半導体素
子の少なくとも2本のピンを少なくとも2本の前記スト
リップラインに合わせ、前記バンプで前記ピンを前記素
子固定台に押し付け、前記半導体素子を測定することを
特徴とする半導体素子測定冶具。
1. An element fixing table having a groove cut out in the shape of a semiconductor element, a low-loss dielectric substrate having a hole in the shape of the semiconductor element in the center, and a substrate attached to the upper surface of the substrate. at least two strip lines comprising a ground conductor and at least two strip conductors attached to the lower surface of the substrate; and bumps provided on the strip conductors of the strip lines; A semiconductor device measuring jig, characterized in that the semiconductor device is measured by aligning at least two pins with at least two of the strip lines and pressing the pins against the device fixing table with the bumps.
JP127791U 1991-01-21 1991-01-21 Semiconductor device measurement jig Pending JPH04117446U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP127791U JPH04117446U (en) 1991-01-21 1991-01-21 Semiconductor device measurement jig

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP127791U JPH04117446U (en) 1991-01-21 1991-01-21 Semiconductor device measurement jig

Publications (1)

Publication Number Publication Date
JPH04117446U true JPH04117446U (en) 1992-10-21

Family

ID=31898561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP127791U Pending JPH04117446U (en) 1991-01-21 1991-01-21 Semiconductor device measurement jig

Country Status (1)

Country Link
JP (1) JPH04117446U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019229798A1 (en) * 2018-05-28 2019-12-05 三菱電機株式会社 Electrical characteristic measuring device for semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019229798A1 (en) * 2018-05-28 2019-12-05 三菱電機株式会社 Electrical characteristic measuring device for semiconductor device
JPWO2019229798A1 (en) * 2018-05-28 2021-02-12 三菱電機株式会社 Electrical property measuring device for semiconductor devices

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