JPH04115592A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH04115592A JPH04115592A JP23674790A JP23674790A JPH04115592A JP H04115592 A JPH04115592 A JP H04115592A JP 23674790 A JP23674790 A JP 23674790A JP 23674790 A JP23674790 A JP 23674790A JP H04115592 A JPH04115592 A JP H04115592A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- resist
- layer
- section
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 44
- 239000004020 conductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 238000005476 soldering Methods 0.000 abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 13
- 230000004888 barrier function Effects 0.000 abstract description 8
- 230000000873 masking effect Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 230000002950 deficient Effects 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract 3
- 239000010949 copper Substances 0.000 abstract 3
- 238000010276 construction Methods 0.000 abstract 1
- RYZCLUQMCYZBJQ-UHFFFAOYSA-H lead(2+);dicarbonate;dihydroxide Chemical compound [OH-].[OH-].[Pb+2].[Pb+2].[Pb+2].[O-]C([O-])=O.[O-]C([O-])=O RYZCLUQMCYZBJQ-UHFFFAOYSA-H 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 26
- 230000007547 defect Effects 0.000 description 8
- 239000011247 coating layer Substances 0.000 description 7
- 239000011889 copper foil Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000007689 inspection Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000011179 visual inspection Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電子回路の配線および電子回路を構成する各種
の部品を実装することを目的とするプリント配線板に関
する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a printed wiring board for the purpose of mounting electronic circuit wiring and various components constituting the electronic circuit.
従来の技術
近年、電子機器の開発競争は停まることを知らず激しさ
を増している。その動向は、■軽小短薄、■製品寿命の
短命化、■多様化に代表される。したがって、それら電
子機器の動作を司どる電子回路に対する要求、制約も厳
しいものとなる。その結果、プリント配線板は高密度実
装を追求し、電子機器のデザインに適合すべく、−品一
様な外観形状を持ち合せた物を都度開発して行かなけれ
ばならない。加えて電子機器の性能1品質を保証する重
要なポイントは、電子部品を実装したプリント配線板の
完成度である。よって、プリント配線板の品質レベルを
向上すべく、種々の実装工法および検査方法の開発が行
なわれている。BACKGROUND OF THE INVENTION In recent years, competition in the development of electronic devices has become more and more intense. These trends are represented by ■lighter, smaller, shorter, and thinner products, ■shorter product lifespans, and ■diversification. Therefore, the demands and restrictions on the electronic circuits that control the operations of these electronic devices also become severe. As a result, in order to pursue high-density packaging and adapt to the design of electronic equipment, printed wiring boards with uniform external shapes must be developed each time. In addition, an important point in guaranteeing the performance 1 quality of electronic equipment is the degree of perfection of the printed wiring board on which electronic components are mounted. Therefore, various mounting methods and inspection methods are being developed in order to improve the quality level of printed wiring boards.
第3図a、bは従来例のプリント配線板の構成を示す平
面図および断面図である。図において、1は銅張り用基
板、2は電子回路の結線に基づいてエツチング形成され
た銅箔部、3は半田デイツプ後、銅箔部2に付着した半
田で、回路部品のリード端子7と銅箔2を電気抵抗がゼ
ロで結線している箇所である。4は第1のレジストコー
ティング層で、銅箔部間の半田付不良を防止する目的で
印刷されている。5はサービスマツプ(両面プリント配
線板の場合では、ロードマツプもありうる)と一般的に
総称される回路情報の印刷部である。FIGS. 3a and 3b are a plan view and a sectional view showing the structure of a conventional printed wiring board. In the figure, 1 is a copper-clad board, 2 is a copper foil part etched based on the connection of the electronic circuit, and 3 is solder that has adhered to the copper foil part 2 after soldering, and is connected to the lead terminal 7 of the circuit component. This is the location where the copper foil 2 is connected with zero electrical resistance. Reference numeral 4 denotes a first resist coating layer, which is printed for the purpose of preventing soldering defects between copper foil parts. Reference numeral 5 denotes a printed portion of circuit information generally collectively referred to as a service map (or a road map in the case of a double-sided printed wiring board).
6はサービスマツプ5とともに形成される第2のレジス
トコーティング層である。第1のレジストコーティング
層4と併せて銅箔2の間の半田付不良を防止する目的で
印刷されている。A second resist coating layer 6 is formed together with the service map 5. This is printed together with the first resist coating layer 4 for the purpose of preventing soldering defects between the copper foils 2.
このように構成された従来のプリント配線板について説
明する。半田デイツプ後の半田付不良、特に異極ならび
に異電位箇所間に発生する半田付着による電気的ショー
ト状態(以下半田ブリッジと呼ぶ)は第2レジストコー
ティング4ならびに第2レジストコーティング部6によ
り防いでいる。A conventional printed wiring board configured as described above will be explained. The second resist coating 4 and the second resist coating part 6 prevent poor soldering after soldering dip, especially electrical shorts caused by solder adhesion between points of different polarities and different potentials (hereinafter referred to as solder bridges). .
発明が解決しようとする課題
このような従来のプリント配線板では、半田付は不良を
軽減するという要請には叶っていたが、完全なものでは
なかった。そこで半田付は不良発生率を抑制し、加えて
不都合にも発生した半田付不良箇所を容易に、しかも的
確に発見しうるブ1ノント配線板の開発が望まれていた
。Problems to be Solved by the Invention In such conventional printed wiring boards, soldering has met the need to reduce defects, but it has not been perfect. Therefore, it has been desired to develop a non-contact wiring board that can suppress the incidence of soldering defects and, in addition, can easily and accurately detect soldering defects that have occurred.
本発明は上記問題を解決するもので、外形の大小にとら
れれず高密度実装のプリント配線板において、半田付は
不良率を軽減させ、さらに、人為的または機械的にプリ
ント配線板の品質検査を迅速かつ正確に行なえるプリン
ト配線板を提供することを目的とする。The present invention solves the above problems.In printed wiring boards that are mounted in high density regardless of the size of the external shape, soldering reduces the defective rate, and furthermore, the quality of printed wiring boards can be inspected manually or mechanically. The purpose of the present invention is to provide a printed wiring board that can quickly and accurately perform the following steps.
課題を解決するだめの手段
本発明は上記目的を達成するために、レジストコーティ
ング層および回路情報の印刷層に加えて、半田付着部で
ある銅箔部を孤立させるために黒色その他有彩色の半田
しろマスキング部を第3のレジストコーティング層とし
て備えた構成のプリント配線板とする。Means for Solving the Problems In order to achieve the above object, the present invention, in addition to the resist coating layer and the printed circuit information layer, uses black or other chromatic colored solder to isolate the copper foil portion where the solder is attached. The printed wiring board includes a white masking portion as a third resist coating layer.
作 用
本発明は上記の構成により、プリント配線板が半田ディ
ソプ工程を通過すると、第1層のレジストコーティング
を処理してない個所の銅箔部に溶解した半田が付着し凝
結する。これら銅箔の半田付着部の周囲に半田しろマス
キング部として具備した黒色の第3層レジスト部が、半
田噴流の流れを抑制し半田ブリッジなどの不良発生を低
下せしめ、その結果、半田銀白色と黒色とで構成する色
彩的高コントラストが容易に半田付品質の良否を判定す
るのに適切な情報を提供する。Effects According to the present invention, when the printed wiring board passes through the soldering process, the melted solder adheres to and condenses on the copper foil portions where the first layer resist coating has not been applied. The black third layer resist area provided as a solder masking area around the solder attachment area of these copper foils suppresses the flow of the solder jet and reduces the occurrence of defects such as solder bridges, and as a result, the solder becomes silvery white. The high color contrast with black provides information suitable for easily determining the quality of soldering.
実施例
以下、本発明の一実施例のプリント配線板について、図
面を参照しながら説明する。EXAMPLE Hereinafter, a printed wiring board according to an example of the present invention will be described with reference to the drawings.
第1図a、bは本発明の一実施例の構成を示す平面図お
よび断面図である。第1図では第3図に示した従来例の
第2のレジストコーティング6に代えて黒色の半田しろ
マスキング部8を具備している。その他の構成要素1〜
7については第3図と同一であるので、それらの説明を
省略する。FIGS. 1a and 1b are a plan view and a sectional view showing the structure of an embodiment of the present invention. In FIG. 1, a black solder margin masking portion 8 is provided in place of the second resist coating 6 of the conventional example shown in FIG. Other components 1~
7 are the same as those in FIG. 3, so their explanation will be omitted.
このように構成されたプリント配線板について、以下そ
の動作を説明する。The operation of the printed wiring board configured in this manner will be described below.
1)半田デイツプたれによる半田ブリッジなどの不良発
生率を減少せしめる目的でエツチング形成された半田付
着部を完全に孤立させるようなマスキング処理の第3の
レジスト層は、従来のダブルマスキング処理による半田
デイツプたれ防止用の障壁よりも長さおよび深さ方向と
もに強化された障壁を構成する。すなわち、本発明事例
従来事例
xl〉x2
Yl ≧ Y2
xl、Yl:障壁の長さおよび高さ(第1図参照)
x2.Y2:障壁の長さおよび高さ(第3図参照)
XおよびYは数値が多きいほどその障壁効果は大きくな
る。1) In order to reduce the incidence of defects such as solder bridges due to solder dip sagging, the third resist layer is masked to completely isolate the solder attachment area formed by etching. This constitutes a barrier that is stronger both in length and depth than the barrier for preventing dripping. That is, present invention case Conventional case xl>x2 Yl ≧ Y2 xl, Yl: length and height of barrier (see Figure 1) x2. Y2: Length and height of barrier (see Figure 3) The larger the values of X and Y, the greater the barrier effect.
11)次に所定の銅箔部半田付着箇所に半田デイツプ後
、半田が適切に付着したかどうかを判定することを容易
に、かつ的確に行なわせる目的で、前記第3のレジスト
層色として黒(その他色彩色)を利用する。従来のプリ
ント配線板では、第2のレジストコーティング層は回路
情報の印刷層と同時に形成されるので、白色(または、
回路情報の印刷色と同系色)となる。半田付着部周囲に
形成されたコーティング層色と、半田の銀白色との色彩
的コントラスト比は、直接的に、半田デイツプ後の目視
検査および自動検査装置の検出精度に影響を与える。第
2図a。11) Next, after soldering is applied to a predetermined solder attachment location on the copper foil, black is added as the third resist layer color in order to easily and accurately determine whether or not the solder has properly adhered. (Other colors) In conventional printed wiring boards, the second resist coating layer is formed at the same time as the circuit information printing layer, so it is white (or
(similar color to the circuit information printing color). The color contrast ratio between the color of the coating layer formed around the solder attachment portion and the silvery white color of the solder directly affects the visual inspection after solder dipping and the detection accuracy of an automatic inspection device. Figure 2a.
bは本発明のプリント配線板および従来のプリである。b is a printed wiring board of the present invention and a conventional circuit board.
第3図に示した従来のプリント配線板においては、第1
のレジスト層を緑色、第2のレジスト層を白色とし、第
2図に示した本発明のプリント配線板においては、第1
のレジスト層ヲ緑色、第2のレジスト層を白色、第3の
レジスト層を黒色としている。第3図の従来のプリント
配線板における相対的な色彩的コントラストの最も大き
い部分は半田と第1のレジスト層(緑色)の隣合う部分
であり、この相対色彩コントラスト比を02とする。ま
た、第2図に示す本発明のプリント配線板の相対的な色
彩的コントラストの最も大きい部分は半田と第3のレジ
スト層(黒色)との隣合う部分であり、この相対色彩的
コントラスト比を01 とする。このとき、C1と02
とを比較すると、C1〉C2
であり、半田がレジスト層を越えているかどうかを目視
判定するときに本発明のプリント配線板が従来のものよ
υも明確に、したがって迅速に判定できる。また、従来
例の白色の第2のレジストを越えるショート状態と比較
すると本発明の効果はさらに大きいものとなる。また、
判定を目視検査でなく、光変換器などを用いた光学的自
動診断器で行なうときにもコントラスト比の大きいこと
は判定精度を高めるのに有効である。このように、本発
明の実施例のプリント配線板によれば、第3のレジスト
層を設け、そのパターンで隣接する半田付着部の周辺を
互いに分離して囲い、その色彩を半田の色彩に対して相
対的に色彩的コントラスト比の大きいものとするプリン
ト配線板とすることにより、隣合う半田付着部間の障壁
を大きくすることができるとともに、半田のレジストを
越えた短絡状態を明確に、かつ迅速に検出することがで
きる。In the conventional printed wiring board shown in Fig. 3, the first
In the printed wiring board of the present invention shown in FIG. 2, the first resist layer is green and the second resist layer is white.
The first resist layer is green, the second resist layer is white, and the third resist layer is black. In the conventional printed wiring board shown in FIG. 3, the portion with the greatest relative color contrast is the portion where the solder and the first resist layer (green) are adjacent to each other, and this relative color contrast ratio is assumed to be 02. Furthermore, the portion of the printed wiring board of the present invention shown in FIG. 2 with the greatest relative color contrast is the portion where the solder and the third resist layer (black) are adjacent to each other, and this relative color contrast ratio is 01. At this time, C1 and 02
When compared with C1>C2, the printed wiring board of the present invention can visually determine whether or not the solder has exceeded the resist layer more clearly and therefore more quickly than the conventional printed wiring board. Moreover, the effect of the present invention is even greater when compared with the short circuit state in which the white second resist is exceeded in the conventional example. Also,
A large contrast ratio is also effective in increasing the accuracy of the judgment when the judgment is made not by visual inspection but by an optical automatic diagnostic device using an optical converter or the like. As described above, according to the printed wiring board of the embodiment of the present invention, the third resist layer is provided, and its pattern separates and surrounds the peripheries of adjacent solder attachment areas, and the color thereof is adjusted to match the color of the solder. By creating a printed wiring board with a relatively high color contrast ratio, it is possible to increase the barrier between adjacent solder attachment areas, and to clearly identify short-circuit conditions beyond the solder resist. Can be detected quickly.
発明の効果
以上の実施例から明らかなように、本発明は絶縁基板と
、その面上の回路導体部と、半田レジストを構成する第
1のレジスト層と、前記第1のレジスト層面に回路情報
をパターンで表示する第2のレジスト層とを備えたプリ
ント配線板において、前記第1のレジスト層の上に第3
のレジスト層を設け、前記第3のレジスト層のパターン
により、隣合う半田付着部の周囲を互いに分離して囲う
レジストを構成し、前記第3のレジスト層の色彩を半田
との相対的な色彩的コントラスト比の大きいものとする
プリント配線板とすることにより、隣接する半田付部分
間の障壁を大きくできるとともに、前記第3のレジスト
を越える半田付不良を的確に、かつ迅速に判定すること
ができる。Effects of the Invention As is clear from the above embodiments, the present invention includes an insulating substrate, a circuit conductor portion on the surface thereof, a first resist layer constituting a solder resist, and circuit information on the surface of the first resist layer. a second resist layer displaying a pattern in a pattern, a third resist layer is provided on the first resist layer;
The pattern of the third resist layer constitutes a resist that separates and surrounds adjacent solder attachment areas, and the color of the third resist layer is determined relative to the solder. By providing a printed wiring board with a high contrast ratio, it is possible to increase the barrier between adjacent soldered parts, and it is also possible to accurately and quickly determine soldering defects that exceed the third resist. can.
第1図a、bは本発明の一実施例のプリント配線板の構
成を示す平面図および断面図、第2図a。
bは本発明の一実施例のプリント配線板および従−1第
3図a、bは従来のプリント配線板の構成を示す平面図
および断面図である。
1・・・・・・銅張り用基板(絶縁基板)、2・・・・
・・銅箔部(回路導体部)、3・・・・・・半田(半田
付着部)、4・・・・・・第1のレジスト層、6・・・
・・・回路情報印刷層(第2のレジスト層)、8・・・
・・・第3のレジスト層。
代理人の氏名 弁理士 小鍜治 明 ほか2名第
図
*娯tfIR91支要園帥
第
図FIGS. 1a and 1b are a plan view and a sectional view showing the structure of a printed wiring board according to an embodiment of the present invention, and FIG. 2a is a sectional view. FIG. 3b is a plan view and a sectional view showing the structure of a printed wiring board according to an embodiment of the present invention, and FIGS. 3a and 3b are a conventional printed wiring board. 1... Copper-clad board (insulating board), 2...
...Copper foil part (circuit conductor part), 3...Solder (solder attachment part), 4...First resist layer, 6...
...Circuit information printing layer (second resist layer), 8...
...Third resist layer. Name of agent: Patent attorney Akira Okaji and two others Figure * Entertainment tfIR91 Supporting Officer Figure
Claims (1)
構成する第1のレジスト層と、前記第1のレジスト層面
に回路情報をパターンで表示する第2のレジスト層とを
備えたプリント配線板において、前記第1のレジスト層
の上に第3のレジスト層を設け、前記第3のレジスト層
のパターンにより、隣合う半田付着部の周囲を互いに分
離して囲うレジストを構成し、前記第3のレジスト層の
色彩を半田との相対的な色彩的コントラスト比の大きい
ものにしたプリント配線板。A printed wiring comprising an insulating substrate, a circuit conductor portion on the surface thereof, a first resist layer forming a solder resist, and a second resist layer displaying circuit information in a pattern on the surface of the first resist layer. In the plate, a third resist layer is provided on the first resist layer, and the pattern of the third resist layer constitutes a resist that separates and surrounds adjacent solder attachment parts, and A printed wiring board in which the color of the resist layer of No. 3 has a large color contrast ratio relative to the solder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23674790A JPH04115592A (en) | 1990-09-05 | 1990-09-05 | Printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23674790A JPH04115592A (en) | 1990-09-05 | 1990-09-05 | Printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04115592A true JPH04115592A (en) | 1992-04-16 |
Family
ID=17005191
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23674790A Pending JPH04115592A (en) | 1990-09-05 | 1990-09-05 | Printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04115592A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6976401B2 (en) | 2001-07-12 | 2005-12-20 | National Aerospace Laboratory Of Japan | Offset rotary joint unit equipped with rotation correction mechanism |
JP2006173337A (en) * | 2004-12-15 | 2006-06-29 | Daisho Denshi:Kk | Electronic module structure |
US7836788B2 (en) | 2002-10-30 | 2010-11-23 | Toyota Jidosha Kabushiki Kaisha | Articulated manipulator |
US7841256B2 (en) | 2003-02-07 | 2010-11-30 | Toyota Jidosha Kabushiki Kaisha | Articulated manipulator |
-
1990
- 1990-09-05 JP JP23674790A patent/JPH04115592A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6976401B2 (en) | 2001-07-12 | 2005-12-20 | National Aerospace Laboratory Of Japan | Offset rotary joint unit equipped with rotation correction mechanism |
US7836788B2 (en) | 2002-10-30 | 2010-11-23 | Toyota Jidosha Kabushiki Kaisha | Articulated manipulator |
US7841256B2 (en) | 2003-02-07 | 2010-11-30 | Toyota Jidosha Kabushiki Kaisha | Articulated manipulator |
JP2006173337A (en) * | 2004-12-15 | 2006-06-29 | Daisho Denshi:Kk | Electronic module structure |
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