JPH04113653A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04113653A
JPH04113653A JP23531190A JP23531190A JPH04113653A JP H04113653 A JPH04113653 A JP H04113653A JP 23531190 A JP23531190 A JP 23531190A JP 23531190 A JP23531190 A JP 23531190A JP H04113653 A JPH04113653 A JP H04113653A
Authority
JP
Japan
Prior art keywords
wiring section
power supply
output signal
gnd
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23531190A
Other languages
Japanese (ja)
Inventor
Masatoshi Matsumoto
雅俊 松本
Heihachi Matsumoto
松本 平八
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23531190A priority Critical patent/JPH04113653A/en
Publication of JPH04113653A publication Critical patent/JPH04113653A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To suppress the amount of electromagnetic radiation at low by extending a power supply wiring section and wiring for GND so as to be adjacent and by laying the power supply wiring in parallel to the output signal wiring section. CONSTITUTION:When setting gate electrode 7 of driver Tr at 'H', electric current flows from bonding pad 1 to main GND wiring section 22 via output signal wiring section 21, diffusion area 3 for output, diffusion area 5 for GND, and wiring section 19 for GND. Further, when setting gate electrode 8 of load Tr at 'H', electric current flows from wiring section 23 for main power supply to the bonding pad 1 via wiring section 20 for power supply, diffusion area 6 for power supply, diffusion area 3 for output, and wiring section 21 for output signal. That is, between the output signal wiring section 21 and the GND wiring section 19 and between the output signal wiring section 21 and the power supply wiring section 20 electric current flows in the directions opposite to each other. Therefore, phases of the radiated electromagnetic waves are also opposite to each other and they are cancelled by each other, thereby extremely reducing the electromagnetic waves to be externally radiated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置に係り、特に半導体集積回路か
らの電磁放射を小さくするパターンレイアウト法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to a pattern layout method for reducing electromagnetic radiation from a semiconductor integrated circuit.

〔従来の技術〕[Conventional technology]

半導体集積回路の高速化に伴い、電磁放射によるシステ
ムの不良が問題となっている。電磁放射の大きな回路と
して出力回路がある。第2図はその一例として出力部の
パターンレイアラ1−を示した図である。この図におい
て、1はポンディングパッド、2は出力回路とポンディ
ングパッド1を結ぶ出力信号配線部、3は出力回路の出
力用拡散領域、4はこの出力用拡散領域3と出力信号配
線部2とを接続するコンタクトホール、5はGND用拡
散領域、6は電源用拡散領域、7Cよ出力回路のドライ
バTrのゲー)・電極、8は出力回路のロドTrのゲー
ト電極、9は出力回路とメイン電源用配線部を結ぶGN
D用配線部、10は出力回路とメイン電源用配線部を結
ぶ電源用配線部、11は前記GND用拡散領域5とGN
D用配線部9を接続するコンタクトホール、12は前記
電源用拡散領域6と電源用配線部10を接続するコンタ
ク)−ホールである。
As semiconductor integrated circuits become faster, system failures due to electromagnetic radiation have become a problem. There is an output circuit as a circuit that emits a large amount of electromagnetic radiation. FIG. 2 is a diagram showing the pattern layerer 1- of the output section as an example. In this figure, 1 is a bonding pad, 2 is an output signal wiring section connecting the output circuit and the bonding pad 1, 3 is an output diffusion region of the output circuit, and 4 is this output diffusion region 3 and the output signal wiring section 2. 5 is a diffusion region for GND, 6 is a diffusion region for power supply, 7C is a gate electrode of the driver Tr of the output circuit, 8 is a gate electrode of the output circuit, and 9 is a gate electrode of the output circuit. GN connecting the main power supply wiring section
D wiring section, 10 is a power supply wiring section connecting the output circuit and the main power supply wiring section, and 11 is the GND diffusion region 5 and GN.
A contact hole 12 connects the D wiring portion 9, and a contact hole 12 connects the power source diffusion region 6 and the power source wiring portion 10.

次に、動作について説明する。Next, the operation will be explained.

ドライバTrのゲート電極7とロードTrのゲート電極
8には反対の信号が入るように設計されており、デー1
−電極7に“H′″の信号が入った場合には出力が°゛
L″、ゲート電極8に“H″の信号が入った場合には出
力が“H”となる。出力が“L ”からH″に変化する
時はポンディングパッド1に向って大電流が流れ出し、
出力が“H″から′L°′に変化する時はポジディング
パッド1からGND領域に大電流が流れ込む。
The gate electrode 7 of the driver Tr and the gate electrode 8 of the load Tr are designed to receive opposite signals.
- When an "H'" signal enters the electrode 7, the output becomes "L", and when an "H" signal enters the gate electrode 8, the output becomes "H".The output becomes "L". When changing from "to H", a large current flows toward the bonding pad 1,
When the output changes from "H" to 'L°', a large current flows from the positive pad 1 to the GND region.

いずれにしても、出力信号配線部2を大電流が流れるが
、この出力信号配線部2を短くできないことが少なくな
い。このため、出力信号配線[2をアンテナとして電磁
放射が起こる。
In any case, a large current flows through the output signal wiring section 2, but it is often impossible to shorten the output signal wiring section 2. Therefore, electromagnetic radiation occurs using the output signal wiring [2 as an antenna.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の出力部のパターンレイアウトでは、前述のごとく
電磁放射が起こる。この放射量は出力の“ON”、”O
FF”の周波数に比例するため、近年基々進んでいく半
導体集積回路の高速化の中、この電磁放射の問題が顕在
化してきた。
In the conventional pattern layout of the output section, electromagnetic radiation occurs as described above. This radiation amount is the output “ON”, “O”
Since the frequency of the electromagnetic radiation is proportional to the frequency of the FF, the problem of electromagnetic radiation has become more apparent as the speed of semiconductor integrated circuits has been increasing in recent years.

この発明は、上記のような問題点を解消するためになさ
れたもので、電磁放射量を低く抑えることができる半導
体装置を得ることを目的とする。
The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device that can suppress the amount of electromagnetic radiation.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、半導体基板上に配置され
た半導体集積回路の出力トランジスク回路と、この出力
トランジスタ回路の出力信号配線部と、出力トランジス
タ回路に接続された電源用配線部およびGND用配線部
とを含む半導体装置において、電源用配線部およびGN
D用配線部を延長して出力信号配線部に隣接し、かつ並
行に配置せしめたものである。
A semiconductor device according to the present invention includes an output transistor circuit of a semiconductor integrated circuit arranged on a semiconductor substrate, an output signal wiring section of the output transistor circuit, a power supply wiring section and a GND wiring connected to the output transistor circuit. In a semiconductor device including a power wiring section and a GN section,
The D wiring section is extended and placed adjacent to and parallel to the output signal wiring section.

〔作用〕[Effect]

この発明における半導体装置は、電磁放射を起こす出力
信号配線部の側に電流変化量が等しく、かつ電流方向の
逆の配線を設けることによって、出力信号配線部から全
く逆の位相の2種類の電磁波が放出される。2種類の電
磁波は非常に近接した場所から放出されるため、互いに
キャンセルし、外から見ると電磁放射が極端に軽減され
る。
In the semiconductor device of the present invention, two types of electromagnetic waves having completely opposite phases are generated from the output signal wiring section by providing wiring with equal current change amount and opposite current direction on the side of the output signal wiring section that causes electromagnetic radiation. is released. Because the two types of electromagnetic waves are emitted from very close locations, they cancel each other out, and when viewed from the outside, electromagnetic radiation is extremely reduced.

〔実施例〕〔Example〕

以下、この発明の一実施例を第1図について説明する。 An embodiment of the present invention will be described below with reference to FIG.

第1図において、第2図と同一符号は同一構成部分を示
し、21は出力回路とポンディングパッド1を結ぶ出力
信号配線部で、従来例より長くしである。19および2
0はこの出力信号配線部21の側に設けられたGND用
配線部と電源用配線部である。22はメインGND用配
線部、23はメイン電源用配線部、24は前記GND用
配線部19とメインGND用配線部22の接続用のコノ
ククトホール、25は前記電源用配線部20とメイン電
源用配線部23の接続用のコンタクト本ルである。
In FIG. 1, the same reference numerals as in FIG. 2 indicate the same components, and 21 is an output signal wiring section connecting the output circuit and the bonding pad 1, which is longer than the conventional example. 19 and 2
0 is a GND wiring section and a power supply wiring section provided on the output signal wiring section 21 side. 22 is a main GND wiring section, 23 is a main power supply wiring section, 24 is a connecting hole for connecting the GND wiring section 19 and the main GND wiring section 22, and 25 is a connection between the power supply wiring section 20 and the main power supply. This is a contact book for connection of the wiring section 23.

次に、動作について説明する。Next, the operation will be explained.

ドライバTrのゲート電極7を“H”にした場合、電流
はポンディングパッド1から出力信号配線部21.出力
用拡散領域3.GND用拡散領域5、GNDN耐用配線
9を経由してメインGND用配線部22に向って流れる
。また、ロードTrのゲート電極8を“H”にした場合
、電流はメイン電源用配線部23から電源用配線部20
.電源用拡散領域6.出力用拡散領域3.出力信号配線
部21を経由してポンディングパッド1に向って流れる
When the gate electrode 7 of the driver Tr is set to "H", the current flows from the bonding pad 1 to the output signal wiring section 21. Output diffusion area 3. It flows toward the main GND wiring section 22 via the GND diffusion region 5 and the GNDN durable wiring 9. Further, when the gate electrode 8 of the load Tr is set to "H", the current flows from the main power supply wiring section 23 to the power supply wiring section 20.
.. Diffusion area for power supply 6. Output diffusion area 3. The signal flows toward the bonding pad 1 via the output signal wiring section 21 .

つまり、上記のように出力信号配線部21とGNDN耐
用配線9の間または出力信号配線部21と電源用配線部
20の間では全く反対の方向に電流が流れる。それ故放
出される電磁波が全く逆位相となり、両者は互いに打ち
消しあうために外部に放出される電磁波が極端に軽減で
きる。
That is, as described above, current flows in completely opposite directions between the output signal wiring section 21 and the GNDN durable wiring 9 or between the output signal wiring section 21 and the power supply wiring section 20. Therefore, the emitted electromagnetic waves have completely opposite phases, and since they cancel each other out, the electromagnetic waves emitted to the outside can be extremely reduced.

なお、上記実施例では、出力信号配線部21の横に平行
に別の配線である゛GND用配線部19および電源用配
線部20を配置する例を示したが、これは出力信号配線
部21の上に別の配線を配置し、全く逆方向に電流が流
れるように回路を構成すれば、同様の効果が得られる。
In addition, in the above embodiment, an example was shown in which another wiring, the GND wiring part 19 and the power supply wiring part 20, is arranged parallel to the output signal wiring part 21; A similar effect can be obtained by placing another wiring above the circuit and configuring the circuit so that the current flows in the completely opposite direction.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は、半導体基板上に配置
された半導体集積回路の出力トランジスタ回路と、この
出力トランジスタ@路の出力信号配線部と、出力トラン
ジスタ回路に接続された電源用配線部およびGND用配
線部とを含む半導体装置において、電源用配線部および
GND用配線部を延長して出力信号配線部に隣接し、か
つ並行に配置せしめたので、電流が反対方向に流れるこ
とにより、放出される電磁波が全く逆位相となり、両者
互いに打ち消し合うため、外部への電磁放射が極端に軽
減できる。
As explained above, the present invention provides an output transistor circuit of a semiconductor integrated circuit disposed on a semiconductor substrate, an output signal wiring section of the output transistor@path, a power supply wiring section connected to the output transistor circuit, and a power supply wiring section connected to the output transistor circuit. In a semiconductor device including a GND wiring section, the power supply wiring section and the GND wiring section are extended and arranged adjacent to and in parallel with the output signal wiring section, so that current flows in the opposite direction, thereby reducing emission. Since the electromagnetic waves emitted are completely opposite in phase and cancel each other out, electromagnetic radiation to the outside can be extremely reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による出力部のパターンし
イアウl−を示す図、第2図は従来の出力部のパターン
レイアラl−を示す図である。 図において、1はボンブイノブパッド、3ば出力用拡散
領域、4,11,12,24,25はコノククトホール
、5はGND用拡散領域、6は電源用拡散領域、7はド
ライバTrのゲート電極、8はロードTrのゲート電極
、19はGND用配線部、20ば電源用配線部、21は
出力信号配線部、22はメイン電源用配線部、23はメ
イン電源用配線部である。 なお、各図中の同一符号は同一または相当部分を示す。
FIG. 1 is a diagram showing a pattern layout of an output section according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional pattern layout of an output section. In the figure, 1 is a bomb knob pad, 3 is an output diffusion region, 4, 11, 12, 24, and 25 are contact holes, 5 is a GND diffusion region, 6 is a power supply diffusion region, and 7 is a driver Tr diffusion region. 8 is a gate electrode of a load Tr, 19 is a GND wiring section, 20 is a power supply wiring section, 21 is an output signal wiring section, 22 is a main power supply wiring section, and 23 is a main power supply wiring section. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に配置された半導体集積回路の出力トラン
ジスタ回路と、この出力トランジスタ回路の出力信号配
線部と、前記出力トランジスタ回路に接続された電源用
配線部およびGND用配線部とを含む半導体装置におい
て、前記電源用配線部およびGND用配線部を前記出力
信号配線部に隣接し、かつ並行に配置せしめたことを特
徴とする半導体装置。
A semiconductor device including an output transistor circuit of a semiconductor integrated circuit arranged on a semiconductor substrate, an output signal wiring section of the output transistor circuit, and a power supply wiring section and a GND wiring section connected to the output transistor circuit. . A semiconductor device, wherein the power wiring section and the GND wiring section are arranged adjacent to and parallel to the output signal wiring section.
JP23531190A 1990-09-03 1990-09-03 Semiconductor device Pending JPH04113653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23531190A JPH04113653A (en) 1990-09-03 1990-09-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23531190A JPH04113653A (en) 1990-09-03 1990-09-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04113653A true JPH04113653A (en) 1992-04-15

Family

ID=16984232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23531190A Pending JPH04113653A (en) 1990-09-03 1990-09-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04113653A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101903930A (en) * 2007-12-21 2010-12-01 苹果公司 Method and apparatus for providing high speed, low EMI switching circuits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101903930A (en) * 2007-12-21 2010-12-01 苹果公司 Method and apparatus for providing high speed, low EMI switching circuits
JP2011508902A (en) * 2007-12-21 2011-03-17 アップル インコーポレイテッド Method and apparatus for forming a high speed, low EMI switching circuit
KR101354267B1 (en) * 2007-12-21 2014-01-22 애플 인크. Method and apparatus for providing high speed, low emi switching circuits

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