JPH04111507A - Amplifying circuit - Google Patents

Abstract

PURPOSE:To reduce the idling current flowing to an output amplification stage in the case of no signal by operating a first by-pass means in accordance with a current corresponding to the output current of a first driving transistor TR and operating a second by-pass means in accordance with a current corresponding to the output current of a second driving TR at the time of no signal. CONSTITUTION:An amplifying circuit 1 essentially consists of a first driving TR Tr3, a second driving TR Tr5, first and second bias means, first and second output amplification stages, and first and second by-pass means. An emitter area ratio of TRs Tr7 and Tr1 and TRs Tr8 and Tr2 is set to 1:N (N is a positive real number), and the value of a resistance R6 connected to the emitter of a TR Tr4 is so set that a collector current I3C of the first driving TR Tr3 is larger than a collector current I4C of the TR Tr4 in the first by-pass means. The value of a resistance R7 is set in the same manner. Thus, the idling current is reduced without reducing the drive capability for a load.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier circuit for push-pull amplification of an input signal, and particularly to an amplifier circuit with reduced idling current.

[Prior Art] Conventionally, a push-pull amplifier circuit as shown in FIG. 2 has been used in an audio output stage of a radio, tape recorder, etc. to amplify an input signal.

In the figure, the amplifier circuit 1 mainly includes a first drive stage A1,
a second drive stage A2, a first output stage consisting of transistors Tr1 and Tr7, and transistors Tr2 and Trg;
and a second output stage consisting of.

Here, the emitter area ratio of transistors Tr7 and Tri and the emitter area ratio of Trg and Tr2 are respectively 1:N(
positive real number).

An input signal A is applied to the first drive stage A1.

The output current of the first drive stage A1 is transmitted through the transistor Tr.
7 collector and base. transistor T
r7 and the transistor Tri are connected in a current mirror relationship, and the mirror ratio is set to N, so
The output current of the first drive stage A1 is 11 (however, I 1-
I IDC+IIAC, lIDCl; L DC current, II
ACi; L alternating current), the collector current of the transistor Tri becomes N-11, and this current is supplied to the capacitor c1 and the resistor R5.

On the other hand, an input signal λ having a phase opposite to that of the input signal A is applied to the second drive stage A2. The output current of the second drive stage A2 is supplied to the collector and emitter of the transistor Trg. The transistor Trg and the transistor Tr2 are
are connected in a current mirror relationship, and the mirror ratio is N
Therefore, the output current of the second drive stage A2 is
2 (However, I 2-I 2DC+I 2AC, 12DC
is a direct current and 12AC is an alternating current), the collector current of the transistor Tr2 is N-12, and this current is supplied to the resistor R5 serving as a load via the coupling capacitor C1.

In addition, since the input signals A and S are in a relationship of opposite phases to each other, the output currents of the transistors Tri and Tr2 are passed through the coupling capacitor C1 in a push-pull relationship to the resistor R5 serving as a load. is supplied to

[Problems to be Solved by the Invention] In the conventional amplifier circuit 1 described above, in order to increase the amplification factor, it is necessary to increase the mirror ratio, and the value of N is set to 10.
Must be set between 0 and 200. however,
If N is set to such a value, the output DC currents of the first and second drive stages A1 and A2 will also be amplified by N times.

In a push-pull type amplifier circuit, in order to prevent crossover distortion, a predetermined idling current must flow through the output transistor when there is no signal, but as mentioned above, if the value of N is increased, the idling current (
There is a problem in that the amount of direct current (direct current) becomes larger than necessary, resulting in large current consumption.

The present invention has been made in view of the above-mentioned problems, and an object of the invention is to
An object of the present invention is to provide an amplifier circuit that can reduce idling current.

[Means for Solving the Problems] In order to achieve the above object, the present invention improves an amplifier circuit.

That is, a first drive transistor that amplifies the first input signal, a second drive transistor that amplifies the second input signal, a first bias means that supplies a bias current to the base of the first drive transistor, and the first drive transistor that amplifies the first input signal. a second bias means for supplying a bias current to the base of the second drive transistor; a first output amplification stage for amplifying the output current of the first drive transistor; and a first output amplification stage for amplifying the output current of the second drive transistor; a second output amplification stage that supplies the output signal of the first output amplification stage to the load in a push-pull relationship;
a first bypass means for bypassing a portion of the output current of the second drive transistor according to a current corresponding to the output current of the first drive transistor; and a current corresponding to the output current of the second drive transistor. and second bypass means for bypassing a part of the output current of the first drive transistor in accordance with the output current of the first drive transistor.

[Operation] In the present invention, when there is no signal, the first bypass means is operated according to the current corresponding to the output current of the η1 drive transistor, and the first bypass means is operated according to the current corresponding to the output current of the second drive transistor. Since the second bypass means is operated accordingly, it is possible to reduce the idling current flowing to the output amplification stage when there is no signal.

In addition, when input signals having opposite phases to each other), . It has a large amplification factor of , and can sufficiently amplify the input signal.

[Example] Preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram of an amplifier circuit according to the present invention.

Circuit Configuration Description The amplifier circuit 1 mainly includes a first drive transistor Tr3, a second drive transistor Tr5, first and second bias means, first and second output amplification stages, and first and second drive transistors. and a bypass means.

The first bias means includes a current source 7 and a transistor Tr.
14, a resistor R3, and a resistor R4, and the second bias means includes a current source 6, a transistor Tr13, a resistor R1, and a resistor R2.

The first output amplification stage consists of current mirror connected transistors Tri and Tr7, and the second output amplification stage consists of current mirror connected transistors Tr2 and Tr8.

The first bypass means consists of transistors Tr12 and Trll in current mirror connection with transistor Tr4, and the second bypass means consists of transistors Trlo and Tr9 in current mirror connection with transistor Tr6.

Circuit Connection Description The first input terminal 3 is connected to the base of the first drive transistor Tr3 and the base of the transistor Tr4 of the first bypass means, and the second input terminal 4 is connected to the base of the second drive transistor Tr5. Transistor Tr6 of the second bypass means
The input signal is applied to the base of the

At the same time, the base of the first drive transistor Tr3 and the base of the transistor Tr4 of the first bypass means are current mirror-connected to the base of the transistor Tr14 of the first bias means via resistors R3 and R4 connected in series, Bias current is supplied.

The intermediate connection point between resistors R3 and R4 of the first bias means is
The collector of the transistor Tr14 is connected to the current source 7, and the emitter of the transistor Tr14 is connected to the power supply terminal 2.

The base of the second drive transistor Tr5 and the base of the transistor Tr6 of the second bypass means are also current mirror connected to the base of the transistor Tr13 of the second bias means via resistors R1 and R2 connected in series, A bias current is supplied.

The intermediate connection point between the resistors R1 and R2 of the second biasing means is
The collector of the transistor Tr13 is connected to the current source 6, and the emitter of the transistor Tr13 is connected to the power supply terminal 2.

The collector of the first drive transistor Tr3 is connected to the base and collector of the transistor Tr7 in the first output amplification stage, and the collector of the second drive transistor Tr5 is connected to the collector and base of the transistor Trg in the second output amplification stage. be done.

The transistors Tr7 and Trl of the first output amplification stage are connected in a current mirror, and the transistors Tr7 and Tri
The emitter of is connected to the output terminal 5, and the emitter of the transistor T
The bases of ri and Tr7 are connected to the collector of the transistor Tr9 of the second bypass means.

The emitters of the transistors Trg and Tr2 of the second output amplification stage are connected to the ground terminal 8, and the transistor Tr2
and the base of Tr8 is connected to the collector of transistor Trll of the first bypass means.

The collector of the transistor Tr4 of the first bypass means is connected to the base and collector of the transistor Tr12,
The emitter of the transistor Tr4 is connected to the power supply terminal 2 via the resistor R6, and the emitter of the transistor Tr4 is connected to the power supply terminal 2 via the resistor R6.
The emitter of 2 is connected to the ground terminal 8.

The collector of the transistor Tr5 of the second bypass means is connected to the base and collector of the transistor Tr9, the emitter of the transistor Tr6 is connected to the power supply terminal 2 via the resistor R7, and the emitters of the transistors Tr9 and TrlO are connected to the output Connected to terminal 5.

A resistor R5 serving as a load is connected to the output terminal 5 via a coupling capacitor C1.

Description of circuit operation The amplifier circuit 1 is constructed as described above, and the transistor T
The emitter area ratio of r7 and Trl and the transistors Tr8 and Tr2 is set to 1:N (positive real number), and the collector current I3C of the first drive transistor Tr3 is higher than the collector current 14C of the transistor Tr4 of the first bypass means. Similarly, the value of the resistor R6 connected to the emitter of the transistor Tr4 is set so that the collector current 15G of the second drive transistor Tr5 becomes larger than the collector current 16C of the transistor Tr6 of the second bypass means. The value of the resistor R7 connected to the emitter of the transistor Tr6 is set as follows.

When there is no signal: When no signal is applied to the first input terminal 3 and the second input terminal 4, the collector currents I3C and I4C of the transistors Tr3 and Tr4 change depending on the current flowing to the current source 7 of the first bias means. Moreover, since the collector currents I3C and 14C of the transistors Tr3 and Tr4 are determined as described above, the collector current of the transistor Tr3 becomes large. Also, depending on the current flowing through the current source 6 of the second bias means, the transistors Tr5 and Tr
Since the collector current of transistor Tr5 and Tr6 is determined, and the collector currents of transistors Tr5 and Tr6 are determined as described above, the collector current of transistor Tr5 becomes large.

In the first bypass means, the collector current I4C of the transistor Tr4 is inverted, so that the collector current Tr5C of the second drive transistor Tr5 is changed from the collector current I4C of the transistor Tr4 to the transistor T
The current after subtracting the collector current I4C of r4 (15C-
I4C) flows to the transistor Tr8 of the second output amplification stage. Furthermore, since the mirror ratio of the transistors Tr8 and Tr2 is set to 1:N as described above, the current flowing through the transistor Tr2 is N times the collector current 18C of the transistor Tr8. Conventionally, the transistor Tr
Since N times the collector current 15C of No. 5 was flowing, the idling current is reduced from 15C to (15C-I4C).

Further, in the second bypass means, the collector current I6C of Tr6 is inverted, so that the first drive transistor T
A current (Tr3C-Tr6C) obtained by subtracting the collector current Tr6C of Tr6 from the collector current Tr3C of r3 flows through the transistor Tr7 of the first output amplification stage. Moreover, since the mirror ratio of the transistors Tr7 and Trl is set as described above (1:N), the transistor Tri
The current flowing in is the collector current 17 of the transistor Tr7.
It is N times C. Conventionally, N times the collector current 13C of the transistor Tr3 flows, so the idling current is reduced from 13C to (I3C-16C).

When input signals are applied: When a negative signal is applied to the first input terminal 3 and a positive signal is applied to the second input terminal 4, the first drive transistor Tr3 and the first A current flows through the transistor Tr4 of the bypass means. This collector current Tr
3C is supplied to the first output amplification stage, and the collector current T
r4C is a current mirror connected Trll and T'12
is supplied to

Further, since the positive input signal is applied to the base of the second drive transistor Tr5 and the base of the transistor Tr5 of the second bypass means via the second input terminal 4, the second drive transistors Tr5 and Tr6 are in operation. do not. Therefore, no current is supplied to the second output amplification stage and the transistors Tr8 and Tr2 of the second output amplification stage do not operate.Therefore, the first bypass means does not adversely affect the second output amplification stage. .

With the above operation, only the collector current I3C of the first drive transistor Tr3 is supplied to the transistor Tr7 of the first output amplification stage, and the transistor Collector current 17 of transistor Tr7 to Tri
A current N times that of C flows. This current (I7C-N) is
The signal is supplied to a resistor R5 serving as a load via an output terminal 5 and a coupling capacitor C1.

Next, when a positive signal is applied to the first input terminal 3 and a negative signal is applied to the second input terminal 4, the positive signal is passed through the first input terminal 3 to the first drive transistor. Since the voltage is applied to the base of Tr3 and the base of the transistor Tr4 of the first bypass means, the first drive transistors Tr3 and Tr4 do not operate. Therefore, the first drive transistor T
No current is supplied from r3 to the first output amplification stage, and no current is supplied from transistor Tr4 of the first bypass means to mirror-connected transistors Trll and Tr12.

Further, since the negative input signal is applied to the base of the second drive transistor and the transistor Tr5 of the second bypass means via the second input terminal 4, the second drive transistor Tr5 and the second drive transistor Tr5 and A current flows through the transistor Tr6 of the second bypass means. This second drive transistor Tr
A collector current of 5 is supplied to the second output amplification stage.

Note that the second bypass means also does not adversely affect the first output amplification stage.

With the above operation, only the collector current 15C of the second drive transistor Tr5 is supplied to the transistor Tr8 of the second output amplification stage, and the mirror ratio (1:N) of the transistors Trg and Tr2 is used as described above. A current N times the collector current I8C of the transistor Tr8 flows through T r 2. This current (18C-N)
is supplied to a resistor R5 serving as a load via an output terminal 5 and a coupling capacitor C1.

As explained above, according to this embodiment, it is possible to reduce the idling current when there is no signal, and when input signals having opposite phases to each other are applied, the amplification factor similar to the conventional one can be reduced. can amplify the input signal.

In the embodiment shown in FIG. 1, a current limiting resistor R6 is connected to the emitter of the transistor Tr4 of the first bypass means.
One end of the resistor R6 is connected to the power terminal 2, and the other end of the resistor R6 is connected to the power supply terminal 2. However, one end of the resistor R6 is not provided here, and one end of the resistor R6 is connected to the emitter of the transistor Trll of the first bypass means. Connect the other end to the ground terminal 8,
Furthermore, one end of a current limiting resistor R7 is connected to the emitter of the transistor Tr6 of the second bypass means, and the other end of the resistor R7 is connected to the power supply terminal 2, but the resistor R is not provided here.
Even if one end of the resistor R7 is connected to the emitter of the transistor Tr9 of the second bypass means and the other end of the resistor R7 is connected to the output terminal 5, the same effect as the amplifier circuit of FIG. 1 can be obtained.

[Effects of the Invention] As described above, according to the present invention, when push-pull amplifying an input signal, it is possible to reduce the idling current when there is no signal without reducing the amplification factor when the input signal is applied compared to the conventional method. There is an effect.

Therefore, there is an advantage that an extremely useful amplifier circuit can be provided for small electronic devices such as battery-powered tape recorders that require low current consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a preferred embodiment of an amplifier circuit according to the present invention, and FIG. 2 is a circuit diagram of a conventional amplifier circuit. 1... Amplifier circuit power supply terminal 1st input terminal 2nd input terminal Output terminal... Current source ground terminal 1st drive stage 2nd drive stage capacitor... Resistor 14... Transistor 2...・ 3 ... 4 ... 5 ... 6-7 8 ... A1 ... A2 ... I R1-R7 Tri-Tr

Claims (1)

[Claims] A first drive transistor that amplifies a first input signal, a second drive transistor that amplifies a second input signal, and a first bias that supplies a bias current to the base of the first drive transistor. means for supplying a bias current to the base of the second drive transistor; a first output amplification stage for amplifying the output current of the first drive transistor; and a first output amplification stage for amplifying the output current of the second drive transistor. a second output amplification stage that supplies the output signal of the first output amplification stage to the load in a push-pull relationship; and an output of the second drive transistor according to a current corresponding to the output current of the first drive transistor. a first shunting means for shunting a portion of the current; and a second shunting means for shunting a portion of the output current of the first drive transistor in response to a current corresponding to the output current of the second drive transistor. 1. An amplifier circuit comprising: a circuit means;