JPH04111400A - Evaluation method for component arrangement on printed-circuit board - Google Patents

Abstract

PURPOSE:To offer an evaluation value whose accuracy is better by a method wherein the route of a temporary interconnection is judged by taking into consideration the feature of an actual interconnection algorithm. CONSTITUTION:A channel in which an interconnection can be executed is read out from information on a component mounting operation and from information on a board; it is registered on a table which holds information on an empty channel. A flag which indicates a channel directly under a component is erected. The total length of the channel directly under the component and empty channels other than it is counted for each split region; the possibility of an interconnection directly under the component and the frequency factor of an interconnection at each layer are input from the information on the component mounting operation and from the information on the board; the length of the empty channels in the split region is computed. Pins to be wired are computed from logic information; the position of a route region when it is approximated by an L-shaped temporary interconnection is computed. The total length of the empty channels in the found route region is computed for individual routes (for two routes). The expected value of the length of the empty channels is computed and counted from expected values of the total length of the empty the length of the temporary interconnection in the channels, region and the length of the already computed temporary interconnection. When the logic information is not available, the expected value of the length of the counted temporary interconnection is divided by the total length of the computed empty channels; their ratio is displayed or output on a list, a terminal device and an auxiliary storage device.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for connecting components to L after arranging them on a printed circuit board.
The present invention relates to a method of evaluating component placement before actual wiring based on the degree of congestion based on the assumption that wiring is based on a linear approximation, and a method of calculating the degree of congestion to obtain an evaluation result that closely resembles the actual wiring result.

[Conventional technology]

The conventional method, as described in Japanese Unexamined Patent Publication No. 63-174177, divides the entire board and estimates the effective wiring area and virtual wiring route for each divided area, and calculates the horizontal and vertical components. The area distribution of the two is calculated, the degree of occupancy of the divided area is determined from the difference between the two area distributions, and this distribution is displayed to improve wiring efficiency, in other words, to evaluate component placement.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into consideration the fact that in the actual wiring algorithm, empty channels directly under the component may not be used depending on the shape of the mounted component, and the feature of wiring with fewer layers is not considered, In this case, since all channels are treated as the same free channels, there is a possibility that a route different from the actual wiring route is selected, and there is a problem that accurate evaluation is not possible.

An object of the present invention is to determine the route of temporary wiring in consideration of the characteristics of the actual wiring algorithm, and to provide a more accurate evaluation value.

Furthermore, the above-mentioned conventional technology does not take into consideration the influence of errors when the routes of the actual wiring and the temporary wiring do not match, and there is also a problem that accurate evaluation is not possible.

The present invention also refers to a method of reducing errors caused by route selection between actual wiring and temporary wiring, and aims to provide more accurate evaluation values.

[Means to solve the problem]

In order to take into account the characteristics of the actual wiring algorithm for the above purpose, when counting the free channel length of the temporary wiring route candidate area,
A process is added to count the length of the free channel directly under the component and the length of other free channels, and to multiply the total length of the free channels directly under the component by a coefficient specific to the component shape (referred to as routing possibility). This is an additional process in which the total channel length is multiplied by a coefficient (referred to as a wiring frequency coefficient) proportional to the wiring frequency of that layer.

Furthermore, in order to reduce the error caused by route selection between actual wiring and temporary wiring, the selection probability of each route candidate area is calculated from the total length of free channels obtained using the above method, and the expected value of the temporary wiring length is calculated. This is what I did.

[Effect]

In one divided area divided by user specification or system fixed, the total length of free channels (U
The count of λ) is calculated using Equation 1 from the total length of empty channels directly under the component (on ue), the possibility of wiring directly under the component with a fixed component shape (Rpi), and the total length of other empty channels (on ue).

u i =u P i X RP i + u e L
(Formula 1) Furthermore, the total length (U) of free channels (total of all layers) in one divided area is the wiring frequency coefficient (Rs
i) and the above u using equation 2.

μ=ΣμλXRsλ (Equation 2) Rp of Equation 1
There are a method in which i is obtained as component information and Rsi in equation 2 is board information from a library, a method in which it is obtained from a system-specific calculation formula, an initial value, and a method in which the user arbitrarily specifies it at the time of execution. By determining the total length of free channels in one divided area from Equation 1.2, it becomes possible to perform an evaluation that takes into consideration the characteristics of the wiring algorithm described above.

In addition, the expected value of the tentative wire length (E (L) ) in one divided area on a certain route (for example, route 1) is calculated by the tentative wire length (L) of that divided area and the total length of free channels in all route areas. (Route 1: LIAcby Route 2: Ll
:,,c) and the tentative wiring expected value already counted in the route area (route 1: E(L)′A,,L, route 2: E(L)
It is determined from htL using equation 3.

E(L)"LX ((LLAcc-E(L)ALL)/
(LLAt, c-E(L)Atc” LiAcc-E
(L) ac, , ) ) (Formula 3) Here, the value in parentheses on the right side is the selection probability of route 1. By counting this tentative wiring expected value over the entire area of routes 1 and 2, it is possible to reduce the influence of the difference between the routes and the actual wiring, and it is possible to provide a highly accurate evaluation value.

〔Example〕

The flow of processing will be explained below as an embodiment of the present invention with reference to FIG. 1 in the figure reads channels that cannot be wired from component mounting information and board information, and registers them in a table that holds vacant channel information.

Additionally, a flag is set to indicate that the channel is directly under the component. The relationship between this table structure and channels is shown in FIG. There is one cell area for each unit channel length of each layer, and one cell is composed of two types of flags for distinguishing between empty/no wiring and directly under a component/other. 2 in Fig. 1 is calculated from the table shown in Fig. 2 for each divided area by counting the total length of free channels directly under the component and other free channels, and calculating the wiring possibility directly under the component and the wiring frequency coefficient for each layer using the component mounting information, respectively. Input from the board information, and calculate the total length of free channels in one divided area using equations 1 and 2 described above. 3 in FIG. 1 calculates the pin-to-pin to be connected from the logical information, and calculates the route area position when approximated by L-shaped temporary wiring. 4 in Figure 1 is the total length of free channels in the route area obtained in 3 for each route (
There are two routes).

At 5 in FIG. 1, the expected value of the temporary wire length is calculated and counted using the above-mentioned equation 3 from the total free channel length obtained in step 4, the temporary wire length of the divided area, and the already counted expected value of the temporary wire length. 1st
At 6 in the figure, the presence or absence of logical information is determined, and if there is remaining information, step 3 is executed, and if there is no remaining information, step 7 is executed. 7 in FIG. 1 divides the counted expected value of the temporary wiring length by 2 by the calculated total length of free channels, and displays or outputs the ratio as 8 on a list, terminal device, or auxiliary storage device.

〔Effect of the invention〕

According to the present invention, tentative wiring is estimated from pre-wiring information in consideration of the characteristics of the actual wiring algorithm, so that evaluation results close to actual wiring can be obtained and the accuracy of evaluation can be improved.

Further, since the expected value of the temporary wiring length is counted, even if a route different from the actual wiring is estimated, the influence can be suppressed, and there is also an effect of improving the accuracy of evaluation.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the processing flow of an embodiment of the present invention and input/output equipment in each process, and Fig. 2 is a diagram showing the correspondence between the table structure for counting the number of empty channels and the channels on the board. be. High 1 Illustrated 2 Diagram

Claims (2)

[Claims] 1. From the component mounting information, logic information, and board information, calculate the total length of free channels that can be used for wiring in each board division area (or the entire board) and the total wiring (temporary wiring) for evaluation by L-shaped approximation of the connection relationship. The following (
A printed circuit board component placement evaluation method characterized by realizing any or all of a) to (c). (a) A method of counting the total length of empty channels directly under the component by a proportion specific to the component shape when determining the temporary wiring route, taking into account that the area directly under the component is difficult to actually route. (b) In the temporary wiring A method of calculating the total length of free channels in the route candidate area, which is counted during L-shaped approximation, by the total length of free channels in each layer, which is proportional to the frequency of use of each layer in the actual wiring. (c) Temporary wiring is set to L A method of counting the tentative wire length (expected tentative wire length) that is proportional to the ease of wiring in both of the two route candidate regions considered when making a shape approximation. 2. A printed circuit board component placement evaluation method characterized in that the target area is the vacant area area and the total area of temporary wiring instead of the total length of empty channels and the total length of temporary wiring as used in claim 1.