JPH04111359A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04111359A JPH04111359A JP22966190A JP22966190A JPH04111359A JP H04111359 A JPH04111359 A JP H04111359A JP 22966190 A JP22966190 A JP 22966190A JP 22966190 A JP22966190 A JP 22966190A JP H04111359 A JPH04111359 A JP H04111359A
- Authority
- JP
- Japan
- Prior art keywords
- output buffer
- transistor
- breakdown
- channel length
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title description 2
- 230000015556 catabolic process Effects 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000006378 damage Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ICの静電破壊の耐性を向上することのでき
る出力バッファ回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit that can improve resistance to electrostatic damage of an IC.
本発明は出力バッファの出力部分すなわちMOSトラン
ジスタのドレイン部分にノイズが入った場合、ドレイン
部のPN接合によるアバランシニラ降伏か、ソース・ド
レインのパンチスルーでノイズをグランドに逃がすこと
により、素子の破壊を防ぐものである。In the present invention, when noise enters the output part of the output buffer, that is, the drain part of the MOS transistor, the device is prevented from being destroyed by letting the noise escape to ground through avalancinilla breakdown due to the PN junction of the drain part or punch-through between the source and drain. It is something to prevent.
従来、出力バッファ部での静電破壊の耐性を高める技術
として、ソース・ドレインの電極となるコンタクトとゲ
ートのスペースを広げる。ドレイン・ソースの面積を大
きくする、またドレイン・ソースの濃度を濃くし、拡散
の濃度勾配をゆるく、深くし、電界をゆるめてかつアバ
ランシェ降伏も低(する方法が知られていた。Conventionally, as a technique to increase resistance to electrostatic discharge damage in the output buffer section, the space between the contact and the gate, which serve as the source/drain electrodes, is widened. Known methods include increasing the area of the drain and source, increasing the concentration of the drain and source, making the concentration gradient of diffusion gentler and deeper, loosening the electric field, and lowering avalanche breakdown.
しかし、従来の方法では微細化にともないドレイン・ソ
ースが浅い不純物拡散となるため、濃度勾配も急峻とな
り、ドレイン端で電界が強くホットエレクトロンが発生
しやすくなる。そのため微細化されたMOSでは出力ト
ランジスタに大きなノイズがのった時にはこのホットエ
レクトロンで引き起こされるスナップバンク現象でドレ
イン永久破壊が起きるという欠点があった。However, in conventional methods, as miniaturization occurs, impurity diffusion becomes shallow in the drain and source, resulting in a steep concentration gradient and a strong electric field at the drain end, making hot electrons more likely to be generated. Therefore, miniaturized MOS has the disadvantage that when large noise is applied to the output transistor, the snap bank phenomenon caused by these hot electrons causes permanent destruction of the drain.
上記問題点を解決するために、本発明は出力ハンコア部
のNMO5I−ランジスタの耐圧がトルイン部でのPN
接合アバランシヱ降伏が、チャネル部でのパンチスルー
で起きるチャネル長を選ぶことにより、出力バッファの
耐圧は微細化された不純物層で形成されたトランジスタ
を使用しても強くなることができた。In order to solve the above problems, the present invention has been developed so that the withstand voltage of the NMO5I-transistor in the output hammer core section is PN at the toru-in section.
By selecting a channel length where junction avalanche breakdown occurs due to punch-through in the channel portion, the breakdown voltage of the output buffer can be increased even when using a transistor formed with a miniaturized impurity layer.
上記最適化されたチャネル長を持つトランジスタで形成
された出力バッファノイズが入った場合、先にドレイン
部でのアバランシェでブレイクダウンまたはパンチスル
ーでブレイクダウンするため、永久破壊に至らないバッ
ファが得られた。When noise enters the output buffer formed by the transistor with the optimized channel length, it first breaks down due to avalanche or punch-through at the drain, so a buffer that does not cause permanent damage can be obtained. Ta.
以下に本発明の具体的な実施例に基づいて説明する。 The present invention will be explained below based on specific examples.
第1図は公知の半導体装1の製造方法を使って作成した
LDD構造のNMO3トランジスタのドレイン部に電流
を注入し、ドレインが永久破壊したときの電流値とその
時のMOSトランジスタのチャネル長を示したものであ
る。チャネル長が4−以上、あるいは1.2−以下のト
ランジスタ破壊xfLは大きくなり、逆に4趨以下1.
2−以上のトランジスタは小さい電流で永久破壊するこ
とが分かる。従って、出力バッファに使用するトランジ
スタのL長を4辱以上あるいは1.2−以下とするとノ
イズに強い出力バッファを得ることができる。Figure 1 shows the current value when the drain is permanently destroyed when a current is injected into the drain part of an NMO3 transistor with an LDD structure manufactured using a known method for manufacturing a semiconductor device 1, and the channel length of the MOS transistor at that time. It is something that When the channel length is 4 or more or 1.2 or less, the transistor breakdown xfL increases; conversely, if the channel length is 4 or less, 1.
It can be seen that transistors with a value of 2 or more are permanently destroyed by a small current. Therefore, if the L length of the transistor used in the output buffer is set to 4 or more or 1.2 or less, an output buffer that is resistant to noise can be obtained.
以上のようにチャネル長の最適化により、不純物層の深
さや濃度、ドレイン部の面積を変えることなく、ノイズ
に強い出力バッファが得られた。As described above, by optimizing the channel length, an output buffer that is resistant to noise was obtained without changing the depth or concentration of the impurity layer or the area of the drain part.
本発明はPN接合アバランシェ降伏またはパンチスルー
によりノイズを逃がすことにより出力バッファの大きさ
を変えずに静電耐圧の強くする効果がある。The present invention has the effect of increasing the electrostatic breakdown voltage without changing the size of the output buffer by releasing noise through PN junction avalanche breakdown or punch-through.
第1図は本発明の実施例であるMOSトランジスタのド
レインに電流を注入した時の永久破壊電流とチャネル長
である。
以上FIG. 1 shows the permanent breakdown current and channel length when a current is injected into the drain of a MOS transistor according to an embodiment of the present invention. that's all
Claims (1)
ル長を制御することによるPN接合のアバランシェ降伏
あるいはパンチスルーで決まっているMOSトランジス
タを使用していることを特徴とする出力バッファ回路。An output buffer circuit characterized in that it uses a MOS transistor whose source-drain breakdown voltage is determined by avalanche breakdown or punch-through of a PN junction by controlling the channel length.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22966190A JPH04111359A (en) | 1990-08-30 | 1990-08-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22966190A JPH04111359A (en) | 1990-08-30 | 1990-08-30 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04111359A true JPH04111359A (en) | 1992-04-13 |
Family
ID=16895699
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22966190A Pending JPH04111359A (en) | 1990-08-30 | 1990-08-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04111359A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6359313B1 (en) * | 1998-05-18 | 2002-03-19 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection transistor for a semiconductor chip |
-
1990
- 1990-08-30 JP JP22966190A patent/JPH04111359A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6359313B1 (en) * | 1998-05-18 | 2002-03-19 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection transistor for a semiconductor chip |
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