JPH0410787B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives character and graphic information signals, which are digital signals that are multiplexed with television signals and is transmitted, stores them in a memory in a predetermined order, reads them out, and transmits them to a fixed-frame computer such as a cathode ray tube. The present invention relates to a device for displaying character and graphic information on a display means, and provides a device that can display received characters and graphics in a stable state.

So-called text multiplex broadcasting is being considered as a method of multiplexing and transmitting information such as text and graphics in addition to the main image using television signals, and in March 1981, the 4th Radio Technology Council The subcommittee submitted a report on basic standards. Figure 1 shows the transmission method of the character/graphic information signal.
Any horizontal scanning period of the 21st H (and 273rd to 283rd H) (here, the 20th and 283rd H)
283rd H), a 296-bit character/graphic information signal per 1H is multiplexed. This multiplexed signal consists of a 48-bit (6-byte) header part and a 248-bit (31-byte) information data part, as shown in b, and the first 16 bits of the header part are used as a clock signal for reproducing the sampling clock. Cran-in (CR) signal, next 8
The bit is a framing code (FC) signal of a specific code for bit synchronization, and the remaining 24 bits are a service/interrupt signal and a data identification signal. A page control signal, color code signal, pattern data signal, program index signal, etc. are selected and transmitted to the information data section.

Therefore, in a receiving device that receives a television signal in which such character and graphic information signals are multiplexed and displays character and graphic information, it is necessary to have a memory with the storage capacity necessary to display the information image. , extracts the text and graphic information signals of a desired information program from the received television signal, writes the pattern data signals, etc. in a memory in a predetermined order and stores them, while synchronizing them with the screen scanning of a display means such as a cathode ray tube. By reading out the information from the memory and adding it to the display means, character and graphic information is displayed on the screen.

However, in such a receiving device, in order to receive and accurately and stably display the character/graphic information signal multiplexed with the television signal, the clock pulses used to read the signal from the memory must be accurately set during display. must occur.

Therefore, an object of the present invention is to provide a device that can stably and accurately generate such a read clock from a memory and can provide stable display. Embodiments will be described in detail with reference to drawings showing examples.

FIG. 2 is a block diagram of a teletext receiver in which the present invention may be implemented. 1 is a tuner, 2 is a VIF circuit. 3 is a detection circuit, 4 is a video processing circuit for chroma signals and video signals, and 6 is a display circuit.
CRT, 7 is a sync separation circuit, 8 is a horizontal AFC oscillation circuit, 9 is a color subcarrier (FSC) regeneration circuit,
These circuits are similar to those in a normal color television receiver. 5 is a mixing/switching circuit for character signals and video signals; 10 is a slicing circuit for shaping the character/graphic information signal in the video detection output signal into a binary signal; 11 is a write circuit for writing data signals into the memory 14; 12 is a memory 14 that generates a built-in clock.
A circuit 13 controls writing to and reading from the memory 14, and 13 is a circuit for generating a read clock when reading data signals for display. Reference numeral 14 comprises a pattern memory for a screen of character and graphic information to be displayed in the memory. These circuits 5, 10-1
The part 4 is also known as a so-called teletext receiver.

Now, in such a receiving/display device, when the input electric field is weak, the synchronization of the deflection system of the TV's CRT6 is disrupted and the screen shakes, so in order to reduce the shake of displayed characters on the screen, horizontal AFC and It is desirable to control a gated oscillator using the output of the oscillator circuit 8 to create a clock for display readout to reduce the fluctuation of characters, but as a gated oscillator,
If an astable multivibrator with a TTL configuration is used, temperature and aging changes will increase, so it is not practical as it is.

Therefore, in the present invention, the astable multivibrator is controlled by a PLL circuit, the position of the character on the screen is synchronized with the flyback pulse, and the frequency that determines the width of the character is stabilized by the PLL circuit. It is something.

In FIG. 4, _φ1 is a vertical synchronizing signal, _φ2 is a horizontal synchronizing signal, and _φ4 is a horizontal readout clock, which is the output of the NAND gate 30 in FIG. φ ₂ ' is a horizontal synchronizing pulse synchronized with the flyback pulse, and a horizontal display period control pulse φ ₅ is formed from this φ ₂ '. According to the Japanese teletext broadcasting standard, the information transmission rate is 8/5fsc and the writing clock is 8/5fsc, and its phase is determined by the clock line in ( CR) signal, and frame synchronization is applied using a framing code (FC) signal.
This 8/5fsc clock has the same phase with the horizontal synchronization signal for every H and every field, so
If this is also used for reading, and the frequency divider for generating the write clock is synchronously controlled and divided by the horizontal pulse φ ₂ ' only during the horizontal scanning period in which the read clock φ ₄ is generated, the read clock can be used at the time of reading. A comparison pulse for the PLL circuit to be created can be obtained. This is the output of the frequency multiplying/dividing circuit 15 in FIG.

On the other hand, the portions 30 to 39 are a well-known gated oscillator in which fine adjustment means using a variable capacitance diode 37 is introduced, and capacitors 35, 36,
If 37 is combined into a small capacitance (for frequency determination) and resistors 38 and 39 are omitted, a generally known oscillation circuit configuration is obtained. 41 is a buffer amplifier, and 16 is a phase comparator for configuring the PLL circuit.

Further, portions 26 to 29 constitute a double constant low-pass filter circuit. This low-pass filter has a configuration similar to that used in conventional horizontal AFC circuits and color subcarrier AFPC circuits, with a resistor of 26
and capacitor 27 determine τ ₁ in FIG. 5, resistor 28 and capacitor 27 determine τ ₂ , resistor 28 and capacitor 29 determine τ ₃ , and the response between τ ₂ and τ ₃ is determined by resistor 26 and τ 3. It is determined by the ratio of 28. Since the phase comparison of the readout clock pulse is performed at 8/5 fsc (5.73 MHz) as described above, it is sufficient to select τ ₃ to be about 1 KHz, for example.
Note that although the resistor 28 and capacitor 28 may be omitted, it is better to insert one having an appropriate value in terms of noise resistance characteristics.

Considering the overall operation of the circuit shown in Fig. 3, including this low-pass filter circuit, a PLL circuit is formed, and as will be described later, the period in which one comparison pulse for phase comparison exists, that is, the gated If the period in which the oscillator output is present is the majority of the entire period, the device will operate stably.

Therefore, the output of this low-pass filter circuit is applied as a control voltage to the variable capacitance diode 37 via the buffer amplifier 40 and the high resistance 39. 38 is a high resistance for reverse bias. The variable capacitance diode 39 has a variable capacitance.

The gate pulse forming circuit 42 forms the horizontal display period control pulse φ ₅ as described above from the horizontal pulse φ ₂ output from the horizontal AFC oscillation circuit 8, and controls the vertical display period from the vertical synchronization signal φ ₁ from the synchronization separation circuit 7. Form a pulse φ ₃ , and by the conjunction of φ ₃ and φ ₅
Gate the NAND gate 31.

As described above, according to this circuit, the oscillation frequency of the gated oscillator can be accurately adjusted to 8/5fsc by the PLL circuit.

Next, to add some information about the 8/5fsc multiplier/divider circuit 15, in Fig. 6, 43 converts the fsc output to 8/5fsc.
44 is a circuit for frequency-dividing its output by 1/5; 45 is a flip-flop that detects a framing code signal from the output signal of the slice circuit 10 and is set by the detection output; cleared. During this time, since the Q output of the FF 45 is at a high level, the output of the AND gate 46 also becomes a high level, the frequency divider 44 operates, the write clock for the memory 14 is output, and the AND gate 48 becomes conductive. Therefore, it is supplied to the write clock generation circuit 11.

Note that the FF 45 is set each time the FC signal is detected, that is, in each horizontal period in which the character/graphic information signal is superimposed. In Japan, it is supposed to be superimposed on the 10th to 21st H, but in anticipation of an error of 1 H,
The FF 47 is set from the beginning of the 9th H to the end of the 22nd H, and during this period, its output is set to a low level, the AND gate 49 is cut off, and the comparison pulse is not supplied to the phase comparator 16. 9th H,
The 22nd H pulse can be easily formed using a counter from the synchronous separation output.

In addition, _the gate signal for extracting the output of the gated oscillator may be gated with the logical sum signal of pulses φ ₅ and φ ₃ in FIG. If you gate with the OR signal of φ ₅ ′ (φ ₂ ′ or narrower) and φ ₃ and lengthen the comparison period in the phase comparator 16 (in other words, shorten the period where no comparison is possible) Operation becomes more stable. As an example, φ ₅ ' is formed in the delay circuit 50 in FIG.
The NAND gate 51 creates an inverted output of the AND with φ ₃ and supplies it to the NAND gate 31 . in this case,
It is sufficient to count the output of the NAND gate 30 or buffer amplifier 41, gate only the display clock with a gate circuit, and supply it to the memory 14.

As described above, in the character and graphic information display device of the present invention, a gated oscillator is used to generate the clock for reading display data from the memory, and PLL control is applied to this clock. Also, there is no frequency change due to changes in the elements and capacitance of the TLL circuit, and stable and accurate display can be performed. Also, 1/
The 5 frequency divider can be used for both writing and reading clocks.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram showing the mode of transmission of a text/graphic information signal, FIG. 2 is a basic block diagram of a text broadcasting receiver, and FIGS. 3 and 6 are a diagram of a text/graphic information display device according to an embodiment of the present invention. Main part circuit diagram, 4th
5 and 5 are waveform diagrams and characteristic diagrams for explaining the operation. 7... Synchronization separation circuit, 8... Horizontal AFC oscillation circuit, 9... FSC regeneration circuit, 10... Slice circuit,
11...Write clock generation circuit, 12...Write/
Read processing control circuit, 13...Read clock generation circuit, 14...Memory, 15...8/5fsc multiplication frequency division circuit, 16...Phase comparator, 26, 28...Resistor,
27, 29... Capacitor, 30, 31...
NAND gate, 40, 41... Patshua amplifier,
42... Gate pulse forming circuit, 37... Variable capacitance diode.

Claims (1)

[Claims] 1. Receive text and graphic information signals that are multiplexed and transmitted during the vertical retrace period of a television signal, store them in a memory, and display text and graphic information on the television screen based on the data signals read from the memory. In a display device, a gated oscillator for forming a memory read clock whose oscillation period is controlled by pulses including horizontal and vertical display periods created based on horizontal pulses and vertical pulses output from a horizontal AFC oscillator circuit is used. and a comparison signal synchronized with the color subcarrier and the horizontal synchronization signal during a period other than the entire period in which character and graphic information is superimposed during the vertical retrace period of the television signal or before and after the period, and the gated oscillator. The oscillation output of the gated oscillator is applied to a phase comparison circuit, and the oscillation output of the gated oscillator and the phase comparison output of the comparison signal are supplied to a frequency control element of the gated oscillator via a low-pass filter. to configure a PLL circuit, and set the oscillation start phase of the gated oscillator to the horizontal
A character and graphic information display device controlled by horizontal pulses synchronized with the output of an AFC oscillation circuit.