JPS6151469B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives character and graphic information signals, which are digital signals that are multiplexed with television signals and is transmitted, stores them in a memory in a predetermined order, reads them out, and transmits them in a scanning format such as a cathode ray tube. The present invention relates to a device for displaying character and graphic information on a display means, and provides a device that can display received characters and graphics in a stable state.

So-called text multiplex broadcasting is being considered as a method of multiplexing and transmitting information such as text and graphics in addition to the main image using television signals, and in March 1981, the 4th Radio Technology Council The subcommittee submitted a report on basic standards. Figure 1 shows the transmission method of the character/graphic information signal.
Any horizontal scanning period of the 21st H (and 273rd to 283rd H) (here, the 20th and 283rd H)
283rd H), a 296-bit character/graphic information signal per 1H is multiplexed. This multiplexed signal consists of a 48-bit (6-byte) header part and a 248-bit (31-byte) information data part, as shown in b, and the first 16 bits of the header part are used as a clock signal for reproducing the sampling clock. The crank-in CR signal, the next 8 bits are a framing code EC signal of a specific code for bit synchronization, and the remaining 24 bits are a service identification interrupt signal and a data identification signal. In the information data section, page control signals, color code signals, pattern data signals, program index signals, etc. are selected and transmitted.

Therefore, in a receiving device that receives a television signal in which such character and graphic information signals are multiplexed and displays character and graphic information, it is necessary to have a memory with the storage capacity necessary to display the information image. , extracts the text and graphic information signals of the desired information program from the received television signal, writes the pattern data signals, etc. in a memory in a predetermined order and stores them, while synchronizing them with the screen scanning of the display means of the cathode ray tube. By reading out the information from the memory and adding it to the display means, character and graphic information is displayed on the screen.

However, in such a receiving device, in order to receive and accurately and stably display the character/graphic information signal multiplexed with the television signal, the clock pulses used to read the signal from the memory must be accurately set during display. must occur.

Therefore, an object of the present invention is to provide a device that can stably and accurately generate such a memory read clock and provide stable display. A detailed explanation will be given with reference to the drawings showing examples.

FIG. 2 is a block diagram of a teletext receiver in which the present invention may be implemented. 1 is a tuner, 2 is a VIF circuit, 3 is a detection circuit, 4 is a video processing circuit for chroma signals and video signals, and 6 is a display circuit.
CRT, 7 is a sync separation circuit, 8 is a horizontal AFC oscillation circuit, and 9 is a color subcarrier f _SC reproducing circuit, which are similar to the circuits of a normal color television receiver. 5 is a mixing/switching circuit for a character signal and a video signal; 10 is a slicing circuit for shaping a character/figure information signal in a video detection output signal into a binary signal; 11
1 is a write clock generation circuit for writing data signals to the memory 14; 12 is a circuit for controlling writing to and reading from the memory 14;
Reference numeral 3 denotes a read clock generating circuit when reading data signals for display. 14 is memory,
It consists of a pattern memory for one screen of character and graphic information to be displayed. These circuits 5, 10 to 14 are also known as a so-called teletext receiver.

Now, in such a receiving/display device, when the input electric field is weak, the synchronization of the deflection system of the TV's CRT6 is disrupted and the screen shakes, so in order to reduce the shake of displayed characters on the screen, horizontal AFC and It is desirable to control a gated oscillator using the output of the oscillator circuit 8 to create a clock for display readout to reduce the fluctuation of characters, but if an astable multivibrator with a TTL configuration is used as the gated oscillator, temperature and aging Since the changes would be large, it would be impractical to leave it as is.

Therefore, in the present invention, the astable multivibrator is controlled by a PLL circuit, and the position of the characters on the screen is synchronized with the flyback pulse.
The frequency that determines the width of the characters is stabilized using a PLL circuit.

In FIG. 4, _φ1 is a vertical synchronizing signal, _φ2 is a horizontal periodic signal, and _φ4 is a horizontal readout clock, which is the output of the NAND gate 30 in FIG. φ ₂ ' is a horizontal periodic pulse synchronized with the flyback pulse, and a horizontal display period control pulse φ ₅ is formed from this φ ₂ '. According to the Japanese teletext broadcasting standard, the information transmission rate is 8/5f _SC , and the writing clock is 8/5f _SC , and its phase is the same as the clock run in the text/graphic information signal during writing. (CR) signal, and frame synchronization is applied using a framing code (FC) signal. Since this 8/5f _SC clock is at the same position relative to the horizontal synchronizing signal for every H and every field, it can also be used for reading, and only during the horizontal scanning period when the readout clock _φ4 is generated. , a comparison pulse for the PLL circuit can be obtained by synchronously controlling and dividing the frequency divider for generating the write clock using the horizontal pulse φ ₂ '. This is the output of the frequency multiplying/dividing circuit 15 in FIG.

On the other hand, the portions 30 to 39 are a well-known gated oscillator in which a fine adjustment means using a variable cap 37 is introduced.
If 8 and 39 are omitted, it is a generally known oscillation circuit configuration, and the capacitor 34 may be replaced with a resistor. 41 is a buffer amplifier, 16
is a phase comparator for configuring a PLL circuit.

In addition, parts 17 to 29 constitute a sample and hold circuit, and include FET 26 and resistor 2.
It will work even if 8 and 29 are omitted. 17 is a buffer amplifier, which converts the output voltage of the phase comparator 16 into
Inform FET18. FET18 and FET26 are switching FETs for sample and hold, and FET1
8 is the display period control pulse φ ₅ (horizontal direction) and φ ₃ vertical direction in FIG. 4, which are cut off during the display period, and during other periods, that is, during the period when data is read from the memory 14 and displayed, the gate electrode is The level becomes high, the FET 18 becomes conductive, and the output of the buffer amplifier 17 is stored in the capacitor 19. When the gated oscillator stops oscillating, FET 18 is cut off and the charge in capacitor 19 is held.

20 is a buffer amplifier, and 21 and 22 are resistors that determine the amount of feedback. Also, 27 is an inverter,
While FET18 is cut off, FET26 is conductive, and the output of buffer amplifier 17 is
It is returned via 9. Low resistors 28' and 28 are resistors that determine the gains of buffer amplifiers 17 to 20. Of course, the configuration of the sample and hold circuit is not limited to this.

23 is a buffer amplifier, whose output is connected to a resistor 24
and is integrated and smoothed by a capacitor 25. That is, 17
~23 circuit, when the oscillation output of the NAND gate 30 is continuous, the voltage obtained is almost the same as the voltage compared to the output of the 8/5f _SC multiplier divider circuit 15,
A PLL circuit is formed. That is, the sample-and-hold circuit allows the same handling as comparison of continuous signals.

The integrated output voltage is applied as a control voltage to the variable cap 37 via the buffer amplifier 40 and the high resistance 39. 38 is a high resistance for reverse bias. Varicap 37 has a variable capacitance.

In the gate pulse forming circuit 42, the horizontal AFC
The display period control pulse _φ5 is formed from the output of the oscillation circuit 8 as described above, the display period control pulse _φ3 is formed from the synchronization signal from the synchronization separation circuit 7, and the logical sum of _φ3 and _φ5 is used to generate the NAND gate. 31 and FET1
8 and the inverted output of the logical sum of φ ₃ and φ ₅ .
Gates FET26.

As described above, according to this circuit, the oscillation frequency of the gated oscillator can be accurately adjusted to 8/5 of f _SC using the PLL circuit.

Next, to add some information about the 8/5f _SC multiplier frequency divider circuit 15, in FIG _. is a flip-flop which detects a framing code signal from the output signal of the slice circuit 10, is set by the detected output, and is cleared by the next horizontal period pulse. Meanwhile, FF45 Q
Since the output is at a high level, the output of the OR gate 46 is also at a high level, the frequency divider 44 operates, and the write clock for the memory 14 is output, and the AND gate 48 is conductive, so the write operation is performed. The signal is supplied to the internal clock generation circuit 11.

In addition, FF45 is used for convenience of FC signal detection, that is,
It is set during the horizontal period when the character/graphic information signal is superimposed. In Japan, it is supposed to be superimposed on the 10th to 21st H, but in anticipation of an error of 1H, FF47 is set from the beginning of the 9th H to the end of the 22nd H, and during this time its Q output is is set to a low level, the AND gate 49 is cut off, and no comparison pulse is supplied to the phase comparator 16.
The 9th H and 22nd H pulses can be easily formed using a counter from the synchronous separation output.

As described above, in the character and graphic information display device of the present invention, a gated oscillator is used to generate the clock for reading display data from the memory, and this is subjected to PLL control. However, there is no frequency change due to changes in the elements and capacitance of the TTL circuit, and stable and accurate display can be achieved. Also,
The 1/5 frequency divider can be used both for writing and for reading clocks.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram showing the mode of transmission of text and graphics information signals, FIG. 2 is a basic block diagram of a text broadcasting receiver, and FIG. 5 in FIG. A circuit diagram of the main part, and FIG. 4 is a waveform diagram for explaining its operation. 7...Synchronization separation circuit, 8...Horizontal AFC oscillation circuit, 9...f _SC regeneration circuit, 10...Slice circuit, 11...Write clock generation circuit, 12...Write/read processing control circuit, 13... ...Read clock generation circuit, 14...Memory, 15...8/5f _SC multiplication/divider circuit, 16...Phase comparator, 17, 20, 23
...Battle amplifier, 18,26...FET, 1
9...Capacitor, 24...Resistor, 25...Capacitor, 30,31...NAND gate, 35,3
6...Capacitor, 37...Varicap, 3
8, 39...Resistor, 40, 41...Buffer amplifier, 42...Gate pulse forming circuit.

Claims (1)

[Claims] 1. A gated gate whose horizontal period of oscillation is controlled by a horizontal periodic pulse, and which is synchronized with the vertical scanning of the television screen and stops oscillation at the top and bottom edges of the screen for the entire horizontal scanning period. An oscillator is provided, a variable impedance element is provided to control the oscillation frequency, and the output obtained by dividing the oscillation frequency and the color subcarrier or its multiplication or frequency division output are compared only during the oscillation period of the oscillator, and the output is calculated. A PLL circuit is formed by providing a sample and hold circuit before supplying the signal to the low frequency converter and separating the comparator circuit and the low frequency converter during the oscillation stop period, and using the output of the oscillation circuit. , a character and graphic information display device characterized in that character and graphic information read out from a memory is displayed on a television screen. 2. Comparing the horizontal periodic pulse obtained by dividing the oscillation output with the horizontal pulse synchronized with the horizontal periodic signal of the television signal, and sampling and holding only at the upper and lower ends of the screen. The text and graphic information display device according to scope 1.