JPH04107830A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To be able to control the density profile without inconsistency, reduce the overall resistance of the gate electrode, and achieve high operating speeds even with finer device features by placing a #1 gate electrode layer on a semi conductor substrate, implanting ions into the semiconductor substrate through the #1 gate electrode layer, and forming a low density source-drain diffusion layer. CONSTITUTION:A field oxide film 2 is formed on a p-type silicon substrate 1 and a gate oxide film 3 is formed using the thermal oxidation method. After this, a polycrystalline silicon film 4 is deposited using an SiH4 base gas, doping is performed, and low resistance achieved. Next, a silicon oxide film 5 is formed and etching is used to expose the polycrystalline silicon film 4. A high melting point metal film 6 is formed and this is used as a mask to implant phosphorus ions through the polycrystalline silicon film 4, forming the low density source- drain diffusion layer 7. Since the #1 gate electrode layer is formed through adhesion, film thickness uniformity can be easily controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a field effect transistor having a try-doped-drain (LDD) structure.

[Conventional technology]

Conventionally, as a manufacturing method for this type of semiconductor device, there are, for example, the following manufacturing methods (IED, Technical Digest, pp. 742-745, 198
Year 6 (I EDM, Tech, Digest.

1', 742-745)).

First, as shown in FIG. 3(a), a field oxide film 2 for element isolation is formed on a P-type silicon substrate 1 by selective oxidation, and then a gate oxide film 3. Polycrystalline silicon films 4 are sequentially formed.

Next, polycrystalline silicon film 4 is etched by anisotropic etching using photoresist pattern 13 as a mask.

At this time, the polycrystalline silicon film 4 is not entirely etched, but only a certain thickness remains. Subsequently, phosphorus ions are implanted through the remaining polycrystalline silicon film 4 to form a low concentration source/drain diffusion layer 7. The reason why a certain thickness of the polycrystalline silicon film 4 is left in this manner is to form an inverted T-shaped gate electrode 41 (see FIG. 3(b)) later.

Next, as shown in FIG. 3(b), the silicon oxide film deposited over the entire surface is etched back by anisotropic etching to form sidewalls 8. Next, the remaining portion of the polycrystalline silicon film 4 is etched using the sidewall 8 as a mask to form an inverted T-shaped gate electrode earthwork.
Using the inverted T-shaped gate electrode soil 1 and sidewalls 8 as masks, arsenic (As) ions are implanted to form highly concentrated source/drain diffusion layers 9. The inverted T-shaped gate electrode 41 is formed in this way because high-energy electrons (hot electrons) generated near the low-concentration drain jump into the sidewall and are trapped, causing the low-concentration diffusion layer to become depleted. This is to prevent this from occurring by providing a gate electrode on the low concentration diffusion layer, and to prevent a decrease in the conductance of the transistor.

A hole is opened and an aluminum wiring 11 is formed.

In this manufacturing method, the width of the sidewall 8 controls the overlap dimension between the inverted T-shaped gate electrode earthwork and the low concentration source/drain diffusion layer 7.

2. Problems to be Solved by the Invention] In this conventional semiconductor device manufacturing method, as shown in FIG. 3(a), the polycrystalline silicon film 4 is etched so that only a certain film thickness remains. However, it is difficult to control the thickness of the remaining film by etching, and it tends to become non-uniform within the wafer surface and between the wafers. This variation in film thickness directly affects the depth of the next ion implantation, causing variation in the concentration profile of the lightly doped source/drain diffusion layer, leading to increased variation in transistor characteristics. Atsu AsahiAlso, if only polycrystalline silicon is used as the gate electrode, there is a problem in that the resistance increases as the device becomes smaller and the operating speed becomes slower.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of depositing a first gate electrode layer on one main surface of a semiconductor substrate, and selectively forming a second gate electrode layer on the first electrode layer. process and
A step of forming a low concentration source/drain diffusion layer by implanting ions into one main surface of the semiconductor substrate through the first gate electrode layer using the second gate electrode layer as a mask; a step of forming a sidewall on the side surface of the semiconductor substrate, and a step of implanting ions into one main surface of the semiconductor substrate using the sidewall and the second gate electrode layer as a mask to form a highly concentrated source/drain diffusion layer. ing.

In the present invention, since the first gate electrode layer is formed by deposition rather than etching, the film thickness can be easily controlled and can be made uniform within the wafer surface and between wafers. Therefore, the impurity concentration and its profile of the low-concentration source/drain diffusion layer formed by ion implantation through the electrode layer become uniform within the wafer surface and between wafers, resulting in a transistor with uniform characteristics. can be manufactured. Note that this first gate electrode layer is preferably formed by chemical vapor deposition (CVD). Furthermore, although silicon, a high melting point metal, a silicide of a high melting point metal, etc. are used as the first gate electrode layer, polycrystalline silicon is preferably used because it causes less deterioration of the gate oxide film and is easy to process. It will be done.

Further, in the present invention, the second gate electrode layer is selectively formed after the first gate electrode layer is deposited.

Therefore, a material different from that of the first gate electrode layer can be used for the second gate electrode layer. For example, when polycrystalline silicon is used for the first gate electrode layer, a high melting point metal or its silicide is preferably used for the second gate electrode layer.

The semiconductor device to be formed is an insulated gate field effect transistor (MI) using a gate insulating film such as a silicon oxide film.
SFET), a gate insulating film is formed and then a first gate electrode layer is formed thereon. This insulating film is
It can be used as an etching stopper when removing the first gate electrode layer later.

Furthermore, if a protective film such as a silicon nitride film is formed on the upper surface of the second gate electrode layer, and the first gate electrode layer is etched using the protective film and the gate electrode covered with the sidewalls as a mask, the second gate electrode layer can be etched. The gate electrode layer is not etched and its thickness is not reduced. moreover,
If a silicon oxide film, silicon nitride film, etc. is used for the sidewall, even if a high melting point metal is used as the second gate electrode layer, the high melting point metal is covered by the sidewall and protective film, so the first gate The electrode layer is not etched when removed by etching. therefore,
The surface of the semiconductor substrate is not contaminated by this high melting point metal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views for explaining one embodiment of the present invention.

As shown in FIG. 1(a), on a P-type silicon substrate 1,
By selective oxidation method, the film thickness is 4000℃ at 950~1000℃.
A field oxide film 2 of ~8,000 thick is formed, and then a gate oxide film 3 of 50 to 300 thick is formed at 700 to 900[deg.] C. by thermal oxidation. Then, for example, Low
A polycrystalline silicon film 4 having a thickness of 500 to 2000 wafers is deposited by pressure CVD (LPCVD) at 600 to 650° C. using SiH as a source gas.

The polycrystalline silicon film 4 is doped with phosphorus (P) or arsenic (As) immediately after deposition, and has a layer resistance of 10 to 5007
Reduces resistance to the mouth. As a doping method, for example, an acceleration energy of 1 (1 to 40 KeV and an implantation amount of 10 to 15 to 1016 cm) which does not penetrate the polycrystalline silicon film 4 is used.
There is a method of performing ion implantation of -2.

Next, a silicon oxide film 5 with a thickness of 2,000 to 5,000 thick is formed using the CvD method, and the silicon oxide film 5 on the region that will become the channel of the MOSFET is etched using a photoresist pattern (not shown) as a mask. Polycrystalline silicon film 4 is exposed.

Next, as shown in FIG. 1(b), a high melting point metal film 6 such as tungsten is coated on the exposed polycrystalline silicon film 4 with a film thickness of 100%.
It is selectively formed with a film thickness of about 0 to 4,000. Here, as a method for forming this, for example, by a silane reduction method,
Tanksten hexafluoride (WFs) and silane (Si
There is a method of selectively growing tungsten at a temperature of 200 to 300°C using H4). Another method is to deposit a high melting point metal film over the entire surface and then etch back by anisotropic etching, leaving the high melting point metal film 6 only on the exposed polycrystalline silicon film 4.

Next, as shown in FIG. 1C, after removing the silicon oxide film 5 by wet etching, phosphorus (P) ions are implanted through the polycrystalline silicon film 4 using the high melting point metal film 6 as a mask. , a low concentration source/drain diffusion layer 7 is formed. Here, the ion implantation of phosphorus (P) is performed with an implantation energy of, for example, 50 to 50, depending on the thickness of the polycrystalline silicon film 4.
250KeV, implantation amount I Q 12~l Q Ifcm
- Perform under the condition of 2.

Next, as shown in Figure 1(d), 1000 to 30
A sidewall 8 is formed on the side surface of the high-melting point metal film 6 by depositing a silicon oxide film 4 of 0.00000000000000000000000000 and performing anisotropic etching thereon.

Next, as shown in FIG. 1(e), the polycrystalline silicon film 4 is anisotropically etched using the sidewall 8 and the high melting point metal film 6 as masks, and the polycrystalline silicon film 4' and the high melting point metal film 6 are etched. An inverted T-shaped gate electrode earthwork with a two-layer structure is formed. Subsequently, arsenic (As) ions are implanted using the inverted T-shaped gate electrode earthwork and sidewalls 8 as masks to form highly concentrated source/drain diffusion layers 9. Here, the arsenic ion implantation is performed at, for example, an implantation energy of 30 ~],
This is carried out under the conditions of 0 OKeV and an implantation amount of 1015 to 1016 cIn''''.

Finally, as shown in FIG. 1(f), an interlayer insulating film 10 is formed on the entire surface.
After forming contact holes at predetermined positions, aluminum wiring 11 is subsequently formed, and a semiconductor device is manufactured.

In this manufacturing method, since the polycrystalline silicon film 4 is formed in advance, the film thickness can be easily controlled, and variations in the concentration pull file of the low concentration source/drain diffusion layer 7 can be controlled. In addition, since a high melting point metal was used as the second gate electrode layer, the inverted T-shaped gate electrode earthwork was formed using a polycrystalline silicon film 4.
' and a high melting point metal film 6/\2 layer structure, and low resistance can be achieved.

FIGS. 2(a) to 2(e) are cross-sectional views for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention.

First, a field oxide film 2 for element isolation is formed on a P-type silicon substrate l according to the method explained using FIGS. 1(a) and 1(b), and then a gate oxide film 3 and a polycrystalline silicon film 4 are formed. Form sequentially. After reducing the resistance of the polycrystalline silicon film by ion implantation, a silicon oxide film 5 is formed,
A high melting point metal film 6 is selectively formed in the areas etched using the photoresist pattern as a mask. After that, as shown in FIG. 2(a), a thick silicon nitride film 2 is applied to the entire surface.
is deposited and formed.

Next, as shown in FIG. 2(b), the silicon nitride film 12 is etched back by anisotropic etching, leaving the silicon nitride film 12' only on the high melting point metal film 6.

Next, as shown in FIG. 2C, after removing the silicon oxide film 5 by wet etching, phosphor ( P) ion implantation is performed to form a low concentration source/drain diffusion layer 7. Then Figure 2(d)
As shown in FIG. 3, a sidewall 8 of silicon oxide is formed, and anisotropic etching is performed on the polycrystalline silicon film 4 using the silicon nitride film 12' and the sidewall 8 as a mask to separate the polycrystalline silicon film 4' and the refractory metal. An inverted T-shaped gate electrode layer 1 having a two-layer structure consisting of a film 6 is formed.

Finally, as shown in FIG. 2(e), first, a highly concentrated source/drain diffusion layer 9 is formed by ion implantation of arsenic (As), and then an interlayer insulating film 10 is formed in the same manner as in the first embodiment. Aluminum wiring 11 is formed.

In this embodiment, not only the sides of the high melting point metal film 6 are covered with the sidewalls 8, but also the top surface thereof is covered with the silicon nitride film 12', so that the polycrystalline silicon film 4 is anisotropically During etching, the high melting point metal film 6 is not etched. Therefore, the film thickness will not be reduced, and the low concentration source/drain diffusion layer 7 etc. will not be contaminated by the etched high melting point metal.

〔Effect of the invention〕

As explained above, in the present invention, in order to form an inverted T-shaped gate electrode, the first gate electrode layer is first deposited, and then the second gate electrode layer is selectively formed. The thickness of the first gate electrode layer can be easily controlled, and ions are implanted onto one main surface of the semiconductor substrate through the gate electrode layer of Apprentice 1 to form a low concentration source/drain diffusion layer. This has the effect that the concentration profile of implanted ions in the low concentration source/drain diffusion layer can be controlled without variation.

Further, in the present invention, since the inverted T-shaped gate electrode is formed separately into the first gate electrode layer and the second gate electrode layer, the electrode can easily have a two-layer structure, and the second gate electrode layer can be easily formed into a two-layer structure. A different material from the first gate electrode layer can be used for the electrode layer. Therefore, even if a relatively high resistivity material such as polycrystalline silicon is used for the first gate electrode layer, by using a high melting point metal or the like for the second gate electrode, the gate electrode as a whole can be The resistance can be lowered, and even if the device is miniaturized, high-speed operation is possible. Furthermore, by forming a protective film on the second gate electrode layer before etching the first gate electrode layer using the second gate electrode layer and the sidewall as a mask, the first gate electrode layer can be anisotropically etched. When sexually etching,
This has the effect of preventing the second gate electrode layer from being thinned and contaminating the diffusion layer by ions etched during the thinning.

Point metal film, 7...Low concentration source/drain diffusion layer, 8...Side wall, 9...High concentration source/drain diffusion layer, 10...・Interlayer insulating film, 11... Aluminum wiring, 12.12
'...Silicon nitride film, 13...Photoresist, 41...Inverted T-shaped gate electrode.

Agent: Patent Attorney Susumu Uchihara

[Brief explanation of drawings]

Figures 1(a) to (') are cross-sectional views showing each manufacturing process in one embodiment of the present invention, and Figures 2(a) to (e) are sectional views showing each manufacturing process in another embodiment of the present invention. The cross-sectional views shown in FIGS. 3(a) to 3(c) are cross-sectional views showing each manufacturing process in the conventional example. 1... P-type silicon substrate, 2... Field oxide film , 3... Kate oxide film, 4,4'.
... Polycrystalline silicon film, 5 ... Silicon oxide film, 6 .... ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Pion 41 Inverted T-shaped Geto electric dust Figure 3

Claims (3)

[Claims] (1) A step of depositing a first gate electrode layer on one main surface of a semiconductor substrate; a step of selectively forming a second gate electrode layer on the first gate electrode layer; using the second gate electrode layer as a mask, implanting ions into one main surface of the semiconductor substrate through the first gate electrode layer to form a low concentration first source/drain diffusion layer; ,
forming a sidewall on the side surface of the second electrode layer; and implanting ions into one main surface of the semiconductor substrate using the sidewall and the second gate electrode layer as a mask to form a highly concentrated second source. - A method for manufacturing a semiconductor device, comprising a step of forming a drain diffusion layer. (2) The method of manufacturing a semiconductor device according to claim 1, wherein a polycrystalline silicon layer is used as the first gate electrode layer, and a high melting point metal layer is used as the second gate electrode layer. (3) The method further comprises the steps of forming a protective film on the second gate electrode layer, and then etching the first gate electrode layer using the protective film and the sidewalls as a mask. 2. The method of manufacturing a semiconductor device according to claim 1.