JPH04106586A - Display control circuit - Google Patents

Abstract

PURPOSE:To shorten the time required for a display process by outputting other-directional address to a display means by an other-directional address output means and also outputting select signals for respective one-directional address output means and address data to the selected one-directional address output means when a control means inputs address data on a display area to the other-directional address output means. CONSTITUTION:A CPU 12 outputs virtual address data AD. A common driving circuit 1 outputs select signals CE1 - CE8 and real addresses AX of selected segment driving circuit 17-i (i=1 - 8) are outputted. When writing to a display area E1 whose most significant digit bit address is (40,70) is performed, the CPU 12 outputs the virtual address (40,70) to the common driving circuit 1. The X-directional component of the virtual address AD is 70 and the select signal CE1 is outputted; and the driving circuit 17-1 is selected and writes the display area E1 from the real address (40,70).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display control circuit that controls the display of a display device such as a liquid crystal display device.

In a liquid crystal display device, etc., which is constructed by interposing a liquid crystal layer between a common electrode and a segment electrode formed on a pair of transparent substrates, addresses are set in a matrix on the display area, and each address is displayed. Control takes place. A display device in which such a display area is set is connected to a column direction address output circuit that outputs address data in the column direction and a row direction address output circuit that outputs address data in the row direction. When the display area of this liquid crystal display device increases in size, for example in the row direction, a plurality of row direction address output circuits are used to perform display control for each predetermined address range. These row-direction address output circuits and column-direction address output circuits are connected to a CPU (central processing circuit) including a microprocessor and the like, and are supplied with address data, display data, and the like.

Problems to be Solved by the Invention In such a large liquid crystal display device, the CPU selects one of the plurality of row direction address output circuits according to the virtual address on the display in the display area, and outputs the selected row direction address. It was designed to output real address data within the control range of the output circuit. Moreover, such processing is performed by software via the CPU. Conventionally, it is necessary to perform such software processing for each address in the display area. Therefore, in the past, display processing required a large amount of time, and especially in the case of portable battery-powered data processing devices, it was difficult to supply the relatively large amount of power consumption necessary for high-speed CPU operation. The problems were obvious.

An object of the present invention is to provide a display control circuit that solves the above-mentioned technical problems and achieves high-speed display operation.

Means for Solving the Problems The present invention provides a plurality of one-way addresses connected to a display means in which addresses are set in a matrix in a display area and displayed, and outputs one-way address data for each predetermined address range. an output means, and a second direction connected to the display means and outputting second direction address data, a selection signal for each one direction address output means, and an address data output to the selected one direction address output means. A display control circuit characterized in that it includes an address output means and a control means for outputting address data of a display area to the other direction address output means.

According to the present invention, when displaying on a display means in which addresses are set in a matrix in a display area, one-way address data is output for each predetermined address range by a plurality of one-way address output means. . Further, the control means inputs the address data of the display area to the other direction address output means. The other direction address output means outputs the other direction address data to the display means, and
A selection signal for each one-way address output means and address data to the selected one-way address output means are output.

Therefore, compared to the case where such address processing is performed as software processing by the CPU, the time required for display processing can be shortened, and high-speed processing can be realized in display operation ftE.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, the second factor is a block diagram of a data processing device 2 in which the common drive circuit 1 is used, and FIG.
FIG. This data processing device 2 is so-called a notebook size, and a first operating section 3 and a second operating section 4 are configured to be openable and closable at a connecting section 5. The second operation section 4 includes a cursor key 6, a function setting key 7, a character entry key 8, a number entry key 9, and the like. On the other hand, so-called transparent touch keys 10 and a liquid crystal display device 11 are arranged in the first operation section 3 .

Such a data processing device '2 is equipped with a CPU (central processing circuit) 12 including, for example, a microprocessor.
A RAM (random access memory) 13 is connected to each key manual means of the 0 and second operation unit 4, and is used as a storage area for various input data and a working area for data during operation, and a RAM (random access memory) 13 for controlling the control operation of the CPU 12. A ROM (read only memory) 14 is connected to which is stored a program that defines the font, display font data, calendar data, and the like.

A clock port n15 for timekeeping, a common drive circuit 1 that controls the display operation of the liquid crystal display device 11 as described later, and a liquid crystal power supply potential supplied to the common drive circuit 1 is changed based on a contrast signal from the common drive circuit 1. , also CPU12
A liquid crystal power supply circuit 16 whose operating state/stop state is switched by a control signal fμ from the controller is connected. A plurality of (eight in this embodiment) segment drive circuits 17 are connected to the common drive circuit 1 and control the display state of the liquid crystal display device 11 together with the common drive circuit 1. Liquid crystal display device 1
1 has a common electrode 11 on a pair of transparent substrates 11a and llb.
c. Form a segment electrode lid, and place liquid crystal N between them.
11e.

A block diagram of the common drive circuit 1 is shown in FIG. The common drive circuit 1 is supplied with a write/read control signal R/W, a clock signal φ, a busy signal BY, a chip enable signal CE, etc. from the CPU 12, and also has a control circuit 19 supplied with address data AD, display data DI, etc. Equipped with Of these, the display data DI is input via the buffer 20. Further, the common drive circuit 1 outputs a frame signal PR, a control signal DIS for controlling ON10FF of display by the segment electrodes, and a clock signal LCK to the segment drive circuit 17. As described above, such a data processing device 2 is portable and has the size of a notebook, and various reference voltages necessary for the operation of the data processing device 2 are generated by a power supply circuit 26 connected to a battery 25.

A data processing circuit 21 is connected to the control circuit 19, and the CP
Logical operations (SET, AND, OR,
After performing OR, etc.), the data is sent to the segment drive circuit 17. The memory control circuit 22 assigns the address data sent from the CPtJ12 to which segment drive port W@
17, and generates a relative address in any of the selected segment drive circuits 17.

The timing generation circuit 23 generates clock signals and the like used for various calculation processes in the common drive circuit 1.
A reference clock signal from an oscillator 24 is provided.

The common signal control circuit 27 and the common side decoder 28 use the clock signal generated by the timing generation circuit 23 to generate a common signal to be supplied to the common electrode of the liquid crystal display device 11. Further, a window processing circuit 29 having a configuration and operation as described later is connected to the control circuit 19, and a contrast adjustment circuit 46 stores the density displayed on the liquid crystal display device 11, and the density data is set by the CPU 12. . Contrast adjustment of the liquid crystal display device 11 is performed by the liquid crystal power supply circuit 16 shown in FIG. 2 based on density data in the contrast adjustment circuit 46, and the liquid crystal power supply potential from the liquid crystal power supply circuit 16 is taken into the common drive circuit 1 A liquid crystal voltage input section 17 is provided for this purpose.

FIG. 4 is a circuit diagram illustrating a wiring portion of a configuration related to the liquid crystal display device 11. As shown in FIG. An 8-bit data bus 81, a 6-bit address bus 82, and a control line 83 to which a selection signal CE for selecting the common drive circuit 1 is output are provided between the CPIJ 12 and the common drive circuit 1.

Common drive circuit 1 and each segment drive circuit 17-1 to 1
7-8, each segment drive circuit 17-1 to 1
78 and each segment drive circuit 17-
Selection signal CEI for selecting any one of 1 to 17-8
- 8 control lines 84 to which CE8 are respectively output, an 8-bit data bus 85, an address bus 86 that supplies 8-bit address data AY in the Y direction in the liquid crystal display device 11, and 4-bit address data AY in the X direction. An address bus 87 that supplies address data AX is connected.

In the liquid crystal display device 11 of this embodiment, the address of the upper left corner is <0.
．． A virtual address space is established having virtual addresses from O) to the lower right corner address (146°895).

On the other hand, each segment drive circuit 17-1 to 17-8 is provided for each predetermined address width (eg, 112 bits) along the row direction of the liquid crystal display device 11. In other words, the segment drive circuit 17-1 has a row direction address range of 0.
~111, and the segment drive circuit 17-2 shares the row direction address range 112 to 223. Similarly, the segment drive circuit 17-8 shares the row direction address range 7.
84-895 will be shared.

Furthermore, in this embodiment, when writing display data to the liquid crystal display device 11, in the case of horizontal writing, the data is written in an 8-bit range continuous in the row direction from the writing start address, as shown in area E1 in FIG. It will be done. Therefore, the common drive circuit 1 of this embodiment, which outputs the virtual address data AD in this virtual space as the address data AD from the CPU 12, based on this virtual address data AD,
The selection signals CEI to CE8 and the real address A in the selected segment drive circuit B17-i (i=1 to 8)
It outputs X. In this embodiment, each of the segment drive circuits 17-1 to 17-8 has 1 to 11 segments in the X direction.
It has a real address range of 2.

FIG. 5 is a diagram showing the configuration of the segment drive circuit 17. Each of the segment drive circuits 17-1 to 17-8 includes a RAM 68, and the address bus 8 described above.
Display data transferred via the data bus 85 is written in units of 8 bits along the row direction from the write start address specified by the address data AX and AY from 6.87.

The address range of this RAM 68 corresponds to, for example, the address range (0,0) to (146111) in the liquid crystal display bag W11 shared by the segment drive circuit 17-1.

The remaining segment drive circuits 17-2 to 17-8 are also provided with a RAM 68 having the same memory capacity.

FIG. 6 is a block diagram showing the t* configuration of the address calculation port n69 provided in the memory control circuit 22 in the common drive circuit 1. From the CPtJ 12, the common drive circuit 1 receives 11-bit address data including a code bit in the X direction of the liquid crystal display device 11, and 10-bit address data including a code bit in the Y direction. The common drive circuit 1 generates 12-bit address data including address data XEO to XE9 in the X direction, an extension bit XE, and a sign bit XS for each data segment drive circuit 17 from this address data, and also generates 12-bit address data in the Y direction. is address data YEO~YE
8. Generate 11-bit address data including extension bit Y and sign bit YS.

Here address data XE O ~ XE 9, YE
O to YE8 are substantial parts of the address data, and extension bits XE and YE are the substantial parts of the address data when the address data input from the CPU 12 to the common drive circuit 1 exceeds the display capacity of the display area 59. Address data XEO to XE9; outside the display area 59 defined by YEO to YE8, and the extension bits XE, Y
It is provided to restrict address data within the extended address area set by combining E. Sign bits XS and YS represent the positive or negative sign of address data.

Address data XE3 to XE9, which is a part of the X-direction address data XEO>XE9, is input to a data conversion circuit 70 implemented by, for example, a ROM.

The data conversion circuit 7o receives input data A shown in Table 1 below.
Output data 01 to o8 are written or configured in advance in addresses corresponding to addresses 1 to A7, and
Unit area Ai for every 8 bits along the direction 1. Selection data AXO to AX3 for selecting any one of At 2° . . . , At 14 (i=1 to 146) along the X direction is output.

In other words, the address calculation circuit 69 shown in FIG.
and the real address AX.

AD=112X (i-1) +AX
--- (1) i; Subscript of selection signal CEi If selection data (AχO to AX3) = 0°1.2, unit areas Al, A21 . A31 are selected correspondingly. Further, from which bit of the selected unit area Aij the start address of the display data starts is set from the χ direction address data XEO to XE2.

Further, the data conversion circuit 70 outputs the selection data B to the selection signal generation circuit 71 by data conversion shown in Table 1 above.
XO~BX2 is output, and a 3-bit selection signal BXO~
BX3 is decoded and the selection signals CE1 to CE8 are
One of these is output. On the other hand, the expansion and
E and the sign bit XS pass through the inversion circuit 72 and are input to the AND circuit 73 along with the valid signal ACX output from the data conversion circuit 70 based on Table 1 above, and the output ACX' is input to the AND circuit 74. be done.

The output of the AND circuit 74 is input to the selection signal generation circuit 71.

The Y-direction address data YEO to YE8 are input to a data conversion circuit 75 for Y-direction address data realized by a ROM or the like having a circuit similar to the data conversion circuit 70, and are converted into the data shown in Table 2 below. As a result of the conversion, the valid signal ACY extending in the Y direction is output from the data conversion circuit 75, and the extension bit YE and sign bit YS are inputted to the AND circuit 73 together with the inverted signal via the inversion circuit 72, and the output thereof is ACY' is input to the AND circuit 74.

(Left space below) Table 2 At this time, the following arithmetic processing is executed by the inversion circuit 72 and the AND circuits 73 and 74.

ACX'=ACX-XE-XS-(2)
ACY'=ACY-YE-YS...(
3) ACT=ACX"・ACY'
(4) When the calculation result of the fourth equation is "1", the CPU 12 sends a selection signal indicating that the address data stored in the common drive circuit 1 is within the address area corresponding to the display area 59. It is detected by the generation circuit 71, and selection signals CEI to CE8 can be output only at this time. The data conversion circuit 75 outputs the stage setting signal BY by the data conversion shown in Table 2 above. This signal indicates whether the display area 59 is configured to span one stage or two or more stages in the Y direction by the common drive circuit 1, and BY=O is one stage, which is the case in this case. Further, the data conversion circuit 75 outputs address data AYO to AY7 in the Y direction to be supplied to each segment drive circuit 17 by the data conversion shown in Table 2 above.

A specific example of the operation of the address calculation circuit 69 will be described below. 'As shown in FIG.
When writing , the CPU 12 outputs the virtual address (40, 70) to the common drive circuit 1. The X-direction component of virtual address AD is 70, and i=0. AX=70 is obtained. That is, the selection signal CEI is output, and the segment drive circuit 1
7-1 is selected, and the segment drive circuit 17-1 writes the display area E1 from the real address (40, 70).

Next, the virtual address of the most significant bit shown in Figure 4 is (13
0, 20), when trying to write in the display area E2,
The CPU 12 outputs the virtual address (130, 20>) to the common drive circuit l. The Y-direction component of the virtual address AD is 130, and similarly, i=2.AX=18 is obtained from the first equation. That is, the selection signal CE2 is output, and the selected segment drive circuit 17-2 writes the display area E2 from the real address (18°20).

On the other hand, when the virtual address of the most significant bit is (110, 50>) as in the display area E3 shown in FIG.
2, each control range is J. In such a case, the common drive circuit 1 uses the virtual address range (1
10, 50) to (112, 50) - Select the segment drive circuit 17-1, and select the remaining virtual address range (11
350) to (117, 50), segment drive circuit 1
7-2 is selected.

Such conversion of address data is performed on a liquid crystal display device [11
/\ data is written or read in the same way. That is, the CPU 12 ignores the classification of the address range of the liquid crystal display area 11 by each segment drive circuit 17-1 to 17-8, and generates virtual address data based on the entire address range (0,0) to (146,896). Since such address conversion processing that only needs to be output is realized by hardware having a circuit configuration as shown in FIG. 6, high-speed display operation in the liquid crystal display device 11 can be realized.

Although the present invention has been described with respect to the liquid crystal display device 11, the present invention can be implemented in other configurations in which addresses are set in the display area and display is performed.

Effects of the Invention According to the present invention, when the control means inputs the address data of the display area to the other direction address output means, the other direction address output means outputs the other direction address data to the display means. At the same time, a selection signal for each one-way address output means and address data to the selected one-way address output means are output.

Therefore, compared to the case where such address processing is performed as software processing by the CPU, the time required for display processing can be shortened and high-speed processing can be realized in display operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a common drive circuit 1 according to an embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2, FIG. 3 is the thousandth page of the data processing device 2, and FIG. 4 is a liquid crystal display device. 11, the fifth factor is the RAM 68 in the segment drive circuit 17.
FIG. 6 is a block diagram of the address calculation circuit 69 provided in the common drive circuit 11. DESCRIPTION OF SYMBOLS 1... Common drive circuit, 2... De-division processing device, 1
DESCRIPTION OF SYMBOLS 1...Liquid crystal display device, 17-1.17-8...Segment drive circuit, 68...RAM, 69...Address conversion circuit, 70.75...Data conversion circuit, 71...
...Selection signal generation circuit, CE1 to CE8...Selection signal agent Patent attorney Keiichi Nishikyo

Claims (1)

[Scope of Claims] A plurality of one-way address output means connected to a display means for displaying addresses set in a matrix in a display area, and outputting one-way address data for each predetermined address range; another direction address output means connected to the display means and outputting the other direction address data, a selection signal for each one direction address output means, and address data to the selected one direction address output means; A display control circuit comprising: control means for outputting address data of a display area to a direction address output means.