JPH04105737U - Clock switching type timing circuit - Google Patents

Abstract

(57) [Summary] [Purpose] A clock switching system that enables stable timing signals to be obtained by switching the clock generation circuit between a PLL oscillation circuit and a crystal oscillation circuit depending on the presence or absence of an external signal (for example, a video signal, etc.) The present invention provides an equation timing circuit. [Structure] The presence or absence of an external signal is detected by a signal detection circuit, and the detection signal is used to switch between a PLL oscillation circuit and a crystal oscillation circuit to apply a stable clock signal to a timing generation circuit.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention relates to a clock-switchable timing circuit, and in particular, it provides a constant stable timing circuit. The present invention relates to a clock-switched timing circuit suitable for generating a switching signal.

0002

[Prior art]

As a conventional timing circuit, for example, the one shown in FIG. 4 has been provided. there was.

0003 In the figure, 1 is a burst gate circuit, 2 is a PLL oscillation circuit, and 3 is a timing circuit. This is a generation circuit.

To explain the configuration and operation of the circuit, a video signal V is input to the burst gate circuit 1 , the burst gate circuit 1 outputs a burst signal f _sc , and this burst signal f _sc is used as a reference signal for the PLL oscillation circuit 2 . It is added to the PLL oscillation circuit 2 as a signal.

[0005]The PLL oscillation circuit 2 outputs _4fsc , which is four times the burst signal, and inputs it to the timing generation circuit 3 as a clock signal, which causes the timing generation circuit 3 to generate various timing signals and generate a burst gate signal _fsc. It outputs the same frequency as that of the PLL oscillation circuit 2 and forms a PLL circuit loop.

Further, a timing signal burst flag signal BF for extracting the burst signal f _sc from the video signal V is applied from the timing generation circuit 3 to the burst gate circuit 1 .

With the above configuration, the timing generation circuit 3 operates using a clock signal that is four times the frequency of the burst signal _fsc output from the PLL oscillation circuit 2, and the PLL oscillation circuit 2 operates based on the frequency of the video signal V. It is designed to lock to the burst signal _fsc inside.

[0008]

[Problem that the idea aims to solve]

However, in the above-mentioned conventional timing generation circuit 3, as shown in FIG. 4, the PLL oscillation circuit 2 enters a free run state when the burst signal f _sc serving as the reference signal disappears due to the stop of the video signal V. The problem was that the timing was off. This invention was made in view of the above points, and its purpose is to eliminate the drawbacks of the conventional example and to use a PLL circuit or a crystal oscillation circuit as a circuit that generates a clock signal depending on the presence or absence of a video signal. An object of the present invention is to provide a clock switching type timing circuit as described above.

[0009]

[Means to solve the problem]

The clock switching type timing circuit of this invention inputs a video signal and bursts. A burst gate circuit that outputs a signal and a PLL ( Phase Locked Loop) oscillation circuit and PLL oscillation circuit. A timing oscillator circuit that generates various timing signals in response to a clock signal. In the configured timing circuit, a signal detection circuit that detects the video signal; a second clock signal having the same frequency as the first clock signal output from the PLL oscillation circuit; A crystal oscillation circuit that oscillates a clock signal and an output signal of the signal detection circuit generate the first signal. The second clock signal and the second clock signal are switched and outputted to the timing generation circuit. A clock changeover switch is provided to switch off the clock when the video signal is lost. Switch the switching switch to the second clock signal side and output it to the timing generation circuit. It is configured as follows.

0010

[Effect]

According to this invention, a burst gamer that inputs a video signal and outputs a burst signal is developed. A PLL (Phase Locked) circuit that uses a burst signal as a reference signal Loop) oscillator circuit and each clock signal output from the PLL oscillator circuit. The timing circuit consists of a timing oscillator circuit that generates a timing signal. a signal detection circuit for detecting the video signal and a signal output from the PLL oscillation circuit; a crystal oscillator that oscillates a second clock signal with the same frequency as the first clock signal A first clock signal and a second clock signal are detected by the output signal of the signal detection circuit and the signal detection circuit. A clock selection switch that switches between the lock signal and the clock signal and outputs it to the timing generation circuit. If the video signal is lost, the clock selection switch can be set to the second clock. Since the configuration is configured to switch to the clock signal side and output it to the timing generation circuit, the video It becomes possible to obtain a stable timing signal regardless of the presence or absence of the signal. .

[0011]

【Example】

Examples of the clock switching type timing circuit according to this invention are shown in FIGS. 1 to 3. I will explain based on this.

0012 Note that the same parts as in the conventional example are given the same reference numerals, and the explanation thereof will be omitted.

[0013] In the figure, 4 and 8 are signal detection circuits, 5 and 9 are crystal oscillation circuits, and 6 is a PLL oscillation circuit. The circuit SW is a clock signal changeover switch. The configuration of the first embodiment shown in FIG. The output circuit 4 is connected to the video signal, and the clock signal is disconnected from the output of the signal detection circuit 4. It is connected to the control terminal of the changeover switch SW.

Further, the output signal CLK ₁ of the PLL oscillation circuit 2 is connected to one contact terminal of the clock changeover switch SW, and the output signal CLK ₂ of the crystal oscillation circuit 5 is connected to the other contact terminal. A common terminal of the clock changeover switch SW is connected to the timing generation circuit 3.

[0015] Timing signal generation of the timing generation circuit 3 of the block configured as described above. In raw operation, when there is a video signal V, the signal detection circuit 4 detects the same signal in the video signal. detects the period signal and outputs "H" level to the output.

When the signal detection circuit 4 outputs the “H” level, the clock changeover switch SW is connected to the PLL oscillation circuit 2 side, and the clock signal input to the timing generation circuit 3 becomes the output signal CLK ₁ from the PLL generation circuit 2. Each timing signal HD, BF, . . . BLK output from the timing generation circuit 3 is generated in synchronization with the video signal V of the input signal.

Note that the PLL oscillation circuit 2 is designed to lock onto the burst signal in the video signal V, and outputs a frequency four times that of the burst signal f _sc as the clock signal CLK ₁ .

Further, when the video signal V disappears, the signal detection circuit 4 outputs the "L" level and switches the clock changeover switch SW to the crystal oscillation circuit 5 side, thereby changing the clock signal input to the timing generation circuit 3. The clock signal CLK ₂ outputted by the crystal oscillation circuit 5 and each timing signal outputted from the timing generation circuit 3 generate timing with the accuracy of the crystal oscillation circuit 5. Note that the output frequency of the crystal oscillation circuit 5 is _4fsc .

Furthermore, in the second embodiment shown in FIG. 2, the reference signal input to the PLL oscillation circuit 2 is switched between the burst signal F _SC and the output signal from the crystal oscillation circuit 9 to correspond to the presence or absence of the video signal V. The oscillation frequency of the crystal oscillation circuit 9 is _fsc , which is the same as that of the burst signal.

[0020] Further, in the third embodiment shown in FIG. 3, the burst signal input to the PLL oscillation circuit 6 Instead, the horizontal synchronization signal H obtained from the video signal V is obtained from the synchronization separation circuit 7. The timing generation operation is the same as in the first embodiment.

[0021] As described above, if there is a video signal V, a timer synchronized with the video signal V outputs a timing signal, and if there is no video signal V, outputs a timing signal for crystal oscillation accuracy. You will be able to get the number.

[0022]

[Effect of the idea]

According to the clock switching type timing circuit according to this invention, it is configured as described above. Therefore, the following effects are achieved.

[0023] The effect of being able to obtain a stable timing signal regardless of the presence or absence of a video signal There is.

[0024] Moreover, it is easy to implement by simply adding a crystal oscillation circuit and a signal detection circuit. It has excellent features.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram showing a first embodiment of this invention.

FIG. 2 is a configuration block diagram showing a second embodiment.

FIG. 3 is a configuration block diagram showing a third embodiment.

FIG. 4 is a configuration block diagram showing a conventional example.

[Explanation of symbols]

1 Burst gate circuit 2,6 PLL oscillation circuit 3 Timing generation circuit 4,8 Signal detection circuit 5,9 Crystal oscillation circuit 7 Synchronous separation circuit SW Clock selection switch

Claims (1)

[Scope of utility model registration request] 1. A burst gate circuit that inputs a video signal and outputs a burst signal, a PLL (Phase Locked Loop) oscillation circuit that uses the burst signal as a reference signal, and a clock signal output from the PLL oscillation circuit that receives various timing signals. In a timing circuit configured with a timing oscillation circuit that generates a signal, a signal detection circuit that detects the video signal and a second clock signal having the same frequency as the first clock signal output from the PLL oscillation circuit are oscillated. A crystal oscillator circuit and a clock changeover switch that switches between a first clock signal and a second clock signal according to the output signal of the signal detection circuit and outputs the same to the timing generation circuit are provided, and when the video signal disappears, the clock changeover switch is provided. A clock switching type timing circuit characterized in that the switch is configured to switch to the second clock signal side and output the signal to the timing generation circuit.