JPH04104574A - Picture processor for facsimile - Google Patents

Picture processor for facsimile

Info

Publication number
JPH04104574A
JPH04104574A JP22152090A JP22152090A JPH04104574A JP H04104574 A JPH04104574 A JP H04104574A JP 22152090 A JP22152090 A JP 22152090A JP 22152090 A JP22152090 A JP 22152090A JP H04104574 A JPH04104574 A JP H04104574A
Authority
JP
Japan
Prior art keywords
linear density
image information
memory
output
address signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22152090A
Other languages
Japanese (ja)
Inventor
Kazuhiro Kusuda
楠田 和広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22152090A priority Critical patent/JPH04104574A/en
Publication of JPH04104574A publication Critical patent/JPH04104574A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To unnecessitate excess time for processing and enormous memory areas by executing a conversion processing on a memory by providing a linear density conversion circuit between a picture processing circuit and the memory. CONSTITUTION:A picture memory 11 is provided to output first image information 17 and 19 of stored high-quality linear density for each line by first address signals 16 and 18, a picture processing circuit 13 is provided to output a second address signal 14 and to process second image information 15 of inputted standard linear density, and a linear density conversion circuit 12 is provided to output the first address signals 16 and 18 for two lines by the second address signal 14 and to output the OR output of the first inputted image information 17 and 19 for two lines as the second image information 15. Thus, since the linear density is converted parallelly with the read-out operation of pictures in the memory, the picture memory can be read out without requiring the memory to once convert the image information of the high-quality linear density to the image information of the standard linear density and to store it or being conscious of the picture processing circuit with the standard linear density as an object is a high-quality linear density form.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はファクシミリの画像処理装置に関し、特に高品
質線密度の画情報を標準線密度の画情報に変換するファ
クシミリの画像処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a facsimile image processing apparatus, and more particularly to a facsimile image processing apparatus that converts high quality line density image information into standard line density image information.

〔従来の技術〕[Conventional technology]

従来のファクシミリの画像処理装置は、高品質線密度で
記憶されたメモリからの画情報を標準線密度の画情報と
して使用する場合は、高品質線密度の2ラインの画情報
で論理和を求めた標準線密度の画情報を一担、メモリの
別領、域に格納し、別領域から読み出した標準線密度の
画情報を用いて画像処理を行っていた。
Conventional facsimile image processing devices, when using image information stored in memory at high quality line density as image information at standard line density, perform a logical sum using two lines of image information at high quality line density. The standard linear density image information is stored in a separate area of the memory, and image processing is performed using the standard linear density image information read out from the separate area.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のファクシミリの画像処理装置では、高品
質線密度でメモリに記憶された画情報を読み出し、標準
線密度の画情報に変換して再度メモリに記憶するので、
メモリ上で変換処理を行うため余分な処理時間および膨
大なメモリ領域が必要となるという欠点がある。
In the conventional facsimile image processing device described above, image information stored in memory at high quality linear density is read out, converted to image information at standard linear density, and then stored in memory again.
Since the conversion process is performed in memory, it has the disadvantage that extra processing time and a huge memory area are required.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のファクシミリの画像処理装置は、記憶された高
品質線密度の第1の画情報を第1のアドレス信号により
1ラインごとに出力する画像メモリと、第2のアドレス
信号を出力し入力の標準線密度の第2の画情報を処理す
る画像処理回路と、前記第2のアドレス信号により2ラ
イン分の前記第1のアドレス信号を出力し入力の2ライ
ン分の前記第1の画情報の論理和出力を前記第2の画情
報として出力する線密度変換回路とを有している。
The facsimile image processing device of the present invention includes an image memory that outputs stored first image information of high quality line density line by line using a first address signal, and an image memory that outputs a second address signal and outputs input information. an image processing circuit that processes second image information of standard linear density; and an image processing circuit that outputs the first address signal for two lines based on the second address signal, and processes the first image information for two lines of input. and a linear density conversion circuit that outputs the logical sum output as the second image information.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。第1図は本発明の一実施例のブロック図、第2図及び
第3図は本実施例の動作を説明するための図である。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIGS. 2 and 3 are diagrams for explaining the operation of this embodiment.

本実施例は第1図において、記憶された高品質線密度の
第1の画情報17.19を第1のアドレス信号16.1
8により1ラインごとに出力する画像メモリ11と、第
2のアドレス信号14を出力し入力の標準線密度の第2
の画情報15を処理する画像処理回路13と、第2のア
ドレス信号14により2ライン分の第1のアドレス信号
16゜18を出力し、入力の2ライン分の第1の画情報
17.19の論理和出力を第2の画情報15として出力
する線密度変換回路12とを有して構成される。
In this embodiment, as shown in FIG.
8 outputs an image memory 11 line by line, and outputs a second address signal 14 to output the second address signal 14 of the input standard linear density.
The image processing circuit 13 processes the image information 15 of , and outputs the first address signal 16.18 for two lines based on the second address signal 14, and outputs the first image information 17.19 for the input two lines. and a linear density conversion circuit 12 that outputs the logical sum output of as the second image information 15.

第2図は、本実施例において線密度変換の対象となる画
像メモリ11上の高品質の画情報、第3図は第2図に対
して線密度変換を行った後の標準の画像情報である。な
お、図において、1−黒ドツト、0=白ドツトを示して
いる。
Figure 2 shows high quality image information on the image memory 11 that is subject to linear density conversion in this embodiment, and Figure 3 shows standard image information after performing linear density conversion on Figure 2. be. In the figure, 1 indicates a black dot, and 0 indicates a white dot.

第1図における線密度変換回路2が第2図の高品質画情
報から第3図の標準画情報を生成する過程を説明すると
線密度変換回路12では、画像処理回路13の発生する
アドレス信号14=Xに対して、アドレス信号16=2
X−1およびアドレス信号18=2Xを画像メモリ11
に入力し、得られた画像メモリ11からの画情報17=
YA。
To explain the process by which the linear density conversion circuit 2 in FIG. 1 generates the standard image information in FIG. 3 from the high-quality image information in FIG. =X, address signal 16=2
X-1 and address signal 18 = 2X to image memory 11
Image information 17 from image memory 11 obtained by inputting into
YA.

画情報19=YBのOR論理出力15=YCを画像処理
回路13へ出力している。すなわち、画像処理回路13
ではラインアドレス14=1を出力すると、線密度変換
回路12によってアドレス信号6とアドレス信号8とを
画像メモリ1へのアドレス入力とし、それぞれの出力画
情報“00001100”と10111000 ”のO
R論理出力の“10111100”を画像処理回路13
へ出力する。次に画像処理回路13がアドレス信号14
=2を出力すると、線密度変換回路2によってアドレス
信号16=3、アドレス信号18=4を画像メモリ11
へのアドレス入力とし、それぞれの出力画情報“111
10000”と“11001101”のOR回論理出力
“11111101”を画像処理回路13へ出力する。
OR logic output 15 = YC of image information 19 = YB is output to the image processing circuit 13 . That is, the image processing circuit 13
Now, when the line address 14=1 is output, the linear density conversion circuit 12 uses the address signal 6 and the address signal 8 as address inputs to the image memory 1, and outputs the output image information "00001100" and "10111000" respectively.
The R logic output “10111100” is sent to the image processing circuit 13.
Output to. Next, the image processing circuit 13 outputs the address signal 14.
=2, the linear density conversion circuit 2 outputs the address signal 16=3 and the address signal 18=4 to the image memory 11.
input the address to , and output image information “111” for each.
10000" and "11001101", the logical output "11111101" is output to the image processing circuit 13.

以下同様に、画像処理回路13の発生するアドレス信号
4=Xに対して、アドレス信号16=2X−1およびア
ドレス信号7=2Xを画像メモリ1へのアドレス入力と
し、得られた画像メモリ11の出力画情報17=YA、
出力画情報19=YBのOR論理出力15=YCを画像
処理回路13へ出力していくことによって、画像処理回
路13は画像メモリ11から第3図に示す標準画情報を
読み出しているのと同じ動作をすることができる。
Similarly, in response to address signal 4=X generated by image processing circuit 13, address signal 16=2X-1 and address signal 7=2X are input to image memory 1, and the resulting image memory 11 is Output image information 17=YA,
By outputting the OR logical output 15=YC of output image information 19=YB to the image processing circuit 13, the image processing circuit 13 is equivalent to reading out the standard image information shown in FIG. 3 from the image memory 11. can perform actions.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、画像処理回路とメモリ閏
に線密度変換回路を設けることによって、メモリ画像の
読み出し動作と並行して線密度変換を行うことにより、
高品質線密度の画情報を標準線密度の画情報に一旦変換
して記憶するメモリを必要とすることなく、また、標準
線密度を対象とした画像処理回路が、高品質−線密度形
式であることを意識することなく画像メモリを読み出せ
る効果がある。
As explained above, the present invention provides linear density conversion circuits in the image processing circuit and memory jump, and performs linear density conversion in parallel with the memory image readout operation.
There is no need for memory to temporarily convert and store high-quality linear density image information into standard linear density image information, and the image processing circuit for standard linear density can convert high-quality linear density image information into high-quality linear density format. This has the effect of allowing you to read out the image memory without being aware of it.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のブロック図、第2図及び第
3図は本実施例の動作を説明するための図である。 11・・・画像メモリ、12・・・線密度変換回路、1
3・・・画像処理回路。
FIG. 1 is a block diagram of one embodiment of the present invention, and FIGS. 2 and 3 are diagrams for explaining the operation of this embodiment. 11... Image memory, 12... Linear density conversion circuit, 1
3... Image processing circuit.

Claims (1)

【特許請求の範囲】[Claims] 記憶された高品質線密度の第1の画情報を第1のアドレ
ス信号により1ラインごとに出力する画像メモリと、第
2のアドレス信号を出力し入力の標準線密度の第2の画
情報を処理する画像処理回路と、前記第2のアドレス信
号により2ライン分の前記第1のアドレス信号を出力し
入力の2ライン分の前記第1の画情報の論理和出力を前
記第2の画情報として出力する線密度変換回路とを有す
ることを特徴とするファクシミリの画像処理装置。
An image memory that outputs the stored first image information of high quality linear density line by line using a first address signal, and an image memory that outputs the second image information of input standard linear density by outputting a second address signal. An image processing circuit to process, outputs the first address signal for two lines based on the second address signal, and outputs a logical sum of the input two lines of the first image information as the second image information. 1. A facsimile image processing device, comprising: a linear density conversion circuit that outputs a linear density conversion circuit.
JP22152090A 1990-08-23 1990-08-23 Picture processor for facsimile Pending JPH04104574A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22152090A JPH04104574A (en) 1990-08-23 1990-08-23 Picture processor for facsimile

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22152090A JPH04104574A (en) 1990-08-23 1990-08-23 Picture processor for facsimile

Publications (1)

Publication Number Publication Date
JPH04104574A true JPH04104574A (en) 1992-04-07

Family

ID=16768000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22152090A Pending JPH04104574A (en) 1990-08-23 1990-08-23 Picture processor for facsimile

Country Status (1)

Country Link
JP (1) JPH04104574A (en)

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