JPH02174472A - Two-dimensional picture synthesis circuit - Google Patents

Two-dimensional picture synthesis circuit

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Publication number
JPH02174472A
JPH02174472A JP33170588A JP33170588A JPH02174472A JP H02174472 A JPH02174472 A JP H02174472A JP 33170588 A JP33170588 A JP 33170588A JP 33170588 A JP33170588 A JP 33170588A JP H02174472 A JPH02174472 A JP H02174472A
Authority
JP
Japan
Prior art keywords
picture
image
dimensional
synthesis circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33170588A
Other languages
Japanese (ja)
Inventor
Tomoyoshi Shikina
識名 朝恵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP33170588A priority Critical patent/JPH02174472A/en
Publication of JPH02174472A publication Critical patent/JPH02174472A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the picture quality of picture synthesis by synthesizing the picture in the lateral direction and using a memory to invert the longitudinal and lateral arrangement of the picture. CONSTITUTION:A picture resulted from 1-dimensional synthesis and an input signal are stored in memories 8-10, and the stored data are read from the memories so that the longitudinal and lateral directions of the original picture are reversed by using a control signal generated by a control circuit 11. Then the picture in the longitudinal direction is synthesized by multipliers 12, 13, an adder 14 and a subtractor 15. Then the relation of the longitudinal direction and the lateral direction of the picture is restored by a memory 16 and the result is outputted to an output terminal 17.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はテレビジョン信号処理に関し、特にティジタル
画像信号の処理に開する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to television signal processing, and in particular to the processing of digital image signals.

[従来の技術] 従来、この種の画像合成回路は、第2図に示すように映
像人力1と映像人力2とをキー人力によって乗算器3,
4て乗算した後に加算器7で合成しており、1次元的な
処理であった。
[Prior Art] Conventionally, this type of image synthesis circuit has been configured to combine video input 1 and video input 2 into multipliers 3 and 2 using key input, as shown in FIG.
After multiplying by 4 and then combining by adder 7, it was a one-dimensional process.

[発明が解決しようとする問題点] 上述した従来の画像合成回路は、1次元処理であるため
、2次元的な分布を持つキー人力で画像を合成する場合
に、斜めの境界線上の画質に問題があった。
[Problems to be Solved by the Invention] The conventional image synthesis circuit described above performs one-dimensional processing, so when manually synthesizing images with a two-dimensional distribution, the image quality on the diagonal boundary line may be affected. There was a problem.

[問題点を解決するための手段] 本発明に係る2次元画像合成回路は2種類の画像を任意
のキー信号を用いて1次元領域で合成する画像合成回路
において、1次元合成後の画像を1フレーム蓄積する手
段Aと、キー信号に対応する合成前の画像を1フレーム
蓄積する手段Bと、キー信号を1フレーム蓄積する手段
Cと、前記手段A、  B、  Cに蓄積された画像の
縦方向と横方向の関係が逆になるように前記手段A、 
 B、  Cを制御する手段りと、前記手段Cの出力を
用いて前記手段Aの出力と前記手段Bの出力とを合成す
る手段Eと、前記手段Eによって合成された画像を1フ
レーム蓄積する手段Fとを含むことである。
[Means for Solving the Problems] A two-dimensional image synthesis circuit according to the present invention is an image synthesis circuit that synthesizes two types of images in a one-dimensional area using an arbitrary key signal. means A for accumulating one frame; means B for accumulating one frame of a pre-combined image corresponding to a key signal; means C for accumulating one frame of a key signal; The means A, such that the relationship between the vertical direction and the horizontal direction is reversed;
means for controlling B and C; means E for synthesizing the output of the means A and the output of the means B using the output of the means C; and storing one frame of the image synthesized by the means E. means F.

[実施例コ 次に本発明の実施例について図面を参照して説明する。[Example code] Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

映像信号1と映像信号2は、それぞれ入力端子1と入力
端子2から乗算器3,4へ入力されて入力端子5から人
力されるキー信号と減算器6によって、ゲインコントロ
ールされた結果、加算器7て加算されて合成される。こ
れらの処理は1次元処理であるため、キー信号が2次元
的な分布をもつ場合に画質に問題があった。そこで、こ
の実施例ては1次元的に合成された結果の画像と入力信
号1とキー信号をメモリ8. 9. 10に蓄積し、制
御回路11によって発生された制御信号によってメモリ
から蓄積結果を原画像の縦方向と横方向が逆になるよう
に読出す。その後さらに乗算器12゜13と加算器14
及び減算器15によって画像の縦方向の合成が行われる
。その後、メモリ16によって、画像の縦方向と横方向
の関係を元に戻して、出力端子17へ出力される。本実
施例では手段A−Cはメモリ8〜10で構成されており
、手段りは制御回路11で構成される。また手段Eは乗
算器12,13、加算器14、減算器15て構成され、
手段Fはメモリ16で構成されている。
Video signal 1 and video signal 2 are input to multipliers 3 and 4 from input terminal 1 and input terminal 2, respectively, and gain-controlled by a key signal and subtractor 6, which are manually input from input terminal 5, and as a result, an adder is input. 7 and are added and synthesized. Since these processes are one-dimensional processes, there is a problem in image quality when the key signal has a two-dimensional distribution. Therefore, in this embodiment, the image resulting from the one-dimensional synthesis, the input signal 1, and the key signal are stored in the memory 8. 9. 10, and the accumulation result is read out from the memory in accordance with a control signal generated by a control circuit 11 so that the vertical and horizontal directions of the original image are reversed. After that, a multiplier 12゜13 and an adder 14
And the subtractor 15 performs vertical synthesis of the images. Thereafter, the memory 16 restores the relationship between the vertical and horizontal directions of the image and outputs it to the output terminal 17. In this embodiment, means A to C are constituted by memories 8 to 10, and means A to C are constituted by a control circuit 11. Further, the means E is composed of multipliers 12 and 13, an adder 14, and a subtracter 15,
The means F consists of a memory 16.

[発明の効果コ 以上説明したように本発明は、画像の横方向の画像合成
を行った後にメモリを使用して画像の縦横を逆転するこ
とにより、画像縦方向の画像合成も行い、2次元的な分
布を持つキー信号による画像合成の画質を向上できる効
果がある。
[Effects of the Invention] As explained above, the present invention synthesizes images in the horizontal direction and then reverses the vertical and horizontal directions of the images using memory, thereby also synthesizing images in the vertical direction. This has the effect of improving the image quality of image synthesis using key signals having a similar distribution.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のブロック図である。 1、 2. 5・・・・・入力端子、 3.4・・・・・・・乗算器、 6・・・・・・・・・減算器、 7・・・・・・・・・・加算器、 8、 9. 10. 16・・・・・・メモ「八11・
・・・・・・・・・制御回路、 12.13・・・・・・・乗算器、 14・・ ・ ・ ・・・・ ・ ・加算器、15・・
・・・・・・・・・減算器、 17・・・・・・・・・・出力端子。 第2図は従来の回路例のブロック図である。 1、 2. 5・・・・・・・入力端子、3.4・・・
・・・・・・・乗算器、 6・ ・ ・ ・・・・・・・・・減算器、7・・・・
・・・・・・・・加算器、 8・・・・・・・・・・・・出力端子。 特許出願人  日本電気株式会社 代理人 弁理士  桑 井 清 −
FIG. 1 is a block diagram of one embodiment of the present invention. 1, 2. 5... Input terminal, 3.4... Multiplier, 6... Subtractor, 7... Adder, 8 , 9. 10. 16... Memo "811.
...... Control circuit, 12.13... Multiplier, 14... ... Adder, 15...
・・・・・・・・・Subtractor, 17・・・・・・・・・Output terminal. FIG. 2 is a block diagram of an example of a conventional circuit. 1, 2. 5... Input terminal, 3.4...
・・・・・・Multiplier, 6・ ・ ・ ・・・・・・・・・Subtractor, 7...
・・・・・・・・・Adder, 8・・・・・・・・・・・・Output terminal. Patent Applicant: NEC Corporation Representative, Patent Attorney: Kiyoshi Kuwai −

Claims (1)

【特許請求の範囲】[Claims] 2種類の画像を任意のキー信号を用いて1次元領域で合
成する画像合成回路において、1次元合成後の画像を1
フレーム蓄積する手段Aと、キー信号に対応する合成前
の画像を1フレーム蓄積する手段Bと、キー信号を1フ
レーム蓄積する手段Cと、前記手段A、B、Cに蓄積さ
れた画像の縦方向と横方向の関係が逆になるように前記
手段A、B、Cを制御する手段Dと、前記手段Cの出力
を用いて前記手段Aの出力と前記手段Bの出力とを合成
する手段Eと、前記手段Eによって合成された画像を1
フレーム蓄積する手段Fとを含むことを特徴とする2次
元画像合成回路。
In an image synthesis circuit that synthesizes two types of images in a one-dimensional area using an arbitrary key signal, the image after one-dimensional synthesis is
means A for accumulating frames; means B for accumulating one frame of a pre-combined image corresponding to a key signal; means C for accumulating one frame of a key signal; means D for controlling said means A, B, and C so that the relationship in direction and lateral direction is reversed; and means for synthesizing the output of said means A and the output of said means B using the output of said means C; E and the image synthesized by the means E as 1
A two-dimensional image synthesis circuit comprising: means F for accumulating frames.
JP33170588A 1988-12-27 1988-12-27 Two-dimensional picture synthesis circuit Pending JPH02174472A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33170588A JPH02174472A (en) 1988-12-27 1988-12-27 Two-dimensional picture synthesis circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33170588A JPH02174472A (en) 1988-12-27 1988-12-27 Two-dimensional picture synthesis circuit

Publications (1)

Publication Number Publication Date
JPH02174472A true JPH02174472A (en) 1990-07-05

Family

ID=18246668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33170588A Pending JPH02174472A (en) 1988-12-27 1988-12-27 Two-dimensional picture synthesis circuit

Country Status (1)

Country Link
JP (1) JPH02174472A (en)

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