JPH0422073B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial Application Field" The present invention provides a method for converting a first television signal having a first field frequency into a 21st television signal having a second field frequency lower than the first field frequency.
The present invention relates to a television signal format conversion device for converting a television signal into a television signal.

"Background technology and its problems" Conventionally, the 525/60 television system (525 lines, 60Hz field frequency) to 625/60 television system (525 lines, 60Hz field frequency)
When converting the field to 50 television format (625 lines and 50Hz field frequency),
In the case of still images, image processing is performed such that 6 fields are thinned out by 1 field. FIG. 1A shows a 525/60 television system signal, and FIG. 1B shows a 625/50 television system signal.

In FIG. 1, Oi indicates the i-th first field, Ei indicates the i-th second field, Fi indicates the i-th frame, and Fi′ is
The i-th frame after conversion is shown. As can _be understood from Fig. 1, the _{5 fields O 1 , E 1 .} are converted respectively. Then, the second field E ₃ of the third frame F ₃ is thinned out, and then O ₄ , E _{4 ,} etc. are thinned out again.
...O ₆ is converted into five fields E ₃ , O ₄ , . . . E ₆ of the 625/50 television system. In this way, the number of fields can be converted by repeating the process of converting 6 fields into 5 fields. Furthermore, when producing moving images, fields before and after thinning are combined to make the movement of the image as smooth as possible. Therefore, there was a drawback that the image became blurred when there was a large amount of movement in the image.

``Object of the Invention'' The purpose of the present invention is to provide a television signal format conversion device that can obtain a smooth field-converted image without blurring in the case of a moving image. .

"Summary of the Invention" The present invention provides a method for converting a first television signal having a first field frequency into a second television signal having a second field frequency different from the first field frequency. A second television signal is obtained by writing one television signal into a memory and thinning or repeatedly reading out the first television signal in accordance with the field frequencies of the first and second television signals. In addition, the motion between frames of the first television signal is detected, and the writing or reading position of the first television signal in the memory is controlled based on the motion detection output.

Embodiment In one embodiment of the present invention, a video signal is converted into a digital video signal and processed. The sampling frequency in this case is the horizontal frequency H (e.g.
For example, an integer multiple of approximately 15.734KHz in the NTSC system.
910 times, and the sample points in that case are fixed as shown in FIG. Then, a certain cluster of sample points (hereinafter referred to as a block) is created on the television screen. As an example, as shown in FIG. 2, one block consists of 8 samples in the horizontal direction and 4 lines in the line direction, a total of 32 samples.

The screen is divided into blocks, and the movement of the screen during one frame is detected. In other words, it is checked for all blocks how far and in what direction the picture in one block has moved during one frame. As shown in Figure 3, when a block at position Bn in a certain frame Fn moves to position Bn+ ₁ in the next frame Fn+ ₁ , the direction and amount of the movement are determined by the motion vector (x, y). will be shown. A matching method can be used as one method for detecting motion vectors. This matching method detects motion vectors by pattern matching, which assumes multiple positions around each block and detects which of them matches the position of the block one frame later. , the motion vector is determined from the detection result. The motion is corrected using the motion vector obtained in this way.

A case will be described in which, for example, a 6-frame video is converted into a 5-frame video using a motion vector. In FIG. 4, F ₁ , F ₂ . . . F ₆ indicate frames on the input side, and F ₁ ', F ₂ '... F ₅ ' indicate frames on the output side.

Frame F ₁ is converted directly into frame F ₁ ′. The conversion from frame F ₂ to F ₂ ′ uses a motion vector. The magnitude of the motion vector is multiplied by the correction coefficient +1/5 and the moving block is moved to create a frame of F ₂ '. Similarly, from frame F ₃ to frame F ₃ ′, the magnitude of the motion vector is corrected to +2/5 times, and frame F ₄
From frame F ₄ ′, the magnitude of the motion vector is +
Correct by 3/5 times and move the moving block. In this case, the moving block may be moved from frame _F5 to frame _F4 ' by correcting the motion vector by -2/5 times. Furthermore, frame F ₆
From frame F ₅ ', the moving block is moved using a motion vector corrected to -1/5.

In this way, when creating 5 frames from 6 frames, the movement caused by thinning out 1 frame is gradually corrected by 20% when converting each frame, resulting in a smooth conversion output without blurring. can get. For example, to obtain the image of frame F ₂ ′, the motion vector is corrected by +1/5 on the image of frame F ₂ , but at the point when the correction is completed, the block that has undergone the motion correction is
Move from position Bn to position Bn+ ₁ . If there is no movement in the adjacent block due to correction, the image in the shaded area in FIG. 5 will be missing, so it is necessary to compensate for the background image. This background compensation is performed by fitting the next image into the missing part of the image.

For this background compensation, a flag is used in which one sample corresponds to one bit. FIG. 6 shows a flag memory in which flags for one frame are stored. In Figure 6, (4 samples x 2 lines)
is considered one block. This flag memory is for distinguishing between an image area where image data is written and an image area where image data is missing. All flags in this flag memory are set to 1 in advance, and then 0 is written when motion correction (including the case of a correction coefficient of 1) is completed in block units. Therefore, as shown by the hatched area in FIG. 5, a flag of 1 remains corresponding to the area where image information is missing. Background compensation can be performed by embedding the next image to be included in the background in the position of flag 1 in this flag memory.

FIG. 7 shows the configuration of one embodiment of the invention described above. A video signal having 8 bits per sample and digitized at a sampling frequency of 910H is supplied to a frame memory 1, and the output of this frame memory 1 is supplied to frame memories 2 and 3.

Output of frame memory 1 and frame memory 2
The output of each block is supplied to the motion vector detection circuit 4, and a motion vector (x,
y) is detected by, for example, a pattern matching method. This motion vector is supplied to a correction circuit 5, and components x and y of the motion vector are multiplied by a correction coefficient K from a terminal 6. This correction coefficient K is the fourth
As shown in the figure, (0, 1/5, 2/5, 3/5, −1/
5) and 6 frames as a unit and sequentially changes every frame.

Motion vector after correction (1+K)x, (1+K)
y is supplied to the address circuit of the frame memory 3 and the address circuit of the flag memory 7. X address generation circuit 8 and Y for frame memory 3
Address generation circuits 9 are provided respectively. The output of the X address generation circuit 8 and the corrected motion vector (1+K)x are added in the adder circuit 10 to form the 1
+K)y are added by the adder circuit 11 and set as the Y address of the frame memory 3.

This frame memory 3 is provided with a memory control circuit (not shown), and the write and read operations are controlled so that the video data is thinned out at a rate of 6 frames to 1 frame. Then, the write block address of the frame memory 3 is shifted according to the corrected motion vector. Reading from the frame memory 3 is performed sequentially using addresses that are not shifted by this motion vector. Data read from frame memory 3 is supplied to selector 12 .

The flag memory 7 is a memory whose number of bits is equal to the number of samples in one frame.
The write address is controlled in the same way. In other words,
An X address generation circuit 13 and a Y address generation circuit 14 are provided in association with the flag memory 7,
Address signals generated from each are supplied to adder circuits 15 and 16, and the corrected motion vectors are added. This flag memory 7 is always given 0 as input data, and 0 is written to the address of the flag memory 7 that corresponds to the address in the frame memory 3 where the image data is written. Frame memory 3 and flag memory 7 are read out synchronously.

Input data is supplied to the selector 12, and one of the input data and read data from the frame memory 3 is selected and taken out as output data. The output of the flag memory 7 is used as a control signal for the selector 12. Flag memory 7
When the output of the flag memory 7 is 1, the output data of the frame memory 3 is selected by the selector 12, and when the output of the flag memory 7 is 0, the input data is selected. This flag memory 7 and selector 1
Background compensation is performed by step 2, and it is possible to obtain output data in which portions where image information is missing are filled in with image data of the next frame.

"Application Example" The present invention can also be applied to the case where, for example, 6 fields are converted to 5 fields not in frame units but in field units.

Furthermore, as an example of Butsuroku, (8 samples ×
It may be one-dimensional, such as 1 line).

"Effects of the Invention" According to the present invention, when a plurality of fields are thinned out at the rate of one field in order to convert the number of fields (or number of frames) in a television system, the converted television image It is possible to prevent blurring from occurring inside the image. In conventional television signal format conversion devices, for example, the image data of three fields, including the front and rear fields, are combined using a predetermined weighting process, resulting in blurred images, especially in the case of images with large movements. It had its flaws.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram used to explain a conventional television signal format conversion device, FIG. 2 is a schematic diagram used to explain television signal sampling in an embodiment of the present invention, and FIG. A schematic diagram used to explain motion vector detection in an embodiment of the invention, FIG. 4 is a schematic diagram used to explain motion correction in an embodiment of the invention, and FIGS. FIG. 7, which is a schematic diagram used to explain background compensation in one embodiment, is a block diagram showing the configuration of one embodiment of the present invention. 1, 2, 3...Frame memory, 4...Motion vector detection circuit, 5...Correction circuit, 7...Flag memory, 12...Selector.

Claims (1)

[Scope of Claims] 1. When converting a first television signal having a first field frequency into a second television signal having a second field frequency lower than the first field frequency, the first television signal A television set in which a second television signal is obtained by writing a television signal into a memory and reading out the first television signal after thinning out the first television signal in accordance with the field frequency difference between the first and second television signals. The television signal format changing device includes a motion vector detection circuit that detects motion between frames of the first television signal, and forms a correction motion vector based on the detected motion vector with a coefficient according to a thinning ratio. a memory address control circuit that controls the writing or reading device in the memory based on the output of the correction circuit; and a memory address control circuit that controls the image missing part of the second television signal based on the output of the correction circuit. 1. A television signal format conversion device comprising: a detection circuit that performs detection; and an image selection circuit that switches and outputs the output signal of the memory or the next image signal according to the detection output of the detection circuit.