JPH0410432A - Gaas wafer and manufacture thereof - Google Patents
Gaas wafer and manufacture thereofInfo
- Publication number
- JPH0410432A JPH0410432A JP2110819A JP11081990A JPH0410432A JP H0410432 A JPH0410432 A JP H0410432A JP 2110819 A JP2110819 A JP 2110819A JP 11081990 A JP11081990 A JP 11081990A JP H0410432 A JPH0410432 A JP H0410432A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- gaas wafer
- layer
- heater
- mirror
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 25
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 6
- 239000003708 ampul Substances 0.000 abstract description 6
- 239000010453 quartz Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000007943 implant Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 39
- 239000007789 gas Substances 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 238000005336 cracking Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000000370 acceptor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004441 surface measurement Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明はp型GaAsウェハおよびその表面処理法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a p-type GaAs wafer and a surface treatment method thereof.
[従来技術]
上記従来のp型GaAsウェハを用いたSH(シングル
へテロ)のpn接合は、第2図に示すように、高純度H
2ガス中においてGaAsウェハ1を搭載したスライド
を移動させてその表面にまず、p層成長溶液層2を接触
させてp層を成長させ、次いでn層成長溶液層3を接触
させてn層を成長させて生成するようにしていた。[Prior art] As shown in FIG.
A slide carrying a GaAs wafer 1 is moved in two gases, and the p-layer growth solution layer 2 is brought into contact with the surface of the slide to grow the p-layer, and then an n-layer growth solution layer 3 is brought into contact with the surface to grow the n-layer. It was made to grow and generate.
第3図は上記第2図における炉内温度のプロファイルの
一例である。GaAsウェハ1は炉内に装着後3時間は
、GaAsウェハの格子定数をp層のA、(Asの格子
定数に近付け、さらに上記各エピタキシャル成長層を厚
く生成するため850℃以上の高温に保たれる。ちなみ
に、GaAsとAlAsの格子定数は950℃で一致す
る。次いで温度を800℃まで徐々に下げてp層を成長
させ、さらに温度を700℃まで徐冷してn層を成長さ
せていた。FIG. 3 is an example of the furnace temperature profile shown in FIG. 2 above. The GaAs wafer 1 was kept at a high temperature of 850° C. or higher for 3 hours after being placed in the furnace in order to bring the lattice constant of the GaAs wafer close to that of the p-layer A and (As) and to form each of the above epitaxial growth layers thickly. By the way, the lattice constants of GaAs and AlAs match at 950°C.Then, the temperature was gradually lowered to 800°C to grow the p-layer, and then the temperature was gradually cooled to 700°C to grow the n-layer. .
[発明が解決しようとする課題]
上記従来の製造方法では、800℃以上の高温において
はGaAsウェハ1内のAs成分の蒸気圧が高くなるた
め、H2ガスにさらされるとAs原子がウェハ表面から
抜けて表面荒れを起こすという問題があった。[Problems to be Solved by the Invention] In the conventional manufacturing method described above, the vapor pressure of the As component in the GaAs wafer 1 increases at high temperatures of 800°C or higher, so when exposed to H2 gas, As atoms are removed from the wafer surface. There was a problem that the particles would come off and cause surface roughness.
上記As原子の抜けが激しいと、ウエノ1が反り、ビッ
ト部分から割れが発生するようになる。If the As atoms drop out too much, the wafer 1 will warp and cracks will occur from the bit portion.
また、Asが抜けた後にAsサイトの空孔(Vas)が
生成され、これがドナーとして働き、p層のアクセプタ
を補償してキャリア濃度を低下させて高抵抗層を形成し
、LEDとしての発光強度を低下させるようになる。In addition, after As escapes, As site vacancies (Vas) are generated, which act as donors, compensate for the acceptors in the p-layer, lower the carrier concentration, and form a high-resistance layer, which increases the light emission intensity as an LED. It starts to decrease.
第4図は上記約850℃のH2ガス中に放置したp型G
aAsウェハ表面における上記キャリア濃度の測定例で
あり、表面のキャリア濃度が著しく低下していることが
わかる。Figure 4 shows the p-type G left in H2 gas at about 850°C.
This is an example of measuring the carrier concentration on the surface of an aAs wafer, and it can be seen that the carrier concentration on the surface is significantly reduced.
本発明の目的は、上記As原子の抜けを補償して、ウェ
ハの反り、ビット部分から割れ、高抵抗層の形成のない
p型GaAsウェハを提供することにある。An object of the present invention is to provide a p-type GaAs wafer that compensates for the above-mentioned omission of As atoms and is free from warping of the wafer, cracking from the bit portion, and formation of a high-resistance layer.
[課題を解決するための手段]
本発明は上記課題を解決するために、p型GaAsウェ
ハを蒸気圧700 torr以上、温度800乃至12
00℃の砒素雰囲気にて10乃至50時間表面処理して
、表面の砒素濃度を予め高め、次いで上記GaAsウェ
ハ表面をエツチングおよびポリッシングにより鏡面仕上
げするようにする。[Means for Solving the Problems] In order to solve the above problems, the present invention provides a p-type GaAs wafer at a vapor pressure of 700 torr or more and a temperature of 800 to 12 torr.
The surface of the GaAs wafer is treated in an arsenic atmosphere at 00° C. for 10 to 50 hours to increase the arsenic concentration on the surface, and then the GaAs wafer surface is etched and polished to a mirror finish.
[作用]
以上のように構成した本発明のp型GaAsウェハは、
表面の過剰なAs濃度がエピタキシ法によるpn接合生
成プロセスの高温(850℃)予備加熱における表面部
Asの抜けを補償し、ウェハの反り、同割れ、高抵抗層
の形成等を防止し、さらに、上記ウェハを用いたLED
の発光強度低下を防止する。[Function] The p-type GaAs wafer of the present invention configured as described above has the following features:
The excessive As concentration on the surface compensates for the omission of As on the surface during high-temperature (850°C) preheating in the pn junction production process using the epitaxy method, and prevents wafer warping, cracking, and formation of a high-resistance layer. , LED using the above wafer
prevents a decrease in luminescence intensity.
[実施例]
第1図は本発明によるp型GaAsウェハ上にAsをド
ープする装置の断面図である。Znを5×1018〜5
×10190m−3ドープしたp型GaAsインゴット
を略400〜500μmの厚さにスライスした複数のウ
ェハ1を石英製のウエノ1キャリア10に立て、石英製
アンプル5内に封止する。石英製アンプル5内の他端に
は金属As4が封止される。金属As4はAs圧制御ヒ
ータ7により加熱されて蒸発し、各ウェハ1の表面から
その内部に侵入する。Asガスの圧力はAs圧制御ヒー
タ7の温度やAs拡散障壁8により制御される。このよ
うなAsガス圧力下にて、各ウェハ1をアニール用ヒー
タ6により800〜1200℃で10〜50時間アニー
ル処理して各ウェハの表面に所要のAs原子を注入する
。[Example] FIG. 1 is a sectional view of an apparatus for doping As onto a p-type GaAs wafer according to the present invention. Zn 5×1018~5
A plurality of wafers 1 obtained by slicing a p-type GaAs ingot doped with x10190 m-3 to a thickness of about 400 to 500 μm are stood up on a wafer 1 carrier 10 made of quartz and sealed in an ampoule 5 made of quartz. The other end of the quartz ampoule 5 is sealed with metal As4. The metal As4 is heated by the As pressure control heater 7, evaporates, and enters the inside of each wafer 1 from the surface thereof. The pressure of the As gas is controlled by the temperature of the As pressure control heater 7 and the As diffusion barrier 8. Under such As gas pressure, each wafer 1 is annealed using an annealing heater 6 at 800 to 1200° C. for 10 to 50 hours to implant the required As atoms into the surface of each wafer.
その後、ウェハ1を石英製アンプル5内より取り出し、
表面にラッピング、エツチング、ポリッシング処理等を
施して鏡面研磨する。上記鏡面研磨の深さは30〜50
μm程度であり、これによりウェハ表面上の過度に過剰
なAs層が取り除かれる。After that, the wafer 1 is taken out from the quartz ampoule 5,
The surface is polished to a mirror finish by lapping, etching, polishing, etc. The depth of the mirror polishing above is 30 to 50
.mu.m, which removes the excessively excessive As layer on the wafer surface.
第5図は上記本発明によって得られたウェハのAsとG
aの組成比測定例である。明らかに、表面から略30μ
mまでのAs濃度が過剰になっており、これにより上記
エピタキシ法によるpn接合生成時の表面部Asの抜け
を補償することが出来るのである。実験によると、上記
本発明によるウェハを上記エピタキシ法によるpn接合
生成時の予備加熱とほぼ同一の850℃のH2ガス雰囲
気中で3時間放置したところ、従来製法によるウェハに
比べて表面の荒れやピットの発生数が著しく減少してい
ることがわかった。FIG. 5 shows As and G of the wafer obtained by the above invention.
This is an example of measuring the composition ratio of a. Apparently, about 30μ from the surface
Since the As concentration up to m is excessive, it is possible to compensate for the omission of As in the surface portion when the pn junction is formed by the epitaxy method. According to experiments, when the wafer according to the present invention was left for 3 hours in an H2 gas atmosphere at 850°C, which is almost the same as the preheating used when forming a pn junction by the epitaxy method, the surface roughness and roughness were observed compared to wafers manufactured using the conventional method. It was found that the number of pits was significantly reduced.
第6図はシングルへテロのLEDの発光強度を上記本発
明によるウェハにより製作したものと従来のウェハによ
り製作したものにつき比較したデータである。これより
、本発明のウェハを用いれば従来LEDにくらべて発光
強度を略30%増加できることがわかる。FIG. 6 shows data comparing the luminous intensity of single hetero LEDs manufactured using the wafer according to the present invention and those manufactured using conventional wafers. From this, it can be seen that by using the wafer of the present invention, the light emission intensity can be increased by about 30% compared to the conventional LED.
[発明の効果コ
本発明によれば、ウェハ表面の過剰なAs濃度がエピタ
キシ法によるpn接合生成プロセスにおける表面部As
の抜けを補償するので、反り、同割れ、高抵抗層の形成
等を防止した良質のGaASウェハを歩留まり良く提供
することができる。[Effects of the Invention] According to the present invention, excessive As concentration on the wafer surface is reduced to surface As in the pn junction generation process by epitaxy.
Since the missing part is compensated for, it is possible to provide high-quality GaAS wafers with a high yield, which prevents warping, cracking, formation of high-resistance layers, etc.
さらに、上記本発明のp型GaAsウェハを用いること
により発光強度が従来品より略30%増加したLEDを
提供することができる。Furthermore, by using the p-type GaAs wafer of the present invention, it is possible to provide an LED whose emission intensity is approximately 30% higher than that of conventional products.
第1図は本発明によるp型GaAsウェハ加工装置の断
面図、第2図はp型GaAsウェハ表面にpn接合を生
成する従来装置の部分断面図、第3図は第2図の装置に
おける温度プロファイル図、第4図は従来のp型GaA
sウェハ表面の測定データ、第5図は本発明のp型Ga
Asウェハ表面の測定データ、第6図は本発明と従来の
p型GaAsウェハを用いたLEDの発光強度比較デー
タである。
: GaAsウェハ、
=p層成長溶液層、
=n層成長溶液層、
:金属GaAs。
:石英アンプル、
ニアニール用ヒータ、
:AS圧制御ヒータ、
:As拡散障壁、
在帽制姥
(貿寝ジ)FIG. 1 is a cross-sectional view of a p-type GaAs wafer processing device according to the present invention, FIG. 2 is a partial cross-sectional view of a conventional device for forming a pn junction on the surface of a p-type GaAs wafer, and FIG. 3 is a temperature diagram of the device shown in FIG. Profile diagram, Figure 4 is a conventional p-type GaA
s wafer surface measurement data, Figure 5 shows the p-type Ga of the present invention.
FIG. 6 shows the measurement data of the As wafer surface and the comparison data of the light emission intensity of LEDs using the present invention and a conventional p-type GaAs wafer. : GaAs wafer, = p-layer growth solution layer, = n-layer growth solution layer, : metallic GaAs. : Quartz ampoule, near-annealing heater, : AS pressure control heater, : As diffusion barrier, trade cap system
Claims (1)
たことを特徴とするp型GaAsウェハ。 2、導電性がp型であるGaAsウェハを蒸気圧700
torr以上、温度800乃至1200℃の砒素雰囲気
にて10乃至50時間熱処理し、次いで上記GaAsウ
ェハ表面をエッチングおよびポリッシングにより鏡面仕
上げすることを特徴とする表面が砒素過剰のGaAsウ
ェハの製造方法。[Claims] 1. A p-type GaAs wafer characterized in that the arsenic concentration on the surface is increased relative to the arsenic concentration inside. 2. A GaAs wafer with p-type conductivity is heated to a vapor pressure of 700
A method for producing a GaAs wafer with an arsenic-excessive surface, the method comprising heat-treating the GaAs wafer in an arsenic atmosphere at a temperature of 800 to 1200° C. for 10 to 50 hours, and then mirror-finishing the surface of the GaAs wafer by etching and polishing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2110819A JPH0410432A (en) | 1990-04-26 | 1990-04-26 | Gaas wafer and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2110819A JPH0410432A (en) | 1990-04-26 | 1990-04-26 | Gaas wafer and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0410432A true JPH0410432A (en) | 1992-01-14 |
Family
ID=14545464
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2110819A Pending JPH0410432A (en) | 1990-04-26 | 1990-04-26 | Gaas wafer and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0410432A (en) |
-
1990
- 1990-04-26 JP JP2110819A patent/JPH0410432A/en active Pending
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