JPH0410432A - Gaas wafer and manufacture thereof - Google Patents

Abstract

PURPOSE:To compensate omission of As atoms and to obtain a p-type GaAs wafer having no warpage, no crack from a bit part, and no formation of a high resistance layer by previously increasing arsenic concentration of a surface, and then mirror-finishing the surface of the wafer by etching and polishing. CONSTITUTION:Metal As 4 is sealed in the other end in a quartz ampule 5. The As 4 is heated by an As pressure control heater 7, evaporated, and invaded thereinto from the surface of the wafer 1. The pressure of As gas is controlled by the temperature of the heater 7 and an As diffusion barrier 8. The wafer 1 is annealed at 800-1200 deg.C for 10-50 hours by an annealing heater 6 even under such As gas pressure to implant predetermined As atoms on the wafer. Then, the wafer 1 is removed from the ampule 5, the surface is lapped, etched, polished to be mirror-finished. Thus, excessive As layer on the wafer is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a p-type GaAs wafer and a surface treatment method thereof.

[Prior art] As shown in FIG.
A slide carrying a GaAs wafer 1 is moved in two gases, and the p-layer growth solution layer 2 is brought into contact with the surface of the slide to grow the p-layer, and then an n-layer growth solution layer 3 is brought into contact with the surface to grow the n-layer. It was made to grow and generate.

FIG. 3 is an example of the furnace temperature profile shown in FIG. 2 above. The GaAs wafer 1 was kept at a high temperature of 850° C. or higher for 3 hours after being placed in the furnace in order to bring the lattice constant of the GaAs wafer close to that of the p-layer A and (As) and to form each of the above epitaxial growth layers thickly. By the way, the lattice constants of GaAs and AlAs match at 950°C.Then, the temperature was gradually lowered to 800°C to grow the p-layer, and then the temperature was gradually cooled to 700°C to grow the n-layer. .

[Problems to be Solved by the Invention] In the conventional manufacturing method described above, the vapor pressure of the As component in the GaAs wafer 1 increases at high temperatures of 800°C or higher, so when exposed to H2 gas, As atoms are removed from the wafer surface. There was a problem that the particles would come off and cause surface roughness.

If the As atoms drop out too much, the wafer 1 will warp and cracks will occur from the bit portion.

In addition, after As escapes, As site vacancies (Vas) are generated, which act as donors, compensate for the acceptors in the p-layer, lower the carrier concentration, and form a high-resistance layer, which increases the light emission intensity as an LED. It starts to decrease.

Figure 4 shows the p-type G left in H2 gas at about 850°C.
This is an example of measuring the carrier concentration on the surface of an aAs wafer, and it can be seen that the carrier concentration on the surface is significantly reduced.

An object of the present invention is to provide a p-type GaAs wafer that compensates for the above-mentioned omission of As atoms and is free from warping of the wafer, cracking from the bit portion, and formation of a high-resistance layer.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a p-type GaAs wafer at a vapor pressure of 700 torr or more and a temperature of 800 to 12 torr.
The surface of the GaAs wafer is treated in an arsenic atmosphere at 00° C. for 10 to 50 hours to increase the arsenic concentration on the surface, and then the GaAs wafer surface is etched and polished to a mirror finish.

[Function] The p-type GaAs wafer of the present invention configured as described above has the following features:
The excessive As concentration on the surface compensates for the omission of As on the surface during high-temperature (850°C) preheating in the pn junction production process using the epitaxy method, and prevents wafer warping, cracking, and formation of a high-resistance layer. , LED using the above wafer
prevents a decrease in luminescence intensity.

[Example] FIG. 1 is a sectional view of an apparatus for doping As onto a p-type GaAs wafer according to the present invention. Zn 5×1018~5
A plurality of wafers 1 obtained by slicing a p-type GaAs ingot doped with x10190 m-3 to a thickness of about 400 to 500 μm are stood up on a wafer 1 carrier 10 made of quartz and sealed in an ampoule 5 made of quartz. The other end of the quartz ampoule 5 is sealed with metal As4. The metal As4 is heated by the As pressure control heater 7, evaporates, and enters the inside of each wafer 1 from the surface thereof. The pressure of the As gas is controlled by the temperature of the As pressure control heater 7 and the As diffusion barrier 8. Under such As gas pressure, each wafer 1 is annealed using an annealing heater 6 at 800 to 1200° C. for 10 to 50 hours to implant the required As atoms into the surface of each wafer.

After that, the wafer 1 is taken out from the quartz ampoule 5,
The surface is polished to a mirror finish by lapping, etching, polishing, etc. The depth of the mirror polishing above is 30 to 50
.mu.m, which removes the excessively excessive As layer on the wafer surface.

FIG. 5 shows As and G of the wafer obtained by the above invention.
This is an example of measuring the composition ratio of a. Apparently, about 30μ from the surface
Since the As concentration up to m is excessive, it is possible to compensate for the omission of As in the surface portion when the pn junction is formed by the epitaxy method. According to experiments, when the wafer according to the present invention was left for 3 hours in an H2 gas atmosphere at 850°C, which is almost the same as the preheating used when forming a pn junction by the epitaxy method, the surface roughness and roughness were observed compared to wafers manufactured using the conventional method. It was found that the number of pits was significantly reduced.

FIG. 6 shows data comparing the luminous intensity of single hetero LEDs manufactured using the wafer according to the present invention and those manufactured using conventional wafers. From this, it can be seen that by using the wafer of the present invention, the light emission intensity can be increased by about 30% compared to the conventional LED.

[Effects of the Invention] According to the present invention, excessive As concentration on the wafer surface is reduced to surface As in the pn junction generation process by epitaxy.
Since the missing part is compensated for, it is possible to provide high-quality GaAS wafers with a high yield, which prevents warping, cracking, formation of high-resistance layers, etc.

Furthermore, by using the p-type GaAs wafer of the present invention, it is possible to provide an LED whose emission intensity is approximately 30% higher than that of conventional products.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a p-type GaAs wafer processing device according to the present invention, FIG. 2 is a partial cross-sectional view of a conventional device for forming a pn junction on the surface of a p-type GaAs wafer, and FIG. 3 is a temperature diagram of the device shown in FIG. Profile diagram, Figure 4 is a conventional p-type GaA
s wafer surface measurement data, Figure 5 shows the p-type Ga of the present invention.
FIG. 6 shows the measurement data of the As wafer surface and the comparison data of the light emission intensity of LEDs using the present invention and a conventional p-type GaAs wafer. : GaAs wafer, = p-layer growth solution layer, = n-layer growth solution layer, : metallic GaAs. : Quartz ampoule, near-annealing heater, : AS pressure control heater, : As diffusion barrier, trade cap system

Claims (1)

[Claims] 1. A p-type GaAs wafer characterized in that the arsenic concentration on the surface is increased relative to the arsenic concentration inside. 2. A GaAs wafer with p-type conductivity is heated to a vapor pressure of 700
A method for producing a GaAs wafer with an arsenic-excessive surface, the method comprising heat-treating the GaAs wafer in an arsenic atmosphere at a temperature of 800 to 1200° C. for 10 to 50 hours, and then mirror-finishing the surface of the GaAs wafer by etching and polishing.