JP3748011B2 - GaN semiconductor crystal growth Si wafer, the wafer and a process for their preparation for the GaN light emitting device using the same - Google Patents

GaN semiconductor crystal growth Si wafer, the wafer and a process for their preparation for the GaN light emitting device using the same Download PDF

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JP3748011B2
JP3748011B2 JP16483599A JP16483599A JP3748011B2 JP 3748011 B2 JP3748011 B2 JP 3748011B2 JP 16483599 A JP16483599 A JP 16483599A JP 16483599 A JP16483599 A JP 16483599A JP 3748011 B2 JP3748011 B2 JP 3748011B2
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wafer
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JP2000351692A (en
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秀夫 中西
一高 寺嶋
鈴香 西村
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一高 寺嶋
東芝セラミックス株式会社
鈴香 西村
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【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、青色の発光素子(例えば、発光ダイオード(LED)やレーザ素子)を作るためのGaN(窒化ガリウム)半導体結晶成長用Si(シリコン)ウエーハ、それを用いたGaN発光素子用ウエーハ及びそれらの製造方法に関する。 The present invention, blue light-emitting elements (e.g., light emitting diode (LED) or a laser device) GaN (gallium nitride) semiconductor crystal growth Si (silicon) wafer for making, GaN light-emitting device wafer and those using the same a method for manufacturing.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
通常、青色の発光素子としてのGaN半導体結晶は、サファイア基板上にエピタキシャル成長によって育成されているが、GaN半導体結晶とサファイア基板の格子定数の差異による格子不整合を生じたり、基板としてのサファイアが劈開性、導電性を有しないことによる不具合がある。 Usually, the GaN semiconductor crystal as a blue light emitting element, has been grown by epitaxial growth on a sapphire substrate, or resulting lattice mismatch due to the difference of the lattice constant of GaN semiconductor crystal and the sapphire substrate, the sapphire as substrate cleavage there is a problem of not having sex, conductivity.
【0003】 [0003]
従来、かかる不具合を解消するため、図7に示すように、基板としてSiを用い、Si基板31上にGa(ガリウム)のバリア層32を介在してGaN半導体結晶層33を形成するGaN発光素子用ウエーハとその製造方法が知られている(特開平10−242055号公報参照)。 Conventionally, such order to solve the problem, as shown in FIG. 7, using Si as a substrate, GaN light-emitting element for forming a GaN semiconductor crystal layer 33 by interposing a barrier layer 32 of Ga (gallium) on the Si substrate 31 use wafer and a manufacturing method thereof are known (see Japanese Patent Laid-Open No. 10-242055).
【0004】 [0004]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
しかし、従来のGaN発光素子用ウエーハとその製造方法では、Si基板上へのGaのバリア層の形成は、両者の格子定数の大幅な違いにより不具合があり、Gaのバリア層上への閃亜鉛鉱型結晶構造のGaN層の形成が困難で、GaN層の結晶構造がウルツ鉱型の結晶系となり、発光素子としての青色発光時の輝度があまりあがらない不具合がある。 However, in the conventional GaN-based light emitting device for wafer and its manufacturing method, formation of the barrier layer of Ga on the Si substrate, there is a problem with significant differences in both the lattice constants, sphalerite to Ga in the barrier layer formation of the GaN layer of blende crystal structure is difficult, the crystal structure of the GaN layer becomes crystalline wurtzite, brightness in blue light as the light emitting element is a defect that seldom go up.
【0005】 [0005]
このため、Si基板とGaN層の中間層としてウルツ鉱型結晶構造のGaNと格子不整合が僅か0.6%程度のBP(リン化ホウ素)単結晶を用いることが考えられる。 Thus, GaN is lattice mismatched wurtzite crystal structure can be considered to use only 0.6% of BP (boron phosphide) monocrystal as an intermediate layer of Si substrate and the GaN layer.
BP単結晶は、中性子の吸収作用があり、原子炉の安全管理や中性子線散乱による物性評価のための中性子線センサーとしての用途が期待され研究が行われている。 BP single crystal, there is absorption of neutrons, use as a neutron ray sensor for the evaluation of the physical properties due to safety management and neutron-ray scattering of the reactor is being carried out are expected to study.
BPは、閃亜鉛鉱型結晶構造を有し、GaNとの格子不整合も前述したように僅かである。 BP has a zinc blende type crystal structure, lattice mismatch with GaN is very small as described above. 一方、Siとの格子不整合が16%と大きいが、B(ホウ素)とSiとの相性がよく、Si基板上へのBPのエピタキシャル成長が報告されているものの、未だ安定的な結晶成長を行えるまでには至っていない。 On the other hand, the lattice mismatch between Si is as large as 16%, B (boron) and good compatibility with the Si, although the epitaxial growth of BP on Si substrates has been reported, can be performed still stable crystal growth not reached before.
その理由として、下記の要因が挙げられる。 The reasons include the following factors.
(1)BPのエピタキシャル成長プロセス中に、Si基板に含まれるO(酸素)が外方拡散し、Bを酸化するため、多結晶化が起こり単結晶成長を阻害する。 (1) during the epitaxial growth process of BP, O (oxygen) included in the Si substrate diffuse outwardly, for the oxidation of B, polycrystallization occurs inhibit single crystal growth.
(2)Si基板34(図8、図9参照)の表面、すなわち、デバイス製作面にCOP(Crystal Originated Paricle :ごく軽いエッチングで形成されるピット(0.5μmぐらいの小孔))等の欠陥35があると、結晶方位の違いによりBPの成長速度に差異が生じ、表面の凹凸が増幅され、表面の均一性(平面度)を欠いてしまう。 (2) Si substrate 34 (see FIGS. 8 and 9) the surface of, i.e., COP the device fabrication surface (Crystal Originated Paricle: pits formed in a very mild etching (about the stoma 0.5 [mu] m)) defects such as If there is 35, a difference in the growth rate of BP due to the difference in crystal orientation is caused, it is amplified surface irregularities, resulting in lack surface uniformity (flatness).
(3)Si基板36(図10参照)の表面がシングルステップレーヤの場合、BPの結晶成長中に、A−A面でフェースの異なるアンチフェーズドドメインが生じ多結晶化する。 (3) If the surface of the Si substrate 36 (see FIG. 10) is a single-step player, in the crystal growth of the BP, different anti-phased domains face at A-A plane is polycrystalline occur.
一方、上記要因を解消するため、BPエピタキシャル成長プロセスにおいて、前処理として、Si基板を水素ガス雰囲気において1000〜1200℃の温度でアニール処理することが考えられるが、処理時間が長時間となる上、高温度に保持するため、新たな表面荒れが発生する等の不具合がある。 Meanwhile, in order to solve the above-mentioned factors, the BP epitaxial growth process, pre as a process, it is considered that the Si substrate is annealed at a temperature of 1000 to 1200 ° C. in a hydrogen gas atmosphere over the processing time is long, for holding high temperature, there are problems such as new surface roughening occurs.
そこで、本発明は、閃亜鉛鉱型結晶構造のGaN層を良好に形成し得るGaN半導体結晶成長用Siウエーハ、それを用いたGaN発光素子用ウエーハ及びそれらの製造方法を提供することを目的とする。 Accordingly, the present invention is, intended to provide GaN semiconductor crystal growth Si wafer a GaN layer may be favorably formed of zinc blende type crystal structure, a GaN light-emitting device wafer and a process for their preparation using the same to.
【0006】 [0006]
【課題を解決するための手段】 In order to solve the problems]
前記課題を解決するため、前記課題を解決するため、本発明 GaN半導体結晶成長用Siウエーハは、CZ法によるSi基板の表面から厚み方向へ少なくとも3μmの間に亘って低酸度濃度で酸素析出物が無く、かつ、表面構造が全面に亘ってダブルステップレーヤとなっており、該Si基板の表面にBP単結晶層が形成されていることを特徴とする。 To solve the above problems, in order to solve the above problems, GaN semiconductor crystal growth Si wafer of the present invention, the oxygen precipitates at a low acidity concentrations over a period of at least 3μm from the surface to the thickness direction of the Si substrate by the CZ method things without and surface structure has a double step player over the entire surface, characterized in that the BP single crystal layer is formed on the surface of the Si substrate.
前記Si基板の表面から厚み方向へ少なくとも5μmの間に亘る酸素濃度は1.0×10 17 atoms/cm 3以下で、残部の酸素濃度は5.0×10 17 〜1.0×10 18 atoms/cm 3であることが好ましい。 The Si concentration of oxygen over a period of at least 5μm from the surface to the thickness direction of the substrate is 1.0 × 10 17 atoms / cm 3 or less, the oxygen concentration of the remainder 5.0 × 10 17 ~1.0 × 10 18 atoms it is preferably / cm 3.
又、前記Si基板の表面にはCOP等のピットが存在しないことが好ましい。 Further, the surface of the Si substrate is preferably no pits such as COP.
、GaN発光素子用ウエーハは、 前記 GaN半導体結晶成長用Siウエーハにおいて、BP単結晶層の上に閃亜鉛鉱型結晶構造のGaN層が形成されていることを特徴とする。 Also, wafers for GaN light-emitting element, in the GaN semiconductor crystal growth Si wafer, wherein the GaN layer of zinc blende type crystal structure on the BP single crystal layer is formed.
【0007】 [0007]
一方、 本発明のGaN半導体結晶成長用Siウエーハの製造方法は、CZ法によるSi単結晶からなるSi基板に水素ガス雰囲気において800〜1300℃の温度でアニール処理を施した後、1050〜1150℃の温度でSiのエピタキシャル成長を施し、該Si基板の表面にBPのエピタキシャル成長を施すことを特徴とする。 On the other hand, the method of manufacturing GaN semiconductor crystal growth Si wafer of the present invention, was subjected to annealing treatment at a temperature of 800 to 1300 ° C. in a hydrogen gas atmosphere Si substrate made of Si single crystal by the CZ method, 1050-1150 ° C. temperature subjected to epitaxial growth of Si in the, and characterized by applying an epitaxial growth of BP on the surface of the Si substrate.
前記Si基板は表面にCOP等のピットの無いものとすることが好ましい。 The Si substrate is preferable to be those without pit COP or the like on the surface.
前記Si単結晶は抵抗値5/1000〜15/1000ΩcmのBヘビードープP +シリコン単結晶とすることが好ましい。 It is preferable that the Si single crystal to B heavily doped P + silicon single crystal of the resistance value 5 / 1000~15 / 1000Ωcm.
、GaN発光素子用ウエーハの製造方法は、第2のGaN半導体結晶成長用ウエーハの製造方法において、BP単結晶層の上に閃亜鉛鉱型結晶構造のGaNのエピタキシャル成長を施すことを特徴とする。 In the method of manufacturing a wafer for GaN light-emitting element is the manufacturing method of the second GaN semiconductor crystal growth wafer, and wherein applying the GaN epitaxial growth of zinc blende type crystal structure on the BP single crystal layer .
【0008】 [0008]
Si基板の表面から厚み方向へ少なくとも3μmの間に亘って酸素濃度が高くて酸素析出物が有ると、BP層のエピタキシャル成長プロセスにおいて、Si基板中の酸素が外方拡散してBを酸化するため、多結晶化が起こりBPの単結晶成長を阻害する。 When the oxygen concentration over a period of at least 3μm from the surface to the thickness direction of the Si substrate by high oxygen precipitates are present in the epitaxial growth process of the BP layer, since the oxygen in the Si substrate is oxidized to B diffuses outward , multi-crystallization occurs to inhibit the single crystal growth of BP.
低酸素濃度で酸素析出物の無い領域は、表面から厚み方向へ15μmの間に亘って形成することが望ましい。 Area without oxygen precipitates at a low oxygen concentration is desirably formed over between 15μm from the surface to the thickness direction.
表面から厚み方向へ少なくとも5μmの間に亘る酸素濃度は、8×10 16 atoms /cm 3以下であることが望ましい。 At least 5μm oxygen concentration ranging between from the surface to the thickness direction is desirably 8 × 10 16 atoms / cm 3 or less.
【0009】 [0009]
水素ガス雰囲気におけるSi基板のアニール処理温度が、800℃未満であると、表面変化は少なくなる、一方、1300℃を超えると、表面が荒れる不具合がある。 Annealing temperature of the Si substrate in a hydrogen gas atmosphere is less than 800 ° C., the surface change is reduced, while when it exceeds 1300 ° C., there is a surface rough defect.
好ましいアニール処理温度は、900〜1250℃である。 Preferred annealing temperature is 900 to 1250 ° C..
シリコン単結晶の抵抗値が、5/1000Ωcm未満であると、エピタキシャル中に不純物が酸素と反応する、一方、15/1000Ωcmを超えると、デバイス形成後に抵抗が大きくなりすぎる。 Resistance of the silicon single crystal is less than 5/1000 .OMEGA.cm, impurities are reacted with oxygen in the epitaxial On the other hand, when it exceeds 15/1000 .OMEGA.cm, resistance after device formation becomes too large.
好ましいシリコン単結晶の抵抗値は、6/1000〜14/1000Ωcmである。 Preferred resistance of the silicon single crystal is 6 / 1000~14 / 1000Ωcm.
【0010】 [0010]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
以下、本発明の実施の形態について具体的な実施例を参照して説明する。 It will now be described with reference to specific embodiments embodiments of the present invention.
先ず、CZ(チョクラルスキー)法により、ドーパントであるBを1.0×10 18 atoms/cm 3以上ドーピングし、6インチのBヘビードープP + Si単結晶(100)を引き上げ、スライスしてCOP等のピットが存在しないSi基板を得た。 First, the CZ (Czochralski) method, which is a dopant B doped 1.0 × 10 18 atoms / cm 3 or more, pulling the 6-inch B heavily doped P + Si single crystal (100), by slicing COP pit and the like to obtain a Si substrate that does not exist.
次に、Si基板に水素(H 2 )ガス雰囲気において800〜1300℃の温度でアニール処理施したところ、図1に示すように、表面から厚さ方向(図1においては上下方向)へ3μmの間に亘って酸素及びその析出物の全く見られないものとなった。 Next, when subjected annealed at a temperature of 800 to 1300 ° C. in hydrogen (H 2) gas atmosphere Si substrate, as shown in FIG. 1, the thickness direction from the surface (in FIG. 1 is a vertical direction) to 3μm of It became shall not observed at all of the oxygen and precipitate over between.
図1において黒点状のものが酸素析出物である。 Those black dot of an oxygen precipitate in FIG.
又、Si基板の表面から厚み方向へ5μmの間に亘る酸素濃度は、1.0×10 17 atoms/cm 3以下で、残部(バルク)の酸素濃度は、5.0×10 17 〜1.0×10 18 atoms/cm 3であり、かつ、Si基板の電気抵抗値は、5/1000〜15/1000Ωcmであった。 Further, the oxygen concentration ranging between 5μm from the surface of the Si substrate to the thickness direction, at 1.0 × 10 17 atoms / cm 3 or less, the oxygen concentration of the remainder (bulk) is, 5.0 × 10 17 ~1. 0 a × 10 18 atoms / cm 3, and the electrical resistance of the Si substrate was 5 / 1000~15 / 1000Ωcm.
【0011】 [0011]
次いで、アニール処理を施したSi基板の表面に、1050〜1150℃の温度でSiのエピタキシャル成長を施してSi単結晶層を形成した。 Then, the surface of the Si substrate subjected to annealing treatment to form a Si single crystal layer by applying an Si epitaxial growth at a temperature of from 1050 to 1150 ° C..
エピタキシャル装置は、内径50mm、長さ350mmの石英管の中央に石英でカバーされたSiCコートを施した黒鉛サセプターを納置し、その上にSi基板を載置し、外部より高周波を印加することによりサセプターを発熱させる構造のものである。 Epitaxial apparatus, an inner diameter of 50 mm, and Osame置 graphite susceptor subjected to covered SiC coated quartz in the center of the quartz tube length 350 mm, placing the Si substrate thereon, applying a high frequency from the outside by those of the structure for heating the susceptor.
又、エピタキシャル成長は、原料ガスとしてSiCl 4 (四塩化ケイ素)ガス、キャリアガスとしてH 2ガスを用い、マスフローコントローラを介して一定量炉内に導入した。 Further, epitaxial growth, SiCl 4 as a raw material gas (silicon tetrachloride) gas, a H 2 gas as a carrier gas was introduced at a constant amount furnace through a mass flow controller.
得られたSi基板は、表面構造が全面に亘ってダブルステップレーヤとなっていた。 Si substrate thus obtained had a surface structure has been a double-step player over the entire surface.
【0012】 [0012]
次に、Si基板のSi単結晶層の上に、900〜1150℃の温度でBPのエピタキシャル成長を施してGaN成長の中間層(バッファー層)としてのBP単結晶層を形成した。 Then, on the Si substrate of Si single crystal layer to form a BP single crystal layer as an intermediate layer of GaN growth (buffer layer) is subjected to BP epitaxial growth at a temperature of 900 to 1150 ° C..
エピタキシャル装置は、Siのエピタキシャル成長に用いたものと同様のものを用い、BPのエピタキシャル成長は、原料ガスとしてPCl 3 (三塩化リン)とBCl 3 (三塩化ホウ素)の混合ガス、キャリアガスとしてH 2ガスを用い、マスフローコントローラを介して一定量炉内に導入した。 Epitaxial device using the same as that used in the epitaxial growth of Si, epitaxial growth of the BP, a mixed gas of BCl and PCl 3 (phosphorus trichloride) as a source gas 3 (boron trichloride), H 2 as a carrier gas using gas was introduced at a constant amount furnace through a mass flow controller.
成長温度シーケンスを図2に示す。 The growth temperature sequence shown in Figure 2.
得られたGaN半導体結晶成長用Siウエーハは、図3に示すように、テラス状の結晶成長が行われていると共に、図4、図5に示すように、ダブルステップレーヤの表面構造のSi基板1の上にBP単結晶層2が、BP,BPと順番に4.56μmの厚みに積層され、表面が極めて均一なものとなった。 The resulting GaN semiconductor crystal growth Si wafer, as shown in FIG. 3, with a terrace-like crystal growth is carried out, as shown in FIGS. 4 and 5, Si substrate surface structure of the double-step player BP single crystal layer 2 on the 1, BP, is laminated to a thickness of 4.56μm on BP and order, the surface became extremely uniform.
【0013】 [0013]
比較のため、アニール処理とSiのエピタキシャル成長を施さない通常のミラーウエーハ(Si基板)を用い、このSi基板の表面に、上述のものと同様にBPのエピタキシャル成長を施してBP単結晶層を形成したところ、その表面の結晶構造は、図6に示すように、四角錐の島状のBPの多結晶が成長しており、表面の均一性(平面度)に欠けたものとなった。 For comparison, using the conventional mirror wafer not subjected to epitaxial growth annealing and Si (Si substrate), the surface of the Si substrate to form a BP single crystal layer is subjected to epitaxial growth of the BP in the same manner as described above where, the crystal structure of the surface, as shown in FIG. 6, polycrystalline pyramid island BP has grown, has become that lacks surface uniformity (flatness).
【0014】 [0014]
次いで、GaN半導体結晶成長用Siウエーハの表面に、700〜1100℃の温度でGaNのエピタキシャル成長を施して閃亜鉛鉱型結晶構造のGaN半導体結晶層を形成した。 Then, the surface of the Si wafer for GaN semiconductor crystal growth, thereby forming a GaN semiconductor crystal layer of zinc blende type crystal structure by performing the epitaxial growth of GaN at a temperature of 700 to 1100 ° C..
エピタキシャル装置は、Siのエピタキシャル成長に用いたものと同様のものを用い、GaNのエピタキシャル成長は、原料ガスとしてMMH(モノメチルヒドラジン)、TMG(トリメチルガリウム)ガス、キャリアガスとしてH 2 、N 2 (窒素)ガスを用い、マスフローコントローラを介して一定量炉内に導入した。 Epitaxial device using the same as that used in the epitaxial growth of Si, GaN epitaxial growth, as a source gas MMH (monomethyl hydrazine), TMG H 2 as (trimethyl gallium) gas, carrier gas, N 2 (nitrogen) using gas was introduced at a constant amount furnace through a mass flow controller.
得られたGaN発光素子用ウエーハは、GaN半導体単結晶層の表面が極めて均一で、その厚みが4μmであり、又、結晶構造が完全な閃亜鉛鉱型となっていた。 The resulting wafers for GaN light-emitting element, the surface of GaN semiconductor single crystal layer is very uniform, the thickness is 4 [mu] m, also the crystal structure has been a complete zinc-blende.
【0015】 [0015]
上記GaN発光素子用ウエーハから、GaN発光素子を切り出して発光させたところ、青色発光時の輝度が極めて高いものであった。 From the GaN light-emitting element wafer, where light is emitted by cutting out the GaN light emitting element, luminance in blue emission it was extremely high.
【0016】 [0016]
【発明の効果】 【Effect of the invention】
以上説明したように、本発明 GaN半導体結晶成長用Siウエーハとその製造方法によれば、デバイス形成用領域側が低酸素濃度で酸素析出物が無く、かつ、表面構造がダブルステップレーヤとなっているので、GaN半導体単結晶層の中間層となるBP単結晶層を、表面の均一性に優れたものとして、極めて安定的に形成することができる。 As described above, according to the Si wafer and a manufacturing method thereof for GaN semiconductor crystal growth of the present invention, the device forming region side no oxygen precipitates at a low oxygen concentration, and the surface structure becomes double step player because there, the BP single crystal layer is an intermediate layer of GaN semiconductor single crystal layer, as excellent in surface uniformity can be very stably formed.
又、 GaNに対するBPの格子不整合が僅か0.6%程度であるので、GaNの結晶構造を完全な閃亜鉛鉱型とすることができる。 In addition, since the BP of lattice mismatch with respect to GaN it is only about 0.6%, it is possible to the crystal structure of GaN and complete zincblende.
又、GaN発光素子用ウエーハとその製造方法によれば、GaN半導体単結晶の結晶構造が完全な閃亜鉛鉱型となるので、発光素子とした場合、青色発光時の輝度を極めて高いものとすることができる。 Further, according to the wafer and a manufacturing method thereof for GaN light-emitting element, the crystal structure of a GaN semiconductor single crystal is a complete zinc blende type case of the light emitting element, and very high brightness at the time of blue-emitting be able to.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】本発明に係るGaN半導体結晶成長用Siウエーハの製造方法の実施の形態の一例を示すアニール処理工程後のSiウエーハの結晶構造の電子顕微鏡写真である。 1 is an electron micrograph of the crystal structure of the Si wafer after the annealing process of an example of embodiment of the manufacturing method of the GaN semiconductor crystal growth Si wafer according to the present invention.
【図2】本発明に係るGaN半導体結晶成長用Siウエーハの製造方法の実施の形態の一例を示すBPエピタキシャル成長工程の成長温度シーケンスの説明図である。 Figure 2 is an illustration of the growth temperature sequence of BP epitaxial growth step of an example of embodiment of the manufacturing method of the GaN semiconductor crystal growth Si wafer according to the present invention.
【図3】本発明に係るGaN半導体結晶成長用Siウエーハの実施の形態の一例を示すGaN成長中間層としてのBPエピタキシャル成長後の表面の電子顕微鏡写真である。 3 is an electron microscopic photograph of the surface after BP epitaxial growth as GaN grown intermediate layer of an example embodiment of a GaN semiconductor crystal growth Si wafer according to the present invention.
【図4】本発明に係るGaN半導体結晶成長用Siウエーハの実施の形態の一例を示す模式的な部分断面図である。 4 is a schematic partial sectional view showing an example of an embodiment of a GaN semiconductor crystal growth Si wafer according to the present invention.
【図5】本発明に係るGaN半導体結晶成長用Siウエーハの実施の形態の一例を示すBPエピタキシャル成長後の断面の電子顕微鏡写真である。 5 is an electron micrograph of a cross-section after BP epitaxial growth of an example embodiment of a Si wafer for GaN semiconductor crystal growth according to the present invention.
【図6】従来のGaN半導体結晶成長用Siウエーハにエピタキシャル成長を施されたBPの結晶構造を示す電子顕微鏡写真である。 6 is an electron micrograph showing the crystal structure of a conventional GaN semiconductor crystal growth Si wafer to BP that has been subjected to epitaxial growth.
【図7】従来のGaN発光素子用ウエーハの断面図である。 7 is a cross-sectional view of a conventional GaN light-emitting element wafer.
【図8】従来のGaN半導体結晶成長用Siウエーハの部分断面図である。 8 is a partial cross-sectional view of a conventional GaN semiconductor crystal growth Si wafer.
【図9】図6のSiウエーハの平面図である。 9 is a plan view of a Si wafer of FIG.
【図10】BPがエピタキシャル成長された従来のGaN半導体結晶成長用Siウエーハの模式的な部分断面図である。 [10] BP is a schematic partial cross-sectional view of a conventional GaN semiconductor crystal growth Si wafer having an epitaxially grown.
【符号の説明】 DESCRIPTION OF SYMBOLS
1 Si基板2 BP単結晶層 1 Si substrate 2 BP single crystal layer

Claims (8)

  1. CZ法によるSi基板の表面から厚み方向へ少なくとも3μmの間に亘って低酸素濃度で酸素析出物が無く、かつ、表面構造が全面に亘ってダブルステップレーヤとなっており、該Si基板の表面にBP単結晶層が形成されていることを特徴とするGaN半導体結晶成長用Siウエーハ。 At least 3μm oxygen precipitates at a low oxygen concentration throughout the period from the surface to the thickness direction of the Si substrate by the CZ method is not, and the surface structure has a double step player over the entire surface of the Si substrate Si wafers for GaN semiconductor crystal growth, wherein the BP single crystal layer is formed.
  2. 前記Si基板の表面から厚み方向へ少なくとも5μmの間に亘る酸素濃度が1.0×10 17 atoms/cm 3以下で、残部の酸素濃度が5.0×10 17 〜1.0×10 18 atoms/cm 3であることを特徴とする請求項1記載のGaN半導体結晶成長用Siウエーハ。 The Si concentration of oxygen over a period of at least 5μm from the surface to the thickness direction of the substrate is at 1.0 × 10 17 atoms / cm 3 or less, the oxygen concentration of the balance 5.0 × 10 17 ~1.0 × 10 18 atoms GaN semiconductor crystal growth Si wafer according to claim 1, characterized in that the / cm 3.
  3. 前記Si基板の表面にCOP等のピットが存在しないことを特徴とする請求項1又は2記載のGaN半導体結晶成長用Siウエーハ。 Claim 1 or 2 GaN semiconductor crystal growth Si wafer, wherein an absence of pits COP or the like on the surface of the Si substrate.
  4. 請求項1、2又は3記載のSiウエーハにおいて、BP単結晶層の上に閃亜鉛鉱型結晶構造のGaN層が形成されていることを特徴とするGaN発光素子用ウエーハ。 In Si wafer according to claim 1, wherein, BP single crystal layer wafer for GaN light-emitting element, wherein the GaN layer of zinc blende type crystal structure is formed on the.
  5. CZ法によるSi単結晶からなるSi基板に水素ガス雰囲気において800〜1300℃の温度でアニール処理を施した後、1050〜1150℃の温度でSiのエピタキシャル成長を施し、該Si基板の表面にBPのエピタキシャル成長を施すことを特徴とするGaN半導体結晶成長用Siウエーハの製造方法。 After annealed at a temperature of 800 to 1300 ° C. in a hydrogen gas atmosphere Si substrate made of Si single crystal by the CZ method, subjecting an Si epitaxial growth at a temperature of 1,050 to 1,150 ° C., the BP to the surface of the Si substrate method for producing a Si wafer for GaN semiconductor crystal growth, characterized in that performing an epitaxial growth.
  6. 前記Si基板を表面にCOP等のピットの無いものとすることを特徴とする請求項記載のGaN半導体結晶成長用Siウエーハの製造方法。 Method of manufacturing a GaN semiconductor crystal growth Si wafer of claim 5, wherein the assumed no pits such as COP the Si substrate to the surface.
  7. 前記Si単結晶を抵抗値5/1000〜15/1000ΩcmのBヘビードープP +シリコン単結晶とすることを特徴とする請求項又は記載のGaN半導体結晶成長用Siウエーハの製造方法。 Method for producing a Si single crystal resistance 5 / 1,000-15/1000 .OMEGA.cm of B heavily doped P + silicon single crystals characterized by claim 5 or 6 GaN semiconductor crystal growth Si wafer according.
  8. 請求項5、6又は7記載のSiウエーハの製造方法において、BP単結晶層の上に閃亜鉛鉱型結晶構造のGaNのエピタキシャル成長を施すことを特徴とするGaN発光素子用ウエーハの製造方法。 The method of manufacturing a Si wafer of claim 5, 6 or 7, wherein the production method of a wafer for GaN light-emitting device characterized by subjecting a GaN epitaxial growth of zinc blende type crystal structure on the BP single crystal layer.
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