JPH04103238A - Phase hold circuit - Google Patents

Abstract

PURPOSE:To prevent phase jump, phase squeeze and phase deviation by correcting intermittently a change in a phase difference caused when an output phase of a serial data is kept constant so as to make the output phase close to an initial setting value. CONSTITUTION:The circuit is provided with a delay comparison section 9 which compares a delay quantity decided by an adder subtraction section 7 designating a delay of a variable delay section 1 with an initial setting delay and validates the adder subtraction section 7 based on the result of comparison. A phase difference between a synchronizing signal in an output data of the delay section 1 and an internal reference signal generated through frequency division by a highly stable crystal oscillation section 2 is measured relatively and only a change is inputted to the adder subtraction section 7, in which the absolute value is obtained and it is compared with information of the initial setting value and when the absolute value is changed, the adder subtraction section 7 is controlled so that the absolute value is made close to the initial setting value little by little timewise or equal thereto. Thus, a phase jump, a phase squeeze and a phase change due to jitter of a data and accuracy difference of a crystal oscillation section are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a data transmission device. In particular, it relates to a device that keeps the output phase of serial data constant.

〔overview〕

The present invention is a means for keeping the output phase of serial data constant, and eliminates phase jumps, phase jams, and phase shifts by intermittently correcting changes in the phase difference that occur and bringing the output phase closer to the initial setting value. It is designed to be able to suppress the

[Conventional technology]

Conventionally, in order to keep the output phase of serial data constant, a phase comparison between the output data phase of the delay section and the internal reference signal, which is the frequency divider output from the highly stable crystal oscillator section, was performed.
The output of the frequency divider is synchronized with the synchronization signal in the input data of the delay section, the absolute value of the phase difference is determined by the phase amount measurement section, and the pulses corresponding to the absolute amount are counted by the frequency divider and the amount of delay is changed. phase holding operation was performed.

[Problem to be solved by the invention]

In such conventional examples, the amount of delay that can be varied in the delay unit is finite, and when the absolute amount of phase increases and the frequency divider exceeds the maximum count, the amount of delay becomes zero, and the amount of delay increases. When the absolute value of the phase amount decreases from the maximum direction to the minimum direction, the phase suddenly jumps from the minimum direction to the maximum direction. For this reason, even if the phase jump is improved by prohibiting the phase from going above or below a certain amount, the phase holding operation will stop at the minimum or maximum value, resulting in a phenomenon of phase jamming. Furthermore, a phenomenon occurs in which the phase changes little by little due to the influence of accuracy differences between human input data and the crystal oscillator, jitter generated by the transmission path, etc.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase holding circuit that eliminates such drawbacks and can suppress the occurrence of phase jumps, phase jams, and phase shifts.

[Means to solve the problem]

The present invention provides a phase holding circuit that includes a variable delay section that delays an incoming serial data signal by a specified amount of delay, and a synchronization circuit that extracts a synchronization signal from a serial data signal that has passed through the variable delay section. a signal detection section;
an internal reference signal generation section that generates an internal reference signal; a phase amount measurement section that measures the phase difference between this internal reference signal and the synchronization signal extracted by the synchronization signal detection section; The addition/subtraction section adds or subtracts the amount of change in phase difference to the initial setting delay amount to specify the delay amount of the variable delay section, and the delay amount determined by this addition/subtraction section is compared with the initial setting delay amount. The present invention is characterized by comprising a delay amount comparison section that intermittently enables the addition/subtraction section based on the comparison result. Here, the internal reference signal generation section may be configured as a crystal oscillation section and a frequency divider section.

[Effect]

The amount of phase difference between the synchronization signal in the output data of the delay section and the internal reference signal created by frequency division from a highly stable crystal oscillation section is measured relatively, and only the amount of change is input to the addition/subtraction section to calculate the absolute value. The amount is determined, information on this absolute amount and the initial setting amount is compared, and when the absolute amount changes, the adding/subtracting unit is controlled so that it approaches or becomes equal to the initial setting amount over time little by little when the absolute amount changes.

This makes it possible to improve the phenomena of phase jumps, phase jams, and phase changes due to precision differences in crystal oscillators and data jitter.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. The figure is a block diagram of this embodiment. As shown in the figure, this embodiment includes a variable delay section 1 that delays an incoming serial data signal by a specified amount of delay. 1, a crystal oscillator 2 and a frequency divider 4, which are internal reference signal generators that generate internal reference signals, and and a phase amount measuring unit 5 that calculates the phase difference between the synchronizing signal and the synchronizing signal extracted by the synchronizing signal detecting unit 6;
An addition/subtraction unit 7 adds or subtracts the change in the phase difference obtained by the phase amount measurement unit 5 to the initial setting delay amount to specify the delay amount of the variable delay unit 1; The delay amount comparison section 9 compares the delay amount with the initial setting delay amount and intermittently enables the addition/subtraction section 7 based on the comparison result.

Next, the operation of this embodiment will be explained. The synchronous reproduction section 3 counts down the oscillation frequency of the crystal oscillation section 2 and generates a clock pulse synchronized with input data. First, the initial setting delay amount from the initial phase setting section 8 is given to the adding/subtracting section 7, and the variable delay section 1 is set to the initial value. The output of the variable delay section 1 is given to the synchronization signal detection section 6 to detect the timing of the synchronization signal. Two of the signals (hereinafter referred to as internal reference signals) are supplied to the phase amount measuring section 5. At the same time that the variable delay section 1 is set to the initial value, the phases of the two signals supplied to the phase amount measuring section 5, namely the timing of the synchronization signal and the internal reference signal, are matched under the control of the initial phase setting section 8. Ru. After that, when the phase of the input data changes with reference to the internal reference signal, the output data phase is also output with a shift, so the phase amount measuring section 5 measures the amount of change as a phase difference, and also measures the phase lead/lag. is also detected, and based on that information, the addition/subtraction unit 7 adds or subtracts the amount of change in the phase amount from the initial setting delay amount, and based on the result, controls the delay amount of the variable delay unit 1 to adjust the phase of the output data phase manually. The phase before the change is maintained, and the phases of the two comparison signals from the phase amount measuring section 5 match again. The delay amount comparison section 9 compares the output of the addition/subtraction section 7 that controls the variable delay section 1 with the initial setting delay amount, and controls the addition/subtraction section 7 at regular intervals to gradually increase or decrease the delay amount. , the operations are repeated until the human power of the delay amount comparator 9 reaches the same value.

〔Effect of the invention〕

As explained above, the present invention is a device that uses the output data of this circuit to maintain the output data phase when the human data phase changes, and to compensate for the change in delay amount due to the holding operation. Alternatively, the amount of delay is returned to the initial value or set phase little by little over time within a range that does not affect the operation of the terminal equipment at all. This has the effect of suppressing phase shifts due to jitter in the transmission line.

[Brief explanation of the drawing]

The figure is a block configuration diagram showing the configuration of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Variable delay section, 2... Crystal oscillation section, 3... Synchronous regeneration section, 4... Frequency divider section, 5... Phase amount measurement section,
6... Synchronization signal detection section, 7... Addition/subtraction section, 8...
Initial phase setting section, 9... Delay amount comparison section.

Claims (1)

[Claims] 1. In a phase holding circuit equipped with a variable delay section that delays an incoming serial data signal by a specified amount of delay, the synchronization signal is output from the serial data signal via the variable delay section. an internal reference signal generating section that generates an internal reference signal; a phase amount measuring section that measures the phase difference between this internal reference signal and the synchronizing signal extracted by the synchronizing signal detecting section; an addition/subtraction section that specifies the delay amount of the variable delay section by adding or subtracting the amount of change in the phase difference obtained by the phase amount measuring section to the initial setting delay amount; and the delay amount determined by this addition/subtraction section and the initial setting delay amount. and a delay amount comparator section that compares the delay amount and intermittently enables the addition/subtraction section based on the comparison result. 2. The phase holding circuit according to claim 1, wherein said internal reference signal generation section is comprised of a crystal oscillation section and a frequency divider section.