JPH04102572A - Semiconductor wafer receiving carrier - Google Patents

Semiconductor wafer receiving carrier

Info

Publication number
JPH04102572A
JPH04102572A JP2212797A JP21279790A JPH04102572A JP H04102572 A JPH04102572 A JP H04102572A JP 2212797 A JP2212797 A JP 2212797A JP 21279790 A JP21279790 A JP 21279790A JP H04102572 A JPH04102572 A JP H04102572A
Authority
JP
Japan
Prior art keywords
carrier
semiconductor wafer
chemical
water
grooves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2212797A
Other languages
Japanese (ja)
Inventor
Masato Fujisawa
正人 藤沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2212797A priority Critical patent/JPH04102572A/en
Publication of JPH04102572A publication Critical patent/JPH04102572A/en
Pending legal-status Critical Current

Links

Landscapes

  • Packaging Of Annular Or Rod-Shaped Articles, Wearing Apparel, Cassettes, Or The Like (AREA)
  • Packaging Frangible Articles (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE:To uniformly treat the surface of a semiconductor wafer by forming the crest parts on the inner surface of a carrier in a vertically straight line. CONSTITUTION:The crest parts 7 of grooves 6 are formed into a straight line from the top to the bottom. The semiconductor wafers are orderly placed in the grooves 6 and each carrier undergoes automatically or manually a series of processes including the immersion into a chemical and a water washing tank to treat such wafers with the chemical and water in a predetermined manner. At this time, since the crest parts 7 on the inner surface of the carrier define opening parts in almost the same shape at the top and bottom, there are no occurrence of oscillatory wave and turbulent water flow due to megasonic vibration excited from below. This method makes difficult the occurrence of shadows in the semiconductor wafer periphery and permits the wafer interior to be treated uniformly with the chemical and water.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体ウェハ製造工程で使用する半導体ウ
ェハ収納キャリア(以下単にキャリアという)に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor wafer storage carrier (hereinafter simply referred to as a carrier) used in a semiconductor wafer manufacturing process.

〔従来の技術〕[Conventional technology]

第2図は従来のこの種のキャリアの斜視図で、図におい
て、1,2は両側の対向側壁、3.4はこれらの両側壁
の両側に架設されて連結するU端面板とH1@面板であ
り、5はアライメントビン、6.7は上記各側壁の内面
に設けられた溝とその山部である。
Fig. 2 is a perspective view of a conventional carrier of this type. In the figure, 1 and 2 are opposing side walls on both sides, and 3 and 4 are U end plates and H1 @ face plates installed on both sides of these walls and connected to each other. 5 is an alignment bin, and 6.7 is a groove provided on the inner surface of each side wall and its peak.

次に使用方法について説明する。このキャリアに例えば
半導体ウェハ(図示せず)を溝6の中にIl黙と収納し
、自動機又は手動によって、キャリア毎薬液槽及び水洗
槽に浸漬し、所定の薬液処理及び水洗などの一連の工程
に使用する。
Next, how to use it will be explained. For example, a semiconductor wafer (not shown) is silently stored in the groove 6 in this carrier, and the carrier is immersed in a chemical tank and a water washing tank by an automatic machine or manually, and subjected to a series of predetermined chemical processing and water washing. Used in the process.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところがこの場合、薬液槽処理及び水洗する工程におい
て、キャリアの下方から、例えばメガソニック洗浄の振
動波及びオーバーフロー水洗の水流をアンプフローする
時、内面の山部下部に内面に斜めに突出する突起7aが
あって下方の開口部が狭いため、ウェハ周辺部にキャリ
アによる乱流が生じて影が出来、半導体ウェハ面内に薬
液及び水洗のバラツキが生ずるという欠点があった。
However, in this case, when the vibration waves of megasonic cleaning and the water flow of overflow cleaning are amplified from below the carrier in the process of chemical bath treatment and water washing, the protrusion 7a that projects diagonally toward the inner surface at the lower part of the ridge on the inner surface. Since the lower opening is narrow, turbulence caused by carriers occurs around the wafer, creating a shadow, resulting in variations in chemical solution and water washing within the surface of the semiconductor wafer.

この発明は上記の様な欠点を解消するためになされたも
ので、半導体ウェハ面内に乱脈及び乱流による影が出来
にくいキャリアを提供することを目的とする。
This invention was made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a carrier that is less likely to cause shadows due to turbulence and turbulence in the plane of a semiconductor wafer.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係るキャリアは、キャリア内面の山部分を上
下方向にストレートに形成したものである。
In the carrier according to the present invention, the mountain portions on the inner surface of the carrier are formed straight in the vertical direction.

〔作用〕[Effect]

この発明においては、キャリア内面の山部を一様にスト
レートに構成したので、洗浄及び水洗のときキャリアに
よる乱脈及び乱流が生じない。
In this invention, since the peaks on the inner surface of the carrier are uniformly straight, turbulence and turbulence due to the carrier do not occur during cleaning and washing with water.

〔実施例〕〔Example〕

以下この発明の一実施例を第1図について説明する。第
1区において、1〜6は上記従来例のものと同様である
が、本発明においては溝6の山部7を上から下まで直線
状に形成している。
An embodiment of the present invention will be described below with reference to FIG. In the first section, 1 to 6 are the same as those of the conventional example, but in the present invention, the peaks 7 of the grooves 6 are formed in a straight line from top to bottom.

次に使用方法について説明する。例えば半導体ウェハく
図示せず)を溝6の中に整然と収納し、自動機又は手動
によって、キャリア毎、薬液槽及び水洗槽に浸漬し、所
定の薬液処理及び水洗処理等、一連の工程に使用すると
いう使用方法は、従来と同様であるが、上記の様な使用
の際、第1図で明らかな様に、キャリア内面の山部分7
が上下はぼ同一形状の開口部になっているため、下方か
ら与えられたメガソニック振動の振動波 及び水流の乱
流等が発生せず、これによって半導体ウェハ濁辺に影が
出来にくくなり、ウェハ面内に均一な薬液処理及び水洗
か可能になる。
Next, how to use it will be explained. For example, semiconductor wafers (not shown) are stored in the groove 6 in an orderly manner, and each carrier is immersed in a chemical tank and a water washing tank using an automatic machine or manually, and used for a series of processes such as predetermined chemical processing and water washing. The method of use is the same as in the past, but when used as described above, as is clear from Figure 1, the mountain portion 7 on the inner surface of the carrier
Since the upper and lower openings have almost the same shape, vibration waves of megasonic vibrations applied from below and turbulence of water flow are not generated, which makes it difficult for shadows to form on the edge of the semiconductor wafer. Uniform chemical treatment and water washing can be performed on the wafer surface.

〔発明の効果] 以上のようにこの発明によれば、側壁内面力山部をスト
レート形状に形成するという簡単な構成により、半導体
ウェハの面を均一に処理し得る効果がある。
[Effects of the Invention] As described above, according to the present invention, the surface of a semiconductor wafer can be uniformly processed by a simple structure in which the inner surface of the side wall is formed into a straight shape.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す斜視図で、第2図は
従来のキャリアの斜視図である。 図中、1,2は側壁、6は溝、7は山部である。 なお、図中同一符号は同−又は相当部分を示す。
FIG. 1 is a perspective view showing an embodiment of the present invention, and FIG. 2 is a perspective view of a conventional carrier. In the figure, 1 and 2 are side walls, 6 is a groove, and 7 is a peak. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims]  ウエハを収納する溝を有する一対の側壁部分が両端面
で結合一体化されている半導体ウエハ収納キャリアにお
いて、上記側壁の内面一対の山部分が平行かつ直線状に
構成され、キャリアの下方部分と上方部分の開口部がほ
ぼ同等な形状を有することを特徴とする半導体ウエハ収
納キャリア。
In a semiconductor wafer storage carrier in which a pair of side wall portions each having a groove for accommodating a wafer are integrally connected at both end faces, a pair of ridge portions on the inner surface of the side wall are parallel and linear, and a lower portion and an upper portion of the carrier A semiconductor wafer storage carrier characterized in that the openings of the sections have substantially the same shape.
JP2212797A 1990-08-10 1990-08-10 Semiconductor wafer receiving carrier Pending JPH04102572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2212797A JPH04102572A (en) 1990-08-10 1990-08-10 Semiconductor wafer receiving carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2212797A JPH04102572A (en) 1990-08-10 1990-08-10 Semiconductor wafer receiving carrier

Publications (1)

Publication Number Publication Date
JPH04102572A true JPH04102572A (en) 1992-04-03

Family

ID=16628542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2212797A Pending JPH04102572A (en) 1990-08-10 1990-08-10 Semiconductor wafer receiving carrier

Country Status (1)

Country Link
JP (1) JPH04102572A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6722928B1 (en) 1996-09-20 2004-04-20 Molex Incorporated Press-fit pin for use in a printed circuit board
KR101400755B1 (en) * 2012-11-16 2014-06-30 (주)Sy이노베이션 Container for wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6722928B1 (en) 1996-09-20 2004-04-20 Molex Incorporated Press-fit pin for use in a printed circuit board
KR101400755B1 (en) * 2012-11-16 2014-06-30 (주)Sy이노베이션 Container for wafer

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