JPH04100229A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To restrain the side etching of the lower resist layer comprising a multilayer resist thereby enabling a multilayer resist mask to be formed with high precision by a method wherein the second and first resist layers exposed in the opening formed in the third resist layer are successively and selectively removed by reactive ion etching step so that the second opening penetrating the first and second insulating layers may be formed corresponding to the first opening. CONSTITUTION:The opening width wo in the upper layer resist pattern 1 is smaller i.e. about 1/2 than the corresponding specified opening width w. The resist layer 21 in higher etching rate than the other layer 22 around the opening wo starts to be etched away using the layer 22 as a mask. Simultaneously with the etching step of the resist layer 21, the resist layer 22 is etched away more slowly to increase the opening width so that the bottom part of an opening 4 may finally reach the interface of a conductive layer 3. Successively, the etching step is contained until the opening width wo reaches the specified width w.

Description

[Detailed Description of the Invention] [Summary] Regarding the structure of a multilayer resist and its patterning method.

The object of the present invention is to reduce side etching that occurs in a lower resist layer constituting a multilayer resist during patterning by reactive ion etching using an oxidizing gas, thereby making it possible to form a highly accurate multilayer resist mask.

The etching rate in reactive ion etching is Rt
A first resist layer is formed on one surface of the substrate, and the etching rate in the reactive ion etching is Rt
(where RZ<R1) is applied to the first resist layer.
A pattern consisting of a third resist layer formed on the resist layer and having resistance to the reactive ion etching is formed on the second resist layer, and the pattern consisting of the third resist layer is masked. The method is configured to include steps of sequentially patterning the second resist layer and the first resist layer by the reactive ion etching.

[Industrial application field]

The present invention relates to the structure of a multilayer resist and its patterning in the manufacture of semiconductor devices.

2. Description of the Related Art As the degree of integration of semiconductor devices increases, the trend is toward multilayer wiring and the like in order to facilitate the formation of increasingly finer and more complex patterns. As a result, the wiring, etc. in the upper layer is formed on a base having a larger step. A resist layer for patterning such wiring etc.

A layer thickness distribution occurs corresponding to the level difference.

[Conventional technology]

On the other hand, it is known that there is a standing wave effect when exposing a resist using ultraviolet rays or the like. The standing wave effect occurs significantly in exposure using monochromatic light, such as reduction projection for forming fine patterns. In order to avoid the standing wave effect, it is necessary to control the resist layer thickness, but it is necessary to control the thickness of the resist layer on the entire surface with the steps mentioned above to an appropriate value that does not cause the standing wave effect. It is practically difficult to do so. Multilayer resist technology has been developed as one method to solve this problem. The structure of multilayer resist is
It consists of a flattening layer for eliminating steps or irregularities on the underlying surface, and a resist layer for patterning this flattening layer.

After patterning the resist layer by a lithographic method using ordinary light or an electron beam, an anisotropic etching method such as reactive ion etching (RIB) is performed using this resist layer as a mask.

Patterning the planarization layer. Therefore, the planarization layer is processed into a desired fine pattern without being affected by the standing wave effect as described above.

[Problems to be Solved by the Invention] The flattening layer is generally made of an organic polymer such as novolac resin, and its patterning is.

This is usually done by RIE using oxygen plasma.

This RIB uses oxygen ions (
Although anisotropic etching is mainly caused by 0°), isotropic etching is also caused by oxygen radicals generated at the same time, and the side etching caused by this cannot be ignored. This will be explained with reference to FIG.

In the figure (a), reference numeral 3 denotes a conductive layer made of aluminum or the like, which is patterned using a multilayer resist, and the flattening layer 2 is formed on this conductive layer. And on the planarization layer 2.

An upper resist pattern 1 made of, for example, an organic silicon compound resist 1 that is resistant to oxygen plasma.
is formed.

When the flattening layer 2 is etched by RIE using oxygen plasma using the upper resist pattern 1 as a mask, the isotropic etching by oxygen radicals as described above results in a pattern as shown in FIG.

Side etching of an amount indicated by X occurs on the sidewalls of the patterned planarization layer 2. At this time.

Let W be the opening width of the planarization layer 2 on the surface of the conductive layer 3.

Due to the side etching described above, the effective layer thickness of the planarizing layer 2 that masks the conductive layer 3 around the opening is reduced, but when etching the conductive layer 3 using the planarizing layer 2 as a mask, generally, Since the planarization layer 2 is also subjected to non-negligible etching, the opening width W is shifted by y.

By the way, the flattening layer 2 on a substrate such as a semiconductor wafer
Actually, there is a one-layer thickness distribution. Therefore, etching conditions are set such that an opening of a predetermined size is formed in the planarization layer 2 having the largest thickness. As a result, the opening width W of the planarization layer 2 on the substrate, the side etching amount X,
Furthermore, variations occur in the shift amount y.

Fluctuations in the opening width W and shift amount y caused by a combination of the above-mentioned causes cause errors in the width or mutual spacing of the wiring formed by patterning the conductive layer 3 with precision.

The above problem could be solved if an ideal opening with vertical sidewalls without side etching could be formed in the planarization layer 2, but in reality.

It is difficult to completely avoid side etching caused by oxygen radicals and obliquely incident ions as described above.

By the way, as a method for reducing the side etching in the openings as described above, 50% of the etching gas containing oxygen is added to the etching gas.
A method has been proposed in which a protective film of an organic substance is deposited on the side wall of the opening by adding iC1a or the like. However, according to this method, the protective film attached to the inner wall of the etching apparatus becomes a source of gas emission or dust generation, so maintenance of the apparatus is labor-intensive. There is a drawback that process control becomes unstable.

In view of the above conventional problems, the present invention reduces side etching that occurs in the lower resist layer (flattening layer) constituting the multilayer resist when patterning a multilayer resist by reactive ion etching using an oxidizing gas. The purpose of this invention is to enable the formation of highly accurate multilayer resist masks, thereby improving wiring pattern accuracy.

[Means to solve the problem]

The above purpose is to apply a liquid resist on one surface of a substrate to provide a first resist layer exhibiting a first etching rate in reactive ion etching, and applying a liquid resist that provides a second resist layer exhibiting a lower second etching rate to the surface of the substrate on which the first resist layer is formed; and the substrate on which the second resist layer is formed. forming a third resist layer on its surface that is resistant to the reactive ion etching and has an opening corresponding to a predetermined region defined on the substrate surface; The second resist layer and the first resist layer exposed in the provided opening are sequentially and selectively removed by the reactive ion etching to form the first and second insulating layers corresponding to the opening. forming a second opening penetrating the layer; or a first resist layer exhibiting a first etching rate in two-reactive ion etching; forming on one surface of the substrate; forming on the first resist layer two resist layers exhibiting a second etching rate lower than the first etching rate in the reactive ion etching; forming on the second resist layer a pattern made of a third resist layer that is resistant to reactive ion etching; and using the pattern made of the third resist layer as a mask, forming the second resist layer. and sequentially pattern-accurately patterning the first resist layer by the reactive ion etching.

[For production]

Approximately the lower half of the planarization layer in the multilayer resist is made up of a resist layer with a high etching rate in RIE using oxygen plasma, and the upper half is made up of a resist layer with a low etching rate.

These are patterned by the RIE described above. The side etching amount X is approximately proportional to the time during which the side wall of the planarization layer is exposed to oxygen radicals or obliquely incident ions. Therefore, by using a resist layer with a high etching rate as the lower half of the flattening layer as described above, the overall etching time is shortened, and when an opening of a predetermined width is formed, the amount of side etching is reduced compared to the conventional method. .

When the lower layer is exposed in the above-mentioned opening, the lower layer starts to be etched. However, since the vertical etching speed of the lower layer is higher than the rate of widening of the opening width at the bottom of the upper layer, the side etching in the lower layer is small. Therefore, the side etching at the bottom of the lower layer is The amount of side etching when the opening width reaches a predetermined value is about 172 or less than that of the conventional method.

In this way, openings are formed in the planarization layer with less side etching, ie, with more vertical sidewalls, than in the prior art. Therefore, the opening width varies due to the layer thickness distribution of this flattening layer.

The shift of the opening when patterning the conductive layer using this planarization layer as a mask is reduced, and as a result, wiring with high dimensional accuracy can be formed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1(a), a conductive layer 3 made of, for example, aluminum is deposited on a semiconductor device substrate 10 covered with an insulating layer (not shown), and then a first resist solution is applied onto the conductive layer 3. Next, a second resist solution is applied on the first resist layer 21 and baked at a predetermined temperature to form a second resist layer 21. A resist layer 22 is formed. Resist layers 21 and 22 constitute a conventional planarization layer.

Then, a photoresist is applied on the second resist layer 22.

This is patterned by lithography using light or electron beams to form an upper resist pattern I.

Note that the resist layer 21 is different from the resist layer 22.

A high etching rate by RIB using oxygen plasma is required. Further, the resist pattern 1 is required to have sufficient resistance to RIB using the oxygen plasma. Examples of resist materials that meet these requirements are as follows.

Resist layer 21: Z-CMRloo Resist layer 22 manufactured by Zeon Co., Ltd. NPR-820 Resist pattern 1 manufactured by Nagase Sangyo Co., Ltd.: Z-5EN620 Resist layer 21 manufactured by Zeon Co., Ltd. is PMMA (polymethyl methacrylate) resin system, resist layer 22 is a novolac resin type.

The etching rate ratio between these is approximately 2=1.

The resist pattern 1 is made of an organic silicon compound, and the etching rate by RIB using oxygen plasma is about 1150 to 1/100 of that of the resist layer 21 or 22.

Using upper resist pattern 1 as a mask, resist layer 21 and resist layer 21 are sequentially etched by RIB using oxygen plasma. In this example of etching conditions, a parallel plate type RIE apparatus is used.

Oxygen gas is introduced into this, and the total pressure is controlled to 0.03 Torr to generate plasma.

By the RIE, as shown in FIG. 1(b), the resist layer 22 is first etched to form the opening 4, and then the resist layer 21 exposed in the opening 4 is etched. The progress of the etching at this time is schematically shown in FIG. 2. In FIG. 2(a), marks 1 to 2 indicate the order in which the cross section of the opening 4 changes over time during the etching.

Immediately after the resist layer 21 is exposed in the opening 4,
The opening width at the interface with the resist layer 21 is as follows.

As shown by the curve (2), the resist layer 22 around this opening, which is as small as about 172 times the corresponding opening width w0 in the upper resist pattern 1, is used as a mask.

The resist layer 21, which has a higher etching rate, begins to be etched. At the same time as the etching of the resist layer 21, the etching of the resist layer 22 progresses more slowly, and the opening width increases as shown by the curve . reaches the interface with 3. Then, as shown in FIG. 1), etching is performed until the opening width at the bottom reaches a predetermined value W.

As mentioned above, the etching rate of the resist layer 21 is sufficiently higher than that of the resist layer 22.

The maximum side etching amount X of the side wall of the opening 4 when the opening width at the bottom is W is smaller than that in the conventional method shown in FIG.

Note that in etching the planarization layers 22 and 21.

A non-negligible etching occurs in the upper resist pattern 1, and the edge portion of the upper resist pattern 1 recedes.

This becomes a factor that increases the opening width and side etching. therefore.

In fact, the size of the opening provided in the upper resist pattern 1 is made small in advance in anticipation of additional addition. The maximum side etching amount X of the openings in the flattening layers 21 and 22 is shown based on the edge of the upper resist pattern 1 that has retreated as described above.

FIG. 4 is a diagram schematically showing the progress of etching of the flattening layer 2 in the conventional patterning of the multilayer resist layer shown in FIG. is the order of change of the aperture cross section over time. (3) shows the state immediately after the bottom of the opening reaches the conductive layer 3, and the opening width at the interface with the conductive layer 3 has not yet reached the predetermined value W, but the upper resist pattern 1 has already reached the upper resist pattern 1 at the top of the opening. There is side etching at the bottom. Etching of the planarization layer 2 is continued, and the etching is stopped when the opening width at the bottom reaches a predetermined value W, as shown in FIG. Note that, similarly to the above, in etching the planarization layer 2, the edge portion of the upper resist pattern 1 having the original opening width W0 recedes. The side etching amount X is shown based on the above-mentioned retreated edge in the upper resist pattern 1.

As shown in the figure, when the planarization layer 2 is composed of a single resist layer, etching is performed at a constant rate in the thickness direction of nine layers.
In between, large side etchings occur. the result,
When an opening with a predetermined width W is formed, the effective layer thickness of the planarization layer 2 remaining on the conductive layer 3 is small, and in patterning the conductive layer 3, the opening width W is shifted by y.

On the other hand, according to the present invention, the planarization layers 21 and 2
Since the side etching in 2 is reduced and an opening having a more vertical sidewall is formed, the variation in the opening width W is reduced, and the effective layer of the planarization layer 21 that serves as a mask in patterning the conductive layer 3 is reduced. Large thickness. Therefore, the amount of shift y of the opening width W in patterning the conductive layer 3 is small (and a more accurate wiring pattern can be formed).

In the above embodiment, the planarization layer was made up of two resist layers having different etching rates, but the planarization layer can be made up of two or more resist layers whose etching rate is higher as the lower layer goes.

It is clear that even more precise patterning becomes possible.

〔Effect of the invention〕

According to the present invention, side etching in the flattening layer of a multilayer resist can be reduced, and a fine pattern such as a wiring formed on a surface with a large one-step difference can be formed with high precision.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention. FIG. 2 is a schematic diagram showing the progress of etching in the flattening layer of the multilayer resist structure of the present invention. FIG. 3 is a diagram explaining the problems of the conventional technology. FIG. 4 is a schematic diagram showing the progress of etching in the flattening layer of a conventional multilayer resist structure. In fig. 1 is an upper resist pattern, and 2 is a flattening layer. 3 is a conductive layer, 4 is an opening. 10 is a semiconductor device substrate, and 21 and 22 are resist layers. Explanatory diagram of the principle of the present invention Conventional theory B point theory

Claims (3)

[Claims] (1) A step of applying a liquid resist to one surface of the substrate to provide a first resist layer exhibiting a first etching rate in reactive ion etching, and a step of applying a liquid resist on one surface of the substrate, and in the reactive ion etching, the etching rate is lower than the first etching rate. applying a liquid resist that provides a second resist layer exhibiting a second etching rate to the surface of the substrate on which the first resist layer is formed; and the surface of the substrate on which the second resist layer is formed. a third substrate which is resistant to the reactive ion etching and is provided with an opening corresponding to a predetermined region defined on the surface of the substrate;
forming a resist layer; and sequentially selectively removing the second resist layer and the first resist layer exposed in the opening provided in the third resist layer by the reactive ion etching. and forming a second opening that penetrates the first and second insulating layers in correspondence with the opening. (2) forming a first resist layer on one surface of the substrate that exhibits a first etching rate in reactive ion etching, and exhibits a second rate that is lower than the first rate in the reactive ion etching; forming a second resist layer on the first resist layer; and forming a pattern on the second resist layer comprising a third resist layer that is resistant to the reactive ion etching. and sequentially patterning the second resist layer and the first resist layer by the reactive ion etching using the pattern made of the third resist layer as a mask. Method. (3) At least one intermediate resist layer is provided between the first and second resist layers, and the etching rate of the first and second resist layers and the intermediate resist layer in the reactive ion etching is 3. The method of manufacturing a semiconductor device according to claim 1, wherein the lower the layer, the higher the height.