JPH0399446A - Wiring of semiconductor element - Google Patents

Wiring of semiconductor element

Info

Publication number
JPH0399446A
JPH0399446A JP1236254A JP23625489A JPH0399446A JP H0399446 A JPH0399446 A JP H0399446A JP 1236254 A JP1236254 A JP 1236254A JP 23625489 A JP23625489 A JP 23625489A JP H0399446 A JPH0399446 A JP H0399446A
Authority
JP
Japan
Prior art keywords
wire
film
wire bonding
electrode
peeled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1236254A
Other languages
Japanese (ja)
Other versions
JP2680696B2 (en
Inventor
Shuji Katayama
片山　修治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Tottori Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Tottori Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP1236254A priority Critical patent/JP2680696B2/en
Publication of JPH0399446A publication Critical patent/JPH0399446A/en
Application granted granted Critical
Publication of JP2680696B2 publication Critical patent/JP2680696B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H01L2224/02126—Collar structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive prevention of the deterioration of a semiconductor element by a method wherein a wire bonding is performed on an electrode from over an insulating film, a part of the film is peeled by the shock of the wire bonding and a wiring is provided on the electrode at the peeled part of the film. CONSTITUTION:A wire bonding is performed on a semiconductor element 1 from over an electrode 2 by a ball bonding and wire bonding method. A gold wire of a diameter of 25mum, for example, is used, a ball of a length of about 120mum is formed on the point of the wire bonding wire 4 by a hydrogen torch and a wire bonding is performed. Thereby, in an insulating film subjected to shock by the wire 4 in a wire bonding of a first time, the shocked part only is peeled. The peeled film 3 is often adhered on the point of the ball, but if the hydrogen torch is kept applying to the peeled film at a standby position, the film is easily removed from the point of the wire 4. Moreover, in that state, if a wire bondig is again performed, a first bonding can be attained on the exposed electrode 2 by the peeling of the film 3.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 本発明は絶縁被膜を有する半導体素子にワイヤボンド法
を適用した半導体の配線方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor wiring method in which a wire bonding method is applied to a semiconductor element having an insulating film.

（ロ）従来の技術 従来より、例えばアルミニウムを含む発光ダイオードな
どは特開昭５７−１１１０７３号公報の如く、素子表面
が露出したままであると素子の発光特性が劣化してくる
ので、素子表面に絶縁被膜を設けていた。この場合電極
部分を含む半導体素子表面に絶縁被膜を設け、その後電
極部分の絶縁被膜をホトリソグラフィ法などを用いて除
去し、露出した電極部分にワイヤボンド法で配線を施し
ていた。(B) Conventional technology Conventionally, for example, in the case of light-emitting diodes containing aluminum, as disclosed in Japanese Patent Application Laid-Open No. 57-111073, if the element surface remains exposed, the light emitting characteristics of the element will deteriorate. An insulating coating was provided on the In this case, an insulating film is provided on the surface of the semiconductor element including the electrode portion, and then the insulating film on the electrode portion is removed using a photolithography method or the like, and wiring is applied to the exposed electrode portion using a wire bonding method.

（ハ）発明が解決しようとする課題 ところが、上述の発光ダイオードなどの半導体素子はエ
ピタキシャル成長過程などでウェハが反ったり表面に凹
凸が生じたりするため、電極形成のパターニングと、絶
縁被膜除去のパターニングで位置ずれが生じ、素子表面
が露出することがあり、このような半導体素子は劣化を
生じやすいので不都合であった。(c) Problems to be Solved by the Invention However, in semiconductor devices such as the above-mentioned light-emitting diodes, the wafer warps and irregularities occur on the surface during the epitaxial growth process, so patterning for electrode formation and patterning for removing the insulating film is difficult. Misalignment may occur and the surface of the element may be exposed, which is disadvantageous since such semiconductor elements are susceptible to deterioration.

（ニ）課題を解決するための手段 本発明は上述の欠点を改めるためになされたもので、絶
縁被膜の上から電極に対してワイヤボンドを行い、ワイ
ヤボンド衝撃により絶縁被膜を剥離させ、その剥離部分
において電極に配線を施すものである。(d) Means for Solving the Problems The present invention has been made to correct the above-mentioned drawbacks, and involves wire bonding to the electrode from above the insulating coating, peeling off the insulating coating by the impact of the wire bond, and Wiring is applied to the electrode at the peeled part.

（ホ）作用 これにより絶縁被膜をパターニング除去する必要がなく
、また剥離はワイヤボンド線の先端の大きさに略等しい
から、半導体素子の表面が露出することはない。(E) Effect This eliminates the need to pattern and remove the insulating film, and since the size of the peeling is approximately equal to the tip of the wire bond line, the surface of the semiconductor element is not exposed.

（へ）実施例 以下半導体素子としてＧａＡｌＡｓ発光ダイオードを例
にして詳細に説明する。この半導体素子は一辺２００〜
４００μｍの略サイコロ状またはその表面側をメサエッ
チされた形状若しくはベベル型をなしており、第１図に
示すように、例えば円形で直径が１５０μｍ、厚み２μ
ｍで、Ａｕ。(F) EXAMPLE A GaAlAs light emitting diode will be described in detail below as an example of a semiconductor device. This semiconductor element has 200~
It has a roughly dice shape of 400 μm, a mesa-etched shape on the surface side, or a bevel shape, and as shown in FIG.
m, Au.

Ｇｅ、Ｎｉを主材とする電極（２）が設けられ、その電
極（２）の上を含む素子（１）の表面には、厚さ０．５
〜１０μｍの窒化硅素（Ｓｉ、Ｎ、またはアモルファス
Ｓｉ、Ｎ）から成る絶縁被膜（３）が設けである。この
絶縁被膜（３）は、ウェハの段階、若しくは素子にベレ
ッタライズされた後で形成され、電極（２）に対応する
部分の除去は行われていない。An electrode (2) mainly made of Ge and Ni is provided, and the surface of the element (1) including the top of the electrode (2) has a thickness of 0.5
An insulating coating (3) of ~10 μm of silicon nitride (Si,N or amorphous Si,N) is provided. This insulating coating (3) is formed at the wafer stage or after the device is beletized, and the portions corresponding to the electrodes (2) are not removed.

このような半導体素子（１）に対して、電極（２）の上
方からボールボンドワイヤボンド法によりワイヤボンド
をする。例えば直径２５μｍの金線を用い、水素トーチ
によりおよそ１２０μｍのボールをワイヤボンド線（４
）の先端に形成しワイヤボンドをする。これにより第１
回のワイヤボンドでワイヤボンド線により衝撃を受けた
絶縁被膜（３）は、第２図に示す如くその衝撃部分のみ
剥離される。剥離された絶縁被膜（３）はボールの先端
に付着する場合が多いが、待機位置において水素トーチ
を当てておけばワイヤボンド線の先端から容易に除去さ
れる。そしてその状態で再びワイヤボンドすると、第３
図の如く、絶縁被膜（３）が剥離したことによって露出
した電極（２）に対して第１ボンドが達成できるので、
そのまま第２ボンドを行えば配線を行うことができる。Wire bonding is performed to such a semiconductor element (1) from above the electrode (2) by a ball bond wire bonding method. For example, using a gold wire with a diameter of 25 μm, use a hydrogen torch to attach a ball of approximately 120 μm to a wire bond wire (4
) and wire bond. This allows the first
The insulating coating (3), which has been impacted by the wire bonding wire during the wire bonding process, is peeled off only at the impacted portion, as shown in FIG. The peeled insulating coating (3) often adheres to the tip of the ball, but it can be easily removed from the tip of the wire bond line by applying a hydrogen torch to it in the standby position. Then, when wire bonding is performed again in this state, the third
As shown in the figure, the first bond can be achieved to the electrode (2) exposed due to the peeling of the insulating coating (3).
Wiring can be performed by performing the second bond as is.

上述の説明で、−回だけで絶縁被膜（３）が剥離しない
こともある。しかし絶縁被膜（３）が剥離したか否かは
絶縁被膜（３）の光反射係数の大きさによりパターン認
識できるから何回でも繰り返しワイヤボンドをすればよ
い。In the above explanation, the insulating coating (3) may not be peeled off only by - times. However, whether or not the insulating coating (3) has peeled off can be determined by pattern recognition based on the magnitude of the light reflection coefficient of the insulating coating (3), so wire bonding can be repeated any number of times.

また絶縁被膜（３）の剥離がワイヤボンド線（４）のボ
ールの大きさになるかどうか、及びそのワイヤボンド位
置が電極（２）の中心に限定できるのかということに関
しては、半導体素子表面が露出するかしないかに直接影
響を及ぼすことなので慎重に検討した。その結果、ボン
ディンダ衝撃が局所的であれば有るほど、絶縁被膜（３
）の剥離の大きさは小さく、従ってこの点ではボールボ
ンド法以外の方法がより効果を期待できることとなり、
また電極の位置そのものは絶縁被膜（３）があるために
パターン認識しにくいものの、半導体素子の外形に対し
て電極（２）の位置を特定する作業は比較的容易である
ことが分かった。Also, regarding whether the peeling of the insulating coating (3) becomes the size of the ball of the wire bond line (4) and whether the wire bond position can be limited to the center of the electrode (2), it is important to note that the surface of the semiconductor element We carefully considered this issue as it has a direct impact on whether or not we will be exposed. As a result, the more localized the bondinder impact, the more the insulation coating (3
) is small, so methods other than the ball bond method can be expected to be more effective in this respect.
Furthermore, although the position of the electrode itself is difficult to pattern recognize due to the presence of the insulating coating (3), it has been found that identifying the position of the electrode (2) with respect to the external shape of the semiconductor element is relatively easy.

さらに剥離した絶縁被膜が配線のときに電極（２）とワ
イヤボンド線（４）の間に介在し、導通不良を生じない
かについて検討した。上述の如くワイヤボンド（空打ち
）の度に水素トーチを当てることによって絶縁被膜は蒸
発したりワイヤボンド線に溶は込んだり、あるいはボー
ルが大きくなり過ぎて落下し次の新しいボールとなった
りして実際上導通不良を起こすことはなかったが、他の
方法として、絶縁被膜（３）の上からワイヤボンド（空
打ち）する度に、予め定められたワイヤボンド線（４）
と密着のよい場所にワイヤボンドして先端を切り離すと
いう方法も有効であった。Furthermore, we examined whether the peeled insulating film would be interposed between the electrode (2) and the wire bond line (4) during wiring, causing poor conduction. As mentioned above, by applying a hydrogen torch each time wire bonding (dry firing) is performed, the insulating film may evaporate, melt into the wire bond line, or the ball may become too large and fall, becoming the next new ball. However, as another method, each time wire bonding (blank bonding) is performed from above the insulating coating (3), a predetermined wire bond line (4) is
Another effective method was to wire-bond the wire to a place where it was in good contact and then cut off the tip.

（ト）発明の効果 以上のような方法で配線を行った発光ダイオード半導体
素子について高温高温連続通電動作を行ったところ、１
０００時間で光出力が８０．０％未満となる素子は全く
見られなかった。(g) Effects of the invention When a light-emitting diode semiconductor element wired in the manner described above was subjected to continuous high-temperature energization, 1
No element was observed in which the optical output was less than 80.0% after 000 hours.

【図面の簡単な説明】[Brief explanation of drawings]

第１図乃至第３図は本発明実施例を説明する配線方法の
工程説明図である。1 to 3 are process explanatory diagrams of a wiring method illustrating an embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] （１）電極表面を含む素子の表面に絶縁被膜を有する半
導体素子の電極上方にワイヤボンド線を複数回ワイヤボ
ンドして半導体素子に配線を施す半導体素子の配線方法
。(1) A wiring method for a semiconductor device, in which wire bonding lines are wire-bonded multiple times above the electrodes of a semiconductor device having an insulating film on the surface of the device including the electrode surface to wire the semiconductor device.
JP1236254A 1989-09-12 1989-09-12 Wiring method of semiconductor element Expired - Lifetime JP2680696B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1236254A JP2680696B2 (en) 1989-09-12 1989-09-12 Wiring method of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1236254A JP2680696B2 (en) 1989-09-12 1989-09-12 Wiring method of semiconductor element

Publications (2)

Publication Number Publication Date
JPH0399446A true JPH0399446A (en) 1991-04-24
JP2680696B2 JP2680696B2 (en) 1997-11-19

Family

ID=16998061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1236254A Expired - Lifetime JP2680696B2 (en) 1989-09-12 1989-09-12 Wiring method of semiconductor element

Country Status (1)

Country Link
JP (1) JP2680696B2 (en)

Also Published As

Publication number Publication date
JP2680696B2 (en) 1997-11-19

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