JPH0537027A - Led array - Google Patents

Led array

Info

Publication number
JPH0537027A
JPH0537027A JP21584091A JP21584091A JPH0537027A JP H0537027 A JPH0537027 A JP H0537027A JP 21584091 A JP21584091 A JP 21584091A JP 21584091 A JP21584091 A JP 21584091A JP H0537027 A JPH0537027 A JP H0537027A
Authority
JP
Japan
Prior art keywords
layer
gaas
gaas layer
electrode
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21584091A
Other languages
Japanese (ja)
Inventor
Shunji Murano
俊次 村野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP21584091A priority Critical patent/JPH0537027A/en
Publication of JPH0537027A publication Critical patent/JPH0537027A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Led Device Packages (AREA)
  • Led Devices (AREA)
  • Dot-Matrix Printers And Others (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Facsimile Heads (AREA)
  • Facsimile Scanning Arrangements (AREA)

Abstract

PURPOSE:To prevent a GaAs layer from being destructed or contaminated by forming an electrode layer on the surface of the GaAs layer and by extracting the electrode layer onto a different kind of substrate for external connection. CONSTITUTION:An SiO film is formed on the surface of a silicon substrate 2 and then it is partially etched to make a window. Nextly, a GaAs layer 6 is formed on the window, the SiO film is etched and the whole surface is protected with an SiN protective layer 14. Then, an electrode 16 is formed by sputtering, vacuum evaporation or other method. Under the condition that the GaAs layer 6 is heated together with the silicon substrate 2, ultrasonic vibration is applied between a gold wire 20 and an external connection layer 18 of the electrode 16 and the gold wire 20 is wire-bonded to the external connection layer 18 with the pressure applied to the gold wire 20 and the ultrasonic vibration. By this method, the GaAs layer 6 is prevented from being destructed or contaminated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の利用分野】この発明は、LEDプリンタヘッド
やディスプレイ、イメージセンサ等に用いるLEDアレ
イに関する。この発明は更に詳細には、シリコン等の異
種基板上にGaAs層をエピタキシャル成長させたLE
Dアレイの電極接続に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LED array used for an LED printer head, a display, an image sensor or the like. More specifically, the present invention is an LE in which a GaAs layer is epitaxially grown on a heterogeneous substrate such as silicon.
It relates to the electrode connection of the D array.

【0002】[0002]

【従来技術】シリコンやゲルマニウム基板上にGaAs
層をエピタキシャル成長させた、LEDアレイが提案さ
れている(例えば特開昭53−74,895号)。この
LEDアレイでは、基板の全面にGaAs層をエピタキ
シャル成長させ、電極もGaAs層上に形成して、Ga
As層上でワイヤボンディング等で外部と接続する。
PRIOR ART GaAs on a silicon or germanium substrate
An LED array in which layers are epitaxially grown has been proposed (for example, JP-A-53-74,895). In this LED array, a GaAs layer is epitaxially grown on the entire surface of the substrate, an electrode is also formed on the GaAs layer, and Ga is formed.
The As layer is connected to the outside by wire bonding or the like.

【0003】しかしながらGaAs層は脆いため、この
部分でワイヤボンディングを行うと不良が多発し、例え
ばGaAs層の破壊が頻発する。シリコン上にGaAs
層をエピタキシャル成長させるのは、高密度なLEDア
レイを得ることと直結している。少なくともLEDアレ
イの高密度化は時代の趨勢である。LEDアレイを高密
度にすると、ボンディングも高密度になる。ここで薄く
脆いGaAs層上でワイヤボンディングを行うと、高密
度化に伴い電極も薄く小さくなるため、ボンディング時
の加圧力を増加させねばならない。そして加圧力を増す
と脆弱なGaAs層にはクラック等が発生し、GaAs
層が破壊される。同様にLEDアレイの高密度化は、ボ
ンディング密度の増加をもたらす。そしてこのことはG
aAs層へのダメージを増加させ、破壊の頻度を増加さ
せる。
However, since the GaAs layer is fragile, if the wire bonding is performed in this portion, defects frequently occur, and, for example, the GaAs layer frequently breaks. GaAs on silicon
Epitaxially growing layers is directly linked to obtaining high density LED arrays. At least, increasing the density of LED arrays is the trend of the times. The higher the density of the LED array, the higher the density of bonding. Here, if wire bonding is performed on a thin and brittle GaAs layer, the electrode becomes thin and thin as the density increases, so the pressure applied during bonding must be increased. When the pressure is increased, cracks are generated in the fragile GaAs layer,
The layer is destroyed. Similarly, densification of LED arrays results in increased bonding density. And this is G
It increases damage to the aAs layer and increases the frequency of destruction.

【0004】ボンディングにはワイヤボンディング以外
に、バンプ接続等の種々のものがあるが、いずれもGa
As層に機械的な無理を加える、あるいは多数の工程を
GaAs層上で行い、GaAs層の劣化や汚染の原因と
なることに変わりはない。例えば半田バンプを形成する
場合、バリア皮膜の形成と下地導電性金属膜の形成、バ
ンプ形成部以外の部分のレジストによるマスク、半田メ
ッキによるバンプの形成、レジストの除去、バンプ以外
の部分の下地導電性金属膜のエッチング、バリア皮膜の
エッチング等の長い工程が必要である。これらの工程に
GaAs層をさらすことは、GaAs層の汚染の原因と
なる。
In addition to wire bonding, there are various types of bonding such as bump connection, all of which are Ga.
There is no change in that mechanical stress is added to the As layer or many steps are performed on the GaAs layer, which causes deterioration and contamination of the GaAs layer. For example, when forming solder bumps, barrier film formation and underlying conductive metal film formation, mask of resist other than bump formation part, bump formation by solder plating, resist removal, base conductivity of parts other than bumps It requires a long process such as etching of the conductive metal film and etching of the barrier film. Exposing the GaAs layer to these steps causes contamination of the GaAs layer.

【0005】[0005]

【発明の課題】この発明の課題は、高価でかつ脆弱なG
aAs層上での外部との接続を避け、GaAs層の破壊
や汚染を防止することに有る。
SUMMARY OF THE INVENTION The object of the present invention is to provide an expensive and fragile G
This is to prevent the GaAs layer from being destroyed or contaminated by avoiding external connection on the aAs layer.

【0006】[0006]

【発明の構成】この発明のLEDアレイは、GaAsと
は異なる材質から成る異種基板上に、発光層のGaAs
層をエピタキシャル成長させたLEDアレイにおいて、
上記GaAs層の表面に電極層を形成し、かつ該電極層
を前記異種基板上に引出し、ここで外部接続することを
特徴とする。
The LED array of the present invention comprises a heterogeneous substrate made of a material different from that of GaAs, and the GaAs of the light emitting layer.
In an LED array in which layers are epitaxially grown,
It is characterized in that an electrode layer is formed on the surface of the GaAs layer, and the electrode layer is drawn onto the different type substrate and externally connected here.

【0007】[0007]

【発明の作用】この発明では、シリコン等の異種基板上
に電極層を引出し、ここで外部接続する。この結果、外
部接続時のGaAs層への衝撃や負荷、汚染は解消し、
高価なGaAs層を傷つけずまた汚染せずに外部接続で
きる。またシリコン等の異種基板はGaAsに比べ強固
であり、外部接続時の破壊は生じない。
According to the present invention, the electrode layer is drawn out on a heterogeneous substrate such as silicon and is externally connected here. As a result, the impact, load, and pollution on the GaAs layer during external connection are eliminated,
External connection is possible without damaging or contaminating the expensive GaAs layer. In addition, a heterogeneous substrate such as silicon is stronger than GaAs and does not break when externally connected.

【0008】[0008]

【実施例】図1に最初の実施例を示す。図において、2
はシリコン基板で、この他にサファイア板上にシリコン
膜を成長させたシリコンオンサファイア基板や、単なる
サファイア基板、あるいはゲルマニウム基板等も使用し
得る。基板2はGaAs層をエピタキシャル成長させ得
るものであれば良い。4はGaAs層とシリコン基板2
との格子定数の差による歪を緩和させるための、中間の
格子定数を持った歪超格子層で、例えば1原子〜10原
子層程度の厚さとする。歪超格子層4は、例えばInG
aAs原子層とGaAs原子層を例えば5層に交互に積
層したものとする。6はエピタキシャル成長で超格子層
4上に積層したGaAs層である。GaAs層6は、例
えばn型GaAs層8,n型GaAlAs層10,Ga
AlAsにp型不純物のZnを導入したp型GaAlA
s−Zn層12の3層からなり、GaAs層8,n型G
aAlAs層10,p型GaAlAs−Zn層12の順
にエピタキシャル成長を続ける、もしくはGaAs層
8,n型GaAlAs層10の形成後にZnを不純物注
入して、p型GaAlAs−Zn層12を形成する。n
型GaAlAs層10とp型GaAlAs−Zn層12
の界面が発光層となる。n型GaAs層8の膜厚は例え
ば2〜3μm,n型GaAlAs層10は1〜2μm,
p型GaAlAs−Zn層12は1〜2μm程度とし、
合計膜厚を例えば7μm程度とする。なおここで示した
GaAs層6の構成は例であり、発光ダイオードとして
用い得る任意のGaAs層の構成に変えることができ、
不純物の種類は任意である。14はSiN、SiO等の
保護層、16は金やAl等の電極層で、p型GaAlA
s−Zn層12上に形成して、シリコン基板2上まで引
出す。シリコン基板2上の電極層を、特に外部接続層1
8と呼ぶ。20は例えばワイヤボンディングした金線
で、例えば線径20〜30μm程度のものを用いる。2
2はシリコン基板2の裏面に設けた共通電極層で、Ga
As層6に設けた多数のLEDの共通電極として用い
る。また24は、シリコン基板2を搭載した外部基板で
ある。これらの結果、n型GaAlAs層10とp型G
aAlAs−Zn層12の界面の発光層は、電極16と
共通電極22に接続される。なお1アレイ当りのLED
の数は、例えば40〜120個等とする。
EXAMPLE FIG. 1 shows a first example. In the figure, 2
Is a silicon substrate, and in addition to this, a silicon-on-sapphire substrate in which a silicon film is grown on a sapphire plate, a simple sapphire substrate, or a germanium substrate may be used. The substrate 2 may be any one that can epitaxially grow a GaAs layer. 4 is a GaAs layer and a silicon substrate 2
A strained superlattice layer having an intermediate lattice constant for relaxing the strain due to the difference in the lattice constant between the and, and has a thickness of, for example, 1 atom to 10 atom layers. The strained superlattice layer 4 is, for example, InG.
For example, it is assumed that the aAs atomic layer and the GaAs atomic layer are alternately laminated in five layers. Reference numeral 6 is a GaAs layer which is laminated on the superlattice layer 4 by epitaxial growth. The GaAs layer 6 includes, for example, an n-type GaAs layer 8, an n-type GaAlAs layer 10, and Ga.
P-type GaAlA obtained by introducing p-type impurity Zn into AlAs
The s-Zn layer 12 comprises three layers, a GaAs layer 8 and an n-type G layer.
The p-type GaAlAs-Zn layer 12 is formed by continuing epitaxial growth of the aAlAs layer 10 and the p-type GaAlAs-Zn layer 12, or by implanting Zn after forming the GaAs layer 8 and the n-type GaAlAs layer 10. n
-Type GaAlAs layer 10 and p-type GaAlAs-Zn layer 12
The interface becomes the light emitting layer. The thickness of the n-type GaAs layer 8 is, for example, 2 to 3 μm, and the thickness of the n-type GaAlAs layer 10 is 1 to 2 μm.
The p-type GaAlAs-Zn layer 12 has a thickness of about 1 to 2 μm,
The total film thickness is, eg, about 7 μm. Note that the structure of the GaAs layer 6 shown here is an example, and can be changed to any structure of the GaAs layer that can be used as a light emitting diode.
The type of impurities is arbitrary. 14 is a protective layer of SiN, SiO, etc., 16 is an electrode layer of gold, Al, etc., and is p-type GaAlA
It is formed on the s-Zn layer 12 and is drawn out onto the silicon substrate 2. The electrode layer on the silicon substrate 2, especially the external connection layer 1
Call it 8. Reference numeral 20 is, for example, a wire-bonded gold wire having a wire diameter of about 20 to 30 μm. Two
2 is a common electrode layer provided on the back surface of the silicon substrate 2,
It is used as a common electrode for many LEDs provided on the As layer 6. Further, 24 is an external substrate on which the silicon substrate 2 is mounted. As a result, the n-type GaAlAs layer 10 and the p-type G
The light emitting layer at the interface of the aAlAs-Zn layer 12 is connected to the electrode 16 and the common electrode 22. LED per array
Is 40 to 120, for example.

【0009】図1のLEDアレイは、次のようにして製
造する。図6に示すように、シリコン基板2の表面を熱
酸化しSiO膜30を形成する。これを部分的にエッチ
ングし、窓を設ける。次いでこの窓の部分に、エピタキ
シャル成長でGaAs層6を形成し、SiO膜30をエ
ッチングし、SiN保護層14で表面を保護する。Si
O膜30は、SiN膜やSiO2膜等に変えても良い。
これらの後にスパッタリングや真空蒸着等で電極16を
設ける。ここで図のように、GaAs層6の端部がシリ
コン基板2に垂直にならず斜めになるようにすると、表
面の高さが連続的に変化するため、電極16の形成が容
易になる。GaAs層6とシリコン基板2との表面高さ
の差により、電極16の形成が困難な場合、例えばGa
As層6以外の部分にSiOやSiN等を堆積させ表面
高さを揃える、あるいはGaAs層6以外の部分にレジ
ストを塗布し、ラッピングで高さをGaAs層6と揃
え、硬化させてこの部分に電極16を形成すれば良い。
LEDアレイのLED密度は、例えば400dpi等と
する。
The LED array of FIG. 1 is manufactured as follows. As shown in FIG. 6, the surface of the silicon substrate 2 is thermally oxidized to form the SiO film 30. This is partially etched to provide a window. Then, a GaAs layer 6 is formed in the window portion by epitaxial growth, the SiO film 30 is etched, and the surface is protected by the SiN protective layer 14. Si
The O film 30 may be replaced with a SiN film, a SiO 2 film, or the like.
After these, the electrode 16 is provided by sputtering or vacuum deposition. Here, as shown in the figure, if the end portion of the GaAs layer 6 is not perpendicular to the silicon substrate 2 but is inclined, the height of the surface changes continuously, so that the electrode 16 is easily formed. When it is difficult to form the electrode 16 due to the difference in surface height between the GaAs layer 6 and the silicon substrate 2, for example, Ga
SiO or SiN or the like is deposited on the portion other than the As layer 6 to make the surface height uniform, or a resist is applied to the portion other than the GaAs layer 6 and the height is made uniform with the GaAs layer 6 by lapping and hardened to this portion. The electrode 16 may be formed.
The LED density of the LED array is, for example, 400 dpi.

【0010】ワイヤボンディングは、例えば次のように
行う。線径20〜30μm程度の金線20、特に線径2
5〜30μmの金線20を用意し、シリコン基板2と共
にGaAs層6を加熱した状態で、金線20と電極16
の外部接続層18との間に超音波振動を加え、金線20
に加えた加圧力と超音波振動とで金線を外部接続層18
にワイヤボンディングする。ここでシリコン基板2はG
aAs層6に比べ強固で、ボンディング時の衝撃や加圧
力による損傷は少なく、仮に損傷が生じたとしてもシリ
コン基板2が物理的に破壊されるものでなければ、LE
Dアレイの性能に影響を及ぼさない。また実施例では、
シリコン基板2の露出面積はGaAs層6の面積に比べ
て極めて広く、広いシリコン基板2上にワイヤボンディ
ングできるので、金線20相互の接触を防止でき、かつ
ワイヤボンディング部の外部接続層18を局所的に広く
大きくできるので、ボンディングが容易になる。これに
対してGaAs層6上で直接電極16にワイヤボンディ
ングすると、ボンディングの加圧力や衝撃でGaAs層
6の破壊が頻発する。なおワイヤボンディングの種類
は、超音波と熱を併用するものの他に、熱や超音波のみ
を用いるものでも良い。
Wire bonding is performed as follows, for example. Gold wire 20 having a wire diameter of about 20 to 30 μm, especially wire diameter 2
A gold wire 20 having a thickness of 5 to 30 μm is prepared, and the gold wire 20 and the electrode 16 are heated with the GaAs layer 6 being heated together with the silicon substrate 2.
Ultrasonic vibration is applied between the external connection layer 18 and the
The gold wire is connected to the external connection layer 18 by the applied pressure and ultrasonic vibration.
Wire bond to. Here, the silicon substrate 2 is G
If the silicon substrate 2 is stronger than the aAs layer 6, is less damaged by impact or pressure during bonding, and the silicon substrate 2 is not physically destroyed even if damage occurs, LE is used.
It does not affect the performance of the D array. Also, in the example,
The exposed area of the silicon substrate 2 is extremely wider than the area of the GaAs layer 6, and since wire bonding can be performed on the wide silicon substrate 2, mutual contact of the gold wires 20 can be prevented and the external connection layer 18 of the wire bonding portion is locally formed. Since it can be made wider and larger, bonding becomes easier. On the other hand, if the electrode 16 is directly wire-bonded on the GaAs layer 6, the GaAs layer 6 is frequently broken due to the pressure or impact of the bonding. It should be noted that the type of wire bonding may use not only ultrasonic waves and heat but also heat and ultrasonic waves only.

【0011】図2に、第2の実施例を示す。LEDアレ
イの製法自体は、図1のものと同様である。図におい
て、26は例えばLEDアレイの制御用のICで、外部
接続層18に設けた金や錫、半田等のバンプ30と、I
C26に設けたバンプ32とを接続し、外部接続とす
る。これはシリコン基板2が安価で大きな基板を用い得
るため、シリコン基板2の遊び部を制御IC等の基板と
して用いたものである。バンプ30は、例えば金線や錫
線を、ワイヤボンディングと同様に超音波と熱を加えな
がら外部接続層18に結合した後、線の根元を切断して
設ける。あるいは通常の半田バンプのように、バリア皮
膜を形成した後に下地導電性金属膜としてのメッキ電極
を形成し、バンプの形成部以外の部分をレジストで覆
い、半田メッキしてバンプを形成する。ついでレジスト
を除き、バンプ以外の部分のバリア皮膜とメッキ電極を
除去する。このような工程をGaAs層6上で行うの
は、金線や錫線からワイヤボンディングと類似の手法で
バンプ形成する場合には、GaAs層6を破壊し、半田
バンプを形成する場合には、GaAs層6を汚染する恐
れが有る。これに対してシリコン基板2の表面でバンプ
30を形成すれば、金線や錫線のワイヤボンディングに
類似の手法でバンプ形成をする場合にはGaAs層6に
影響を与えず、半田バンプの場合でもGaAs層6をレ
ジストで保護しておくだけでよい。
FIG. 2 shows a second embodiment. The manufacturing method itself of the LED array is similar to that of FIG. In the figure, 26 is an IC for controlling an LED array, for example, and bumps 30 such as gold, tin, and solder provided on the external connection layer 18 and I
The bumps 32 provided on C26 are connected to make an external connection. Since the silicon substrate 2 is inexpensive and a large substrate can be used, the play portion of the silicon substrate 2 is used as a substrate for a control IC or the like. The bump 30 is provided, for example, by bonding a gold wire or a tin wire to the external connection layer 18 while applying ultrasonic waves and heat as in the wire bonding, and then cutting the root of the wire. Alternatively, like a normal solder bump, after forming a barrier film, a plating electrode as a base conductive metal film is formed, a portion other than the bump formation portion is covered with a resist, and solder plating is performed to form a bump. Then, the resist is removed, and the barrier film and the plated electrode other than the bumps are removed. Such a process is performed on the GaAs layer 6 when the bumps are formed from a gold wire or a tin wire by a method similar to the wire bonding, the GaAs layer 6 is destroyed, and the solder bumps are formed. There is a risk of contaminating the GaAs layer 6. On the other hand, if the bumps 30 are formed on the surface of the silicon substrate 2, the GaAs layer 6 is not affected when the bumps are formed by a method similar to the wire bonding of gold wires or tin wires. However, it is only necessary to protect the GaAs layer 6 with a resist.

【0012】図3に、第3の実施例を示す。LEDアレ
イの製法自体は、図1のものと同様である。図におい
て、17はGaAs層6の表面を左右に縦断するように
配置した電極層、34はLEDプリンタヘッドのガラス
基板で、36はガラス基板34に設けたデータ配線であ
る。データ配線36は発光層の上部には設けず、データ
配線36による光散乱を防止することが好ましい。バン
プ30,32の合計厚さはGaAs層6の厚さよりもや
や大きくなるようにし、LEDアレイの発光層がガラス
基板34に対向するようにする。このようにすればワイ
ヤボンディングなしで、LEDアレイを外部接続でき、
高密度化に伴う金線20相互のショートを解消できる。
またガラス基板34を基準に発光層の高さを揃え、シリ
コン基板2等の厚さのばらつきによる発光層の高さのば
らつきを解消し、焦点性能を向上できる。
FIG. 3 shows a third embodiment. The manufacturing method itself of the LED array is similar to that of FIG. In the figure, 17 is an electrode layer arranged so as to vertically cross the surface of the GaAs layer 6, 34 is a glass substrate of the LED printer head, and 36 is a data wiring provided on the glass substrate 34. It is preferable that the data wiring 36 is not provided on the light emitting layer to prevent light scattering by the data wiring 36. The total thickness of the bumps 30 and 32 is set to be slightly larger than the thickness of the GaAs layer 6, and the light emitting layer of the LED array faces the glass substrate 34. By doing this, the LED array can be externally connected without wire bonding.
It is possible to eliminate a short circuit between the gold wires 20 due to the high density.
Further, the heights of the light emitting layers are made uniform with respect to the glass substrate 34, and the variation in the heights of the light emitting layers due to the variation in the thickness of the silicon substrate 2 or the like can be eliminated, and the focus performance can be improved.

【0013】図3では、電極17をGaAs層6を縦断
するように形成した。この理由を図4に示す。図に示し
たものはデータ配線36と電極層17の接続関係であ
る。LEDプリンタヘッドでは、多数のLEDアレイを
用い、例えば時分割駆動で1アレイずつ動作させる。こ
のためデータ配線36も、例えば1アレイ分の本数(例
えば64本)だけ形成する。そして配線の便宜のため、
データ配線36を1アレイ毎に折り返して配置する。ま
たLEDアレイの発光層の付近には、光の散乱を防止す
るためデータ配線36を設けない。ここで電極層17で
データ配線36をバイパスし、配線を完成する。このよ
うにしないと、発光層の正面にもデータ配線36を設け
ることになり、LEDアレイからの光が散乱され効率が
低下する。
In FIG. 3, the electrode 17 is formed so as to cross the GaAs layer 6 vertically. The reason for this is shown in FIG. What is shown in the figure is the connection relationship between the data wiring 36 and the electrode layer 17. In the LED printer head, a large number of LED arrays are used, and each array is operated by time-division drive, for example. Therefore, the data wirings 36 are also formed, for example, by the number of one array (for example, 64). And for the convenience of wiring,
The data wiring 36 is arranged so as to be folded back for each array. Further, the data wiring 36 is not provided near the light emitting layer of the LED array in order to prevent light scattering. Here, the electrode layer 17 bypasses the data wiring 36 to complete the wiring. If this is not done, the data wiring 36 will also be provided in front of the light emitting layer, and the light from the LED array will be scattered and the efficiency will decrease.

【0014】図5に、第4の実施例を示す。この実施例
は図2の実施例の変形で、シリコン基板2の一部の図の
右側の領域38に、LEDアレイの電源や制御IC等を
作り付け、保護層14に設けた窓から外部接続層18を
接続したものである。このようにすれば1枚のシリコン
基板2にGaAsLEDアレイと制御回路とを組み込む
ことができる。
FIG. 5 shows a fourth embodiment. This embodiment is a modification of the embodiment of FIG. 2, in which a part of the silicon substrate 2 on the right side of the drawing is provided with a power supply for the LED array, a control IC, etc. 18 is connected. In this way, the GaAs LED array and the control circuit can be incorporated in one silicon substrate 2.

【0015】[0015]

【発明の効果】この発明では、ワイヤボンディングやバ
ンプ形成に伴う破壊や汚染なしに、LEDアレイのGa
As層の電極を外部に接続することができる。例えばワ
イヤボンディングの場合には、加圧力や超音波等による
GaAs層の破壊を避けることができ、またバンプの場
合にはバリア皮膜の形成やメッキ電極の形成、半田メッ
キ等の工程をGaAs層以外の部分で行うことができ、
GaAs層の汚染を防止できる。
According to the present invention, the Ga of the LED array is not damaged or destroyed due to wire bonding or bump formation.
The electrode of the As layer can be connected to the outside. For example, in the case of wire bonding, destruction of the GaAs layer due to pressing force or ultrasonic waves can be avoided, and in the case of bumps, steps such as barrier film formation, plating electrode formation, solder plating, etc. can be performed with the exception of the GaAs layer. Can be done in part
The contamination of the GaAs layer can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】 第1の実施例の断面図FIG. 1 is a sectional view of a first embodiment.

【図2】 第2の実施例の断面図FIG. 2 is a sectional view of a second embodiment.

【図3】 第3の実施例の断面図FIG. 3 is a sectional view of a third embodiment.

【図4】 第3の実施例の電極構成を示す図FIG. 4 is a diagram showing an electrode configuration of a third embodiment.

【図5】 第4の実施例の断面図FIG. 5 is a sectional view of a fourth embodiment.

【図6】 実施例の製造工程を示す断面図FIG. 6 is a cross-sectional view showing a manufacturing process of an example.

【符号の説明】[Explanation of symbols]

2 シリコン基板 6 GaAs層 16 電極層 18 外部接続層 30 バンプ 32 バンプ 34 ガラス基板 36 データ配線 38 制御IC形成領域 2 Silicon substrate 6 GaAs layer 16 Electrode layer 18 External connection layer 30 Bump 32 Bump 34 Glass substrate 36 Data wiring 38 Control IC formation area

フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H04N 1/036 A 9070−5C 1/04 101 7251−5C Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI Technical display location H04N 1/036 A 9070-5C 1/04 101 7251-5C

Claims (1)

【特許請求の範囲】 【請求項1】 GaAsとは異なる材質から成る異種基
板上に、発光層のGaAs層をエピタキシャル成長させ
たLEDアレイにおいて、 上記GaAs層の表面に電極層を形成し、かつ該電極層
を前記異種基板上に引出し、ここで外部接続することを
特徴とする、LEDアレイ。
Claim: What is claimed is: 1. In an LED array in which a GaAs layer as a light emitting layer is epitaxially grown on a heterogeneous substrate made of a material different from GaAs, an electrode layer is formed on the surface of the GaAs layer, and An LED array, wherein an electrode layer is drawn onto the different type substrate and externally connected thereto.
JP21584091A 1991-07-31 1991-07-31 Led array Pending JPH0537027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21584091A JPH0537027A (en) 1991-07-31 1991-07-31 Led array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21584091A JPH0537027A (en) 1991-07-31 1991-07-31 Led array

Publications (1)

Publication Number Publication Date
JPH0537027A true JPH0537027A (en) 1993-02-12

Family

ID=16679139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21584091A Pending JPH0537027A (en) 1991-07-31 1991-07-31 Led array

Country Status (1)

Country Link
JP (1) JPH0537027A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015189037A (en) * 2014-03-27 2015-11-02 株式会社沖データ Semiconductor device, light exposure head and image forming device
JP2015189036A (en) * 2014-03-27 2015-11-02 株式会社沖データ Semiconductor device, light exposure head and image forming device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015189037A (en) * 2014-03-27 2015-11-02 株式会社沖データ Semiconductor device, light exposure head and image forming device
JP2015189036A (en) * 2014-03-27 2015-11-02 株式会社沖データ Semiconductor device, light exposure head and image forming device

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