JPH0613715A - Edge light emitting element and manufacture thereof - Google Patents

Edge light emitting element and manufacture thereof

Info

Publication number
JPH0613715A
JPH0613715A JP16966792A JP16966792A JPH0613715A JP H0613715 A JPH0613715 A JP H0613715A JP 16966792 A JP16966792 A JP 16966792A JP 16966792 A JP16966792 A JP 16966792A JP H0613715 A JPH0613715 A JP H0613715A
Authority
JP
Japan
Prior art keywords
film
layer
semiconductor
semiconductor wafer
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16966792A
Other languages
Japanese (ja)
Inventor
Kaoru Kusunoki
薫 楠
Masahito Mushigami
雅人 虫上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP16966792A priority Critical patent/JPH0613715A/en
Publication of JPH0613715A publication Critical patent/JPH0613715A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

PURPOSE:To easily form a thin element of a semiconductor layer by a method wherein an electrode film is formed on both sides of the semiconductor layer, and the electrode film of an end light-emitting element, where light is emitted from the side face, is cleaved without patterning. CONSTITUTION:This edge light-emitting element is formed by laminating a compound semiconductor layer and electrode films 12 and 13 formed on both surfaces of a semiconductor wafer 1, and a beam of light is emitted from the side face. The outermost layer of Au films 3 and 7 of the electrode films 12 and 13 are formed thick 1500 to 2500Angstrom .

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップの端面
(側面)から発光する端面発光素子およびその製法に関
する。さらに詳しくは、半導体基板の両面に形成される
電極膜のうち金被膜の厚さを薄くして劈開しやすくした
端面発光素子およびその製法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an end face light emitting device which emits light from an end face (side face) of a semiconductor chip and a method for manufacturing the same. More specifically, the present invention relates to an end face light emitting device in which a gold film of an electrode film formed on both surfaces of a semiconductor substrate is thinned to facilitate cleavage, and a manufacturing method thereof.

【0002】[0002]

【従来の技術】半導体レーザやスーパールミネッセント
ダイオードなどで半導体チップの端面から発光する端面
発光素子は、GaAsなどの半導体基板にpn接合が形
成された半導体ウエハ21の表面と裏面のほぼ全面に電極
膜22、23として金属被膜が形成される。この電極膜とし
ては、半導体ウエハ21とのオーミックコンタクトをとる
ためのAuGe膜やTi膜などが形成されると共に、最
上膜にはダイボンディングやワイヤボンディングをし易
くするためAu膜が形成されるなど複数の金属膜で形成
されている。
2. Description of the Related Art An edge emitting element that emits light from an edge of a semiconductor chip with a semiconductor laser, a super luminescent diode, or the like is provided on almost the entire front and back surfaces of a semiconductor wafer 21 having a pn junction formed on a semiconductor substrate such as GaAs. A metal coating is formed as the electrode films 22 and 23. As this electrode film, an AuGe film or a Ti film for forming ohmic contact with the semiconductor wafer 21 is formed, and an Au film is formed on the uppermost film to facilitate die bonding or wire bonding. It is formed of a plurality of metal films.

【0003】そののち、半導体ウエハ21を切断分離して
各半導体チップを製造するのであるが、端面発光素子で
は各チップに切断分離した切断面から発光させるため、
切断面は完全な平面になっていないと、光が一定方向に
発射されない。そのためこの種の端面発光素子では、各
半導体チップに分離するのにダイヤモンドカッタで切断
することは適さず、半導体結晶面を利用した劈開により
切断分離がなされている。
After that, the semiconductor wafer 21 is cut and separated to manufacture each semiconductor chip. In the edge emitting element, each chip is made to emit light from the cut surface.
If the cut surface is not perfectly flat, light will not be emitted in one direction. Therefore, in this type of edge emitting device, it is not suitable to cut with a diamond cutter to separate each semiconductor chip, and the semiconductor chip is cut and separated by cleavage.

【0004】前述の電極膜のうち、Au膜は3000〜1000
0 Åの厚さに形成されており、Auには延性および展性
があるため、半導体ウエハ21は結晶面に沿って劈開しや
すいがAu膜の切断はしにくい。そのため、あらかじめ
半導体ウエハ21を劈開する場所の電極膜22、23を除去
し、図3〜4に示すように、電極膜22、23の縦方向およ
び横方向に複数の溝24、25が穿設されたパターンを形成
する必要がある。パターンの形成工程は、露光工程とエ
ッチング工程からなり、露光工程では半導体ウエハ21上
にレジストを塗布し、塗布されたレジストを露光、現像
してパターンを形成する。このレジストを塗布する際、
半導体ウエハ21を真空チャックで吸着して回転させなが
らスピンコートにより塗布する。また、エッチング工程
では露光工程で形成されたレジストをマスクとして下地
膜である電極膜22、23を食刻し電極膜22、23のパターン
が形成される。
Of the above-mentioned electrode films, the Au film is 3000-1000.
Since it is formed to have a thickness of 0Å and Au has ductility and malleability, the semiconductor wafer 21 is likely to be cleaved along the crystal plane, but the Au film is difficult to cut. Therefore, the electrode films 22 and 23 at the positions where the semiconductor wafer 21 is cleaved are removed in advance, and a plurality of grooves 24 and 25 are formed in the vertical and horizontal directions of the electrode films 22 and 23 as shown in FIGS. It is necessary to form a patterned pattern. The pattern forming step includes an exposure step and an etching step. In the exposure step, a resist is applied on the semiconductor wafer 21, and the applied resist is exposed and developed to form a pattern. When applying this resist,
The semiconductor wafer 21 is attracted by a vacuum chuck and applied by spin coating while rotating. In the etching process, the resist films formed in the exposure process are used as masks to etch the electrode films 22 and 23 that are base films to form patterns of the electrode films 22 and 23.

【0005】[0005]

【発明が解決しようとする課題】この従来技術によって
半導体ウエハを劈開しチップを作製するばあい、前記露
光工程におけるレジスト塗布の工程でウエハを真空チャ
ックで固定し、回転させる必要がある。このばあい、半
導体ウエハの厚さが150 μm以下になると真空チャック
による半導体ウエハの把持力によって半導体ウエハが割
れ易くなる。また一方、半導体ウエハが割れないように
真空チャックの把持力を弱くすると真空チャックの回転
により半導体ウエハに遠心力が働いて真空チャックから
離脱する。
When a semiconductor wafer is cleaved and chips are produced by this conventional technique, it is necessary to fix the wafer with a vacuum chuck and rotate it in the resist coating step in the exposure step. In this case, when the thickness of the semiconductor wafer is 150 μm or less, the semiconductor wafer is easily broken due to the gripping force of the semiconductor wafer by the vacuum chuck. On the other hand, if the gripping force of the vacuum chuck is weakened so that the semiconductor wafer is not cracked, centrifugal force acts on the semiconductor wafer due to the rotation of the vacuum chuck, and the semiconductor wafer is separated from the vacuum chuck.

【0006】したがって、厚さの薄い端面発光用半導体
チップを作製するのに、電極膜にパターンを形成するこ
とは不良率の増大につながり、パターンを形成できな
い。一方、端面発光素子では前述のように劈開面を利用
する必要があり(たとえば、伊藤良一ら「半導体レー
ザ」23頁(1989年))、チップ化のためには劈開が必要
であるが、電極膜が厚いばあい劈開時に電極膜が切断で
きず、薄い(150 μm以下)半導体層の端面発光用半導
体チップがえられないという問題がある。
Therefore, forming a pattern on the electrode film in manufacturing a thin edge emitting semiconductor chip leads to an increase in the defective rate, and the pattern cannot be formed. On the other hand, in the edge emitting element, it is necessary to utilize the cleavage plane as described above (for example, Ryoichi Ito et al., “Semiconductor Laser” page 23 (1989)), and cleavage is required for chip formation, but the electrode If the film is thick, the electrode film cannot be cut at the time of cleavage, and there is a problem that a thin (150 μm or less) semiconductor chip for edge emitting cannot be obtained.

【0007】本発明の目的は、半導体ウエハの両面に形
成されるAu膜の厚さを薄くし、パターニングしなくて
も容易に半導体チップ化できるようにすると共に、半導
体チップの厚さの薄い端面発光素子を提供することにあ
る。
An object of the present invention is to reduce the thickness of the Au film formed on both sides of a semiconductor wafer so that it can be easily made into a semiconductor chip without patterning, and the end face having a small thickness of the semiconductor chip can be formed. It is to provide a light emitting element.

【0008】[0008]

【課題を解決するための手段】本発明による端面発光素
子は、p型層とn型層の化合物半導体層の積層により半
導体チップが形成され、該半導体チップの両面の全面に
電極膜が形成され、該半導体チップの側面から発光する
端面発光素子であって、前記電極膜の最外層はAu膜で
形成され、かつ、該Au膜が1500〜2500Åに形成されて
いることを特徴とするものである。
In the edge emitting device according to the present invention, a semiconductor chip is formed by laminating a compound semiconductor layer of a p-type layer and an n-type layer, and electrode films are formed on the entire surfaces of both sides of the semiconductor chip. An end face light emitting device which emits light from a side surface of the semiconductor chip, wherein the outermost layer of the electrode film is formed of an Au film, and the Au film is formed in a range of 1500 to 2500Å. is there.

【0009】また、本発明による半導体レーザは、化合
物半導体基板に化合物半導体層で下部クラッド層、活性
層、第1の上部クラッド層、電流制限層、第2の上部ク
ラッド層、キャップ層が少なくとも形成され、上面と下
面に電極膜が形成されてなる半導体レーザであって、前
記電極膜の最外層はAu膜で形成され、かつ、該Au膜
が1500〜2500Åに形成されていることを特徴とするもの
である。
Further, in the semiconductor laser according to the present invention, at least the lower clad layer, the active layer, the first upper clad layer, the current limiting layer, the second upper clad layer and the cap layer are formed on the compound semiconductor substrate as the compound semiconductor layer. And an outermost layer of the electrode film is formed of an Au film, and the Au film is formed to have a thickness of 1500 to 2500Å. To do.

【0010】さらに、本発明による端面発光素子の製法
は、(a) 化合物半導体基板に化合物半導体層を積層し発
光用半導体ウエハを形成する工程、(b) 該半導体ウエハ
の両面に最外層がAu膜となるように電極膜を形成する
工程、(c) 前記半導体ウエハを結晶面に沿って劈開し半
導体チップを形成する工程、および(d) 該半導体チップ
をダイボンディング、ワイヤボンディングする工程から
なることを特徴とするものである。
Further, the manufacturing method of the edge emitting device according to the present invention is (a) a step of laminating a compound semiconductor layer on a compound semiconductor substrate to form a light emitting semiconductor wafer, and (b) an outermost layer of Au on both sides of the semiconductor wafer. A step of forming an electrode film so as to form a film, (c) a step of forming a semiconductor chip by cleaving the semiconductor wafer along a crystal plane, and (d) a step of die-bonding and wire-bonding the semiconductor chip It is characterized by that.

【0011】[0011]

【作用】本発明によれば、パターニングしなくても半導
体ウエハの劈開により電極膜も切断されると共にダイボ
ンディングやワイヤボンディングを確実にできるAu膜
の厚さを見出してAu膜の厚さが制御されているため、
電極膜にパターンを形成しなくても容易に劈開でき、半
導体チップ化の際に不良が発生することなく、ボンディ
ング性のよい半導体層の薄い端面発光素子用の半導体チ
ップがえられる。。
According to the present invention, the electrode film is cut by the cleavage of the semiconductor wafer without patterning, and the thickness of the Au film is controlled by finding the thickness of the Au film that can surely perform die bonding or wire bonding. Because it has been
Cleavage can be easily performed without forming a pattern on the electrode film, and a semiconductor chip for an edge emitting device having a thin semiconductor layer with good bonding properties can be obtained without causing a defect in forming a semiconductor chip. .

【0012】[0012]

【実施例】つぎに添付図面に基づき本発明の端面発光素
子について詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The edge emitting device of the present invention will be described in detail with reference to the accompanying drawings.

【0013】図1は半導体レーザ用の半導体ウエハの両
面に電極膜が形成された状態の部分的断面説明図であ
る。同図において、1は半導体ウエハで、たとえば図2
に示されるような詳細構造になっている。すなわち、20
0 〜500 μm厚のGaAs基板10上に下部クラッド層11
がたとえば、n型Alx Ga1-x As(0.3 ≦x≦0.
7)層で厚さ約 1.3μm、MBE(分子線エピタキシ
ー)法によりエピタキシャル成長され、その上にさらに
引き続き約0.05μmの厚さで活性層14としてアンドープ
のAlx Ga1-x As(0≦x≦0.2 )層がエピタキシ
ャル成長され、さらにその上に第1の上クラッド層15と
してp型Alx Ga1-x As(0.3 ≦x≦0.7)層が約
0.3 μmエピタキシャル成長され、その上にさらに電流
制限層16としてn型GaAs層が約0.6 μmエピタキシ
ャル成長され、さらにその上に蒸発防止層17としてのn
型Alx Ga1-x As(0.05≦x≦0.2 )層が0.1 μm
エピタキシャル成長され、エッチングによりストライプ
溝が形成され、電流の流れる範囲が制限される。このス
トライプ溝のエッチングの際には、電流制限層16のGa
As層が0.1 μm程度残るようにエッチングし、第1の
上クラッド層15であるAlx Ga1-x As層が直接露出
しないようにする。
FIG. 1 is a partial cross sectional view showing a state in which electrode films are formed on both sides of a semiconductor wafer for a semiconductor laser. In the figure, 1 is a semiconductor wafer, for example, as shown in FIG.
The detailed structure is as shown in. Ie 20
Lower clad layer 11 on GaAs substrate 10 with thickness of 0 to 500 μm
Is, for example, n-type Al x Ga 1-x As (0.3 ≦ x ≦ 0.
7) layer having a thickness of about 1.3 μm, which is epitaxially grown by MBE (Molecular Beam Epitaxy) method, and on top of that, an undoped Al x Ga 1-x As (0 ≦ x ≦ 0.2) layer is epitaxially grown, and a p-type Al x Ga 1-x As (0.3 ≦ x ≦ 0.7) layer is further formed thereon as the first upper cladding layer 15.
An n-type GaAs layer is further epitaxially grown to a thickness of about 0.6 μm as a current limiting layer 16 on the n-type GaAs layer, and an n-type GaAs layer is formed thereon as an evaporation preventing layer 17.
Type Al x Ga 1-x As (0.05 ≦ x ≦ 0.2) layer is 0.1 μm
Epitaxial growth is performed and stripe grooves are formed by etching to limit the range of current flow. When the stripe groove is etched, the Ga of the current limiting layer 16 is
Etching is performed so that the As layer remains about 0.1 μm so that the Al x Ga 1-x As layer, which is the first upper cladding layer 15, is not directly exposed.

【0014】ついで、再度MBE装置に基板を入れ、表
面にヒ素分子線を照射しながら、基板を740 ℃〜760 ℃
に加熱する。この温度では、GaAs層は再蒸発するが
Alx Ga1-x As(x≧0.05)層は再蒸発しないの
で、ストライプ溝のGaAs層のみが除去され、第1の
上クラッド層15のAlx Ga1-x As層が露出する(サ
ーマルエッチング工程)。このとき、電流制限層16のG
aAs層の表面は蒸発防止層17が形成されているため、
蒸発せず、ストライプ溝の部分のみが蒸発する。つぎに
2回目のMBE工程により第2の上クラッド層18として
のp型Alx Ga1-x As(0.3 ≦x≦0.7 )層を約1
μmおよびキャップ層19としてのp型GaAs層を約2
μmエピタキシャル成長して積層する。そののち、Ga
As基板側をラッピングにより研磨して薄層化し、上下
に各々の電極膜12、13をそれぞれ形成する。
Then, the substrate is put into the MBE apparatus again, and the surface of the substrate is irradiated with arsenic molecular beam, and the substrate is heated at 740 ° C to 760 ° C.
Heat to. At this temperature, the GaAs layer re-evaporates, but the Al x Ga 1-x As (x ≧ 0.05) layer does not re-evaporate, so only the GaAs layer in the stripe groove is removed and the Al x of the first upper cladding layer 15 is removed. The Ga 1-x As layer is exposed (thermal etching step). At this time, G of the current limiting layer 16
Since the evaporation prevention layer 17 is formed on the surface of the aAs layer,
It does not evaporate, only the stripe groove part evaporates. Then, a second MBE process was performed to form about 1 p-type Al x Ga 1-x As (0.3 ≤ x ≤ 0.7) layer as the second upper cladding layer 18.
μm and the p-type GaAs layer as the cap layer 19 is about 2
μm is epitaxially grown and laminated. After that, Ga
The As substrate side is polished by lapping to make a thin layer, and electrode films 12 and 13 are formed on the upper and lower sides, respectively.

【0015】この半導体ウエハの上面と下面には電極膜
12、13が蒸着法またはスパッタ法により複数の金属膜で
それぞれ形成されている。まず上面の電極膜12は1000Å
の厚さのTi膜2と2000Åの厚さのAu膜3が形成され
ている。この半導体ウエハ1の上面側は不純物としてB
eが1×1019cm-3程度にドーピングされているため、オ
ーミックコンタクトをとり易く、直接Ti膜が形成され
ている。このTi膜2はAuが半導体層に侵入して反応
し、素子を劣化させないようにバリア金属として形成さ
れるもので、Ti膜2は展性や延性がAuに比べて劣る
ため、厚さの制限は余り問題とならず、500 〜2000Åの
範囲で形成される。また、Au膜3は後述するように15
00〜2500Åにすることにより電極膜をパターニングする
ことなく半導体ウエハを劈開でき、かつ、半導体チップ
をリード端子に固着すると共に電気的接続するダイボン
ディングや半導体チップの電極とリードとを金線などで
電気的接続するワイヤボンディングを支障なく行なえる
ものである。
Electrode films are formed on the upper and lower surfaces of this semiconductor wafer.
12 and 13 are each formed of a plurality of metal films by a vapor deposition method or a sputtering method. First, the top electrode film 12 is 1000Å
A Ti film 2 having a thickness of 2000 and an Au film 3 having a thickness of 2000 Å are formed. The upper surface side of the semiconductor wafer 1 is B as an impurity.
Since e is doped to about 1 × 10 19 cm −3, it is easy to make ohmic contact and a Ti film is directly formed. The Ti film 2 is formed as a barrier metal so that Au does not enter the semiconductor layer and reacts therewith and does not deteriorate the element. Since the Ti film 2 is inferior in malleability and ductility to Au, the Ti film 2 has a large thickness. The limit is not so problematic and is formed in the range of 500 to 2000Å. Further, the Au film 3 has a thickness of 15 as described later.
By setting 00 to 2500Å, the semiconductor wafer can be cleaved without patterning the electrode film, and the semiconductor chip can be fixed to the lead terminals and die bonding for electrical connection and the electrodes and leads of the semiconductor chip can be made with gold wires. Wire bonding for electrical connection can be performed without any trouble.

【0016】また、半導体ウエハ1の裏面側はSiが不
純物として2×1018cm-3程度の濃度になるようにドーピ
ングされてn型に形成されているため、オーミックコン
タクトが形成されにくく、GaAs半導体基板にまずA
uGe(たとえばGeの割合は12at%)膜4が2000Å、
蒸着法またはスパッタ法により形成される。さらに膜の
密着性をよくするためのNi膜5が100 Å、バリア金属
としてのTi膜6が500 Å、最後に半導体チップを接着
するダイボンディングを電気接触よく確実に行うための
Au膜7が2000Å形成されている。
Further, since Si is doped on the back surface side of the semiconductor wafer 1 as an impurity so as to have a concentration of about 2 × 10 18 cm −3 to form an n-type, it is difficult to form an ohmic contact and GaAs is formed. First, the semiconductor substrate A
uGe (for example, the proportion of Ge is 12 at%) film 4 has 2000 Å,
It is formed by a vapor deposition method or a sputtering method. Further, the Ni film 5 for improving the adhesion of the film is 100 Å, the Ti film 6 as the barrier metal is 500 Å, and finally the Au film 7 for securely performing the die bonding for adhering the semiconductor chip with good electric contact. 2000Å formed.

【0017】この裏面側の電極膜もAuGe、Ni、T
iの各膜はAuに比べて展性や延性に劣り、前述の上面
側と同様これらの膜厚の制限は余り問題とならず、それ
ぞれ従来用いられている1500〜2500、50〜150 、500 〜
1000Åに形成されるが、Au膜7は前述と同様に1500〜
2500Åに形成される。
This back side electrode film is also made of AuGe, Ni, T
The respective films of i are inferior in malleability and ductility as compared with Au, and like the above-mentioned upper surface side, the limitation of these film thicknesses does not pose a problem so much, and the conventionally used 1500 to 2500, 50 to 150, and 500 respectively. ~
It is formed to 1000 Å, but the Au film 7 is 1500 to
Formed to 2500Å.

【0018】つぎに、電極膜に用いるAu膜の厚さにつ
いて説明する。前述のように半導体ウエハ1の厚さが15
0 μm以下になると電極膜をパターニングする際、半導
体ウエハ1に割れが発生して歩留が低下し、一方パター
ニングを行わないと半導体ウエハを劈開する際に、電極
膜が切断されず、端面発光する半導体チップを歩留りよ
くえられない。そこで発明者らは鋭意検討を重ねた結
果、電極膜のうち展性、延性に富むAu膜3、7の厚さ
を1500〜2500Åに制御することにより、金属膜のパター
ニングをしなくても半導体ウエハ1を劈開する際に電極
膜も切断でき各半導体チップに分離できると共に、ダイ
ボンディングやワイヤボンディングの際の電気的接続も
確実にできることを見出した。
Next, the thickness of the Au film used as the electrode film will be described. As described above, the thickness of the semiconductor wafer 1 is 15
When the thickness is 0 μm or less, cracking occurs in the semiconductor wafer 1 when patterning the electrode film, and the yield is reduced. On the other hand, when patterning is not performed, the electrode film is not cut when the semiconductor wafer is cleaved, and edge emission The yield of semiconductor chips does not increase. Therefore, as a result of intensive studies by the inventors, by controlling the thickness of the Au films 3 and 7 having high malleability and ductility in the electrode film to 1500 to 2500 Å, the semiconductor film can be formed without patterning the metal film. It has been found that when the wafer 1 is cleaved, the electrode film can be cut and separated into semiconductor chips, and electrical connection can be surely made during die bonding and wire bonding.

【0019】すなわち、まず、Au膜以外のTi膜やA
uGe膜、Ni膜などは前述の厚さで一定にしておき、
半導体ウエハ1の厚さを60μmで形成し、Au膜3、7
のみを1000、1500、2000、2500、3000、4000Åと変えた
ときの半導体ウエハの劈開性とボンディング性(ボンデ
ィング不良が生じない)について調べた。歩留が90%以
上のものを良として良好のものを○、不良のものを×と
して表1に示す結果がえられた。
That is, first, a Ti film or an A film other than the Au film is formed.
The uGe film, the Ni film, etc. are kept constant with the above-mentioned thickness,
The semiconductor wafer 1 is formed to a thickness of 60 μm, and the Au films 3 and 7 are formed.
Cleavability and bondability (no bonding failure) of the semiconductor wafer were investigated when the values were changed to 1000, 1500, 2000, 2500, 3000, 4000Å. The results shown in Table 1 were obtained when the yield was 90% or more as good and as good, and as bad.

【0020】[0020]

【表1】 [Table 1]

【0021】表1からも明らかなようにAu膜の厚さを
1500〜2500Åにすることにより、劈開性、ボンディング
性共に優れ、パターニングせずに半導体チップ化が可能
となった。また、1000Åでのボンディング性の不良はワ
イヤボンディングが剥れることによる不良が大部分で、
ボンディングの接着強度が弱いことによるもので、接触
抵抗が大きく発光特性が劣化したものも含まれている。
As is clear from Table 1, the thickness of the Au film is
By selecting 1500 to 2500Å, both cleavage and bonding properties are excellent, and semiconductor chips can be formed without patterning. In addition, most of the defective bonding properties at 1000Å are due to peeling of wire bonding,
This is because the bonding strength of the bonding is weak, and some of them have large contact resistance and deteriorated light emission characteristics.

【0022】つぎにAuGe膜4とTi膜2、5をそれ
ぞれ前述の例の倍の厚さである4000Åと1000Åとし、A
u膜3、7を2000Åにして同様に劈開性とボンディング
性を調べた。その結果、いずれも良好で、AuGe膜や
Ti膜などの金属膜は厚く形成されても半導体ウエハ1
の劈開性には何ら影響せず、Au膜のみを1500〜2500Å
に形成することにより劈開性、ボンディング性共に満足
することを見出した。
Next, the AuGe film 4 and the Ti films 2 and 5 are set to 4000 Å and 1000 Å, which are double the thickness of the above-mentioned example, respectively.
Cleavability and bondability were similarly examined by setting the u films 3 and 7 to 2000 Å. As a result, all of them are good, and even if the metal film such as the AuGe film or the Ti film is formed thick, the semiconductor wafer 1
It has no effect on the cleavage property of Cu, and only Au film is 1500-2500Å
It was found that the cleavage property and the bonding property are satisfied by forming the film.

【0023】なお、前述の実施例ではn型GaAs基板
に下部クラッド層、活性層などを積層して上面にp型G
aAs層が形成された半導体レーザの例で上面の電極膜
が2層、下面の電極膜が4層の例で説明したが、半導体
レーザ以外の端面発光素子にも同様に適用でき、また電
極膜の形成はこの例に限らず、他の組合せの積層でもよ
く、さらにn型とp型が逆に形成されれば電極膜の積層
構造が変り、また半導体基板がGaAsでなく、InP
などに変ることによっても電極膜の構成は変りうるが、
いずれのばあいにも最外層にボンディング性のためAu
膜が形成され、そのAu膜の厚さが前述の1500〜2500Å
に形成されることにより電極膜をパターニングすること
なく、半導体ウエハを劈開でき、しかもダイボンディン
グ、ワイヤボンディング共に良好にできる。
In the above embodiment, the lower cladding layer, the active layer, etc. are laminated on the n-type GaAs substrate and the p-type G is formed on the upper surface.
In the example of the semiconductor laser in which the aAs layer is formed, the example in which the upper electrode film is two layers and the lower electrode film is four layers has been described, but the same can be applied to edge emitting elements other than the semiconductor laser. Is not limited to this example, and other combinations of laminated layers may be used. Further, if the n-type and p-type are formed in reverse, the laminated structure of the electrode film changes, and the semiconductor substrate is not GaAs but InP
The structure of the electrode film may change due to changes such as
In both cases, Au is bonded to the outermost layer due to its bonding property.
A film is formed, and the thickness of the Au film is 1500 to 2500Å as described above.
By forming the film, the semiconductor wafer can be cleaved without patterning the electrode film, and the die bonding and the wire bonding can be performed well.

【0024】[0024]

【発明の効果】本発明によれば、端面発光素子用の半導
体ウエハの両面に形成される電極膜のうち、Au膜が15
00〜2500Åと薄く形成されているため、電極膜をパター
ニングすることなく、半導体ウエハを劈開することによ
り各半導体チップに分離できる。
According to the present invention, of the electrode films formed on both surfaces of the semiconductor wafer for the edge emitting device, the Au film is 15
Since it is formed as thin as 00 to 2500Å, it can be separated into each semiconductor chip by cleaving the semiconductor wafer without patterning the electrode film.

【0025】その結果電極膜をパターニングする必要が
なく、工数を大幅に削減できると共に、パターニングの
ためのレジスト塗布の際の半導体ウエハの割れなどによ
る不良品も発生せず、コストダウンに大いに寄与する。
As a result, it is not necessary to pattern the electrode film, the number of steps can be greatly reduced, and defective products due to cracking of a semiconductor wafer during resist coating for patterning do not occur, which greatly contributes to cost reduction. .

【0026】しかも電極膜をパターニングすることなく
半導体ウエハを劈開できるため、半導体ウエハの厚さが
100 μm以下の薄いものでも、歩留よく半導体チップ化
でき、たとえば3ビーム法に用いられる半導体レーザチ
ップのように、戻り光の回折格子による分岐したビーム
の反射を避けるため、半導体チップの厚さを80μm以下
に薄くすることも可能となり、薄い半導体層の端面発光
素子を実現できる。
Moreover, since the semiconductor wafer can be cleaved without patterning the electrode film, the thickness of the semiconductor wafer is reduced.
Even a thin film of 100 μm or less can be formed into a semiconductor chip with a good yield. For example, like a semiconductor laser chip used in the three-beam method, in order to avoid reflection of a branched beam due to a diffraction grating of return light, the thickness of the semiconductor chip is increased. Can be made as thin as 80 μm or less, and an edge emitting device having a thin semiconductor layer can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である半導体レーザ用ウエハ
の両面に電極膜が形成された状態の断面説明図である。
FIG. 1 is a cross-sectional explanatory view showing a state where electrode films are formed on both surfaces of a semiconductor laser wafer which is an embodiment of the present invention.

【図2】半導体レーザの半導体層の構造を説明する断面
説明図である。
FIG. 2 is a cross-sectional explanatory diagram illustrating a structure of a semiconductor layer of a semiconductor laser.

【図3】従来の端面発光素子の一製造工程である電極膜
をパターニングした状態の斜視図である。
FIG. 3 is a perspective view showing a state where an electrode film is patterned, which is one manufacturing process of a conventional edge emitting device.

【図4】図3の半導体ウエハの平面図である。FIG. 4 is a plan view of the semiconductor wafer of FIG.

【符号の説明】[Explanation of symbols]

1 半導体ウエハ 3、7 Au膜 12、13 電極膜 1 Semiconductor wafer 3, 7 Au film 12, 13 Electrode film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 p型層とn型層の化合物半導体層の積層
により半導体チップが形成され、該半導体チップの両面
の全面に電極膜が形成され、該半導体チップの側面から
発光する端面発光素子であって、前記電極膜の最外層は
Au膜で形成され、かつ、該Au膜が1500〜2500Åに形
成されていることを特徴とする端面発光素子。
1. An end face light emitting device in which a semiconductor chip is formed by stacking compound semiconductor layers of a p-type layer and an n-type layer, electrode films are formed on the entire surfaces of both sides of the semiconductor chip, and light is emitted from the side surface of the semiconductor chip. The outermost layer of the electrode film is formed of an Au film, and the Au film is formed at 1500 to 2500Å.
【請求項2】 化合物半導体基板に化合物半導体層で下
部クラッド層、活性層、第1の上部クラッド層、電流制
限層、第2の上部クラッド層、キャップ層が少なくとも
形成され、上面と下面に電極膜が形成されてなる半導体
レーザであって、前記電極膜の最外層はAu膜で形成さ
れ、かつ、該Au膜が1500〜2500Åに形成されているこ
とを特徴とする半導体レーザ。
2. A compound semiconductor substrate on which at least a lower clad layer, an active layer, a first upper clad layer, a current limiting layer, a second upper clad layer and a cap layer are formed as compound semiconductor layers, and electrodes are formed on the upper and lower surfaces. A semiconductor laser having a film formed, wherein the outermost layer of the electrode film is formed of an Au film, and the Au film is formed in a thickness of 1500 to 2500Å.
【請求項3】 (a) 化合物半導体基板に化合物半導体層
を積層し発光用半導体ウエハを形成する工程、 (b) 該半導体ウエハの両面に最外層がAu膜となるよう
に電極膜を形成する工程、 (c) 前記半導体ウエハを結晶面に沿って劈開し半導体チ
ップを形成する工程、および (d) 該半導体チップをダイボンディング、ワイヤボンデ
ィングする工程からなることを特徴とする端面発光素子
の製法。
3. A step of laminating a compound semiconductor layer on a compound semiconductor substrate to form a light emitting semiconductor wafer, and (b) forming an electrode film on both surfaces of the semiconductor wafer so that the outermost layer is an Au film. A step, (c) a step of cleaving the semiconductor wafer along a crystal plane to form a semiconductor chip, and (d) a step of die-bonding and wire-bonding the semiconductor chip, a method for manufacturing an edge-emitting device. .
JP16966792A 1992-06-26 1992-06-26 Edge light emitting element and manufacture thereof Pending JPH0613715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16966792A JPH0613715A (en) 1992-06-26 1992-06-26 Edge light emitting element and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16966792A JPH0613715A (en) 1992-06-26 1992-06-26 Edge light emitting element and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0613715A true JPH0613715A (en) 1994-01-21

Family

ID=15890689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16966792A Pending JPH0613715A (en) 1992-06-26 1992-06-26 Edge light emitting element and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0613715A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4888339A (en) * 1986-12-09 1989-12-19 Tanabe Seiyaku Co., Ltd. Agent for prophylaxis and treatment of cardiac hypertrophy
US5803640A (en) * 1996-06-04 1998-09-08 Mitsubishi Pencil Kabushiki Kaisha Applicator
JP2010267813A (en) * 2009-05-14 2010-11-25 Toshiba Corp Light emitting device, and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4888339A (en) * 1986-12-09 1989-12-19 Tanabe Seiyaku Co., Ltd. Agent for prophylaxis and treatment of cardiac hypertrophy
US5803640A (en) * 1996-06-04 1998-09-08 Mitsubishi Pencil Kabushiki Kaisha Applicator
JP2010267813A (en) * 2009-05-14 2010-11-25 Toshiba Corp Light emitting device, and method for manufacturing the same

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