JPH0397199A - Dynamic shift register - Google Patents

Abstract

PURPOSE:To reduce number of transistors (TRs) and to decrease the area required for the circuit by adopting the constitution such that only one P-channel TR is used and its control signal is used for precharging. CONSTITUTION:A precharge signal PC1 for a master latch applies precharging at a low level and after the precharge, a data D is fetched by using a clock PHI. In this case, when the data D is at a high level, N-channel TRs 2, 3 are turned on and the output QM of the master latch goes to a low level. Conversely, when the data D is at a low level, the N-channel TR 2 is turned off and the output reaches a high impedance and the precharged high level is kept for a period. Thus, one stage of the P-channel TR is enough and the TR acts like precharging. Thus, the area required for the circuit is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic shift register, and more particularly to a dynamic shift register that operates with a two-phase clock with precharge timing.

[Conventional technology] Conventionally, this type of dynamic shift register has been constructed by connecting an even number of clocked inverters as shown in Figs. The structure is such that the clock φ1 is used as an even-numbered (slave side) control signal, and the second phase clock φ2 is input.

[Problems to be Solved by the Invention] The conventional dynamic shift register described above is of a type in which clocked inverters are connected in series, so the transistors that receive control signals are N-channel (hereinafter abbreviated as Nch) and P-channel (hereinafter referred to as Pch). (abbreviated as )), the area required for this circuit increases because it requires the same number of stages as each other.

An object of the present invention is to provide a dynamic shift register that requires a small circuit area. [Means for Solving the Problems] The dynamic shift register of the present invention has one transistor on the P-channel side per stage. The transistor that is formed of 2 transistors and whose control signal is clock φ1 input to the N-channel transistor becomes low level during the period from when clock φ2 goes low level until clock φ1 goes high level. signal, N
The transistor in which the clock φ2 is input as a control signal to the channel side transistor is characterized in that it uses a signal that becomes low level during the period from when the clock φ1 becomes low level until the clock φ2 becomes high level.

[Operation] The transistor on the Pch side becomes one stage, and that transistor performs a precharging function.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a dynamic shift register according to a first embodiment of the present invention, and FIG. 2 is a timing chart of the circuit shown in FIG.

Pch transistor 1 has PCI as a gate input, and Nc
It is connected to h transistor 2 at the drain, and the output QM becomes the next data input. The clock power Nch transistor 3 uses the clock φl as the gate power, and is connected to the Nch transistor 2 at the drain. These constitute the master-side latch of the first-stage flip-flop. Transistors 4, 5.6 constitute the slave side latch of the flip-flop, and correspond to transistors 1, 2.3 of the master side latch, respectively.

Next, the operation of this embodiment will be explained with reference to FIG.

Pct is a precharge signal for the master side latch, and performs precharging during a low level period. After this precharge, data D is taken in at clock φ1. At this time, when data D is at a high level, Nch side transistors 2 and 3 are turned on, and the output QM of the master side latch becomes a low level.

Conversely, when the data D is at a low level, the Nch transistor 2 is turned off and the output becomes high impedance, but remains at the precharged high level for a certain period of time.

Note that the broken line portion in FIG. 2 is a portion where data is held by the capacity.

FIG. 4 is a block diagram of a dynamic shift register according to a second embodiment of the present invention.

This embodiment is an example of a 3-bit shift register. Pc
The h-transistor 1 has Pct as its gate input, and is connected to the clock-powered Nch transistor 3 at its drain, and its output becomes the next data input. The data input Nch transistor 2 receives the input data D as a gate input, and is connected to the NCh transistor 3 at the drain. These constitute the master side latch of the first stage flip-flop. Transistors 4, 5.6 constitute the latch of the slave example of the flip-flop, and correspond to transistors 1, 2.3 of the master side latch, respectively, and their operations are the same as in the first embodiment.

[Effects of the Invention] As explained above, the present invention reduces the number of transistors by reducing the number of transistors by using one transistor on the Pch side and precharging by the control signal, thereby reducing the area required for this circuit. effective.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a dynamic shift register according to a first embodiment of the present invention, FIG. 2 is a timing chart of the circuit of FIG. 1, and FIG. 3 is a diagram of a dynamic shift register according to a second embodiment of the present invention. FIG. 4 is a block diagram of a conventional dynamic shift register, and FIG. 5 is a block diagram of the conventional dynamic shift register shown in FIG. 4 expanded to the gate level. DESCRIPTION OF SYMBOLS 1... Pch transistor for master side precharging, 2... Master side data manual Nch} transistor, 3... Master side clock manual Nch transistor, 4... Pch transistor for slave side precharging, 5...・Slave side data manual Nch transistor, 6...Slave side clock manual Nch transistor.

Claims (1)

[Claims] In a dynamic shift register in which clocked inverters of the type using one- and two-phase clocks φ1 and φ2 are connected in series, the transistor on the P-channel side is formed of one transistor per stage, If the clock φ1 is input as a control signal to the N-channel side transistor, the signal that becomes low level during the period from when the clock φ2 becomes low level until the clock φ1 becomes high level is transmitted to the N-channel side transistor. A dynamic shift register in which a clock φ2 is input as a control signal uses a signal that is at a low level for a period from when a clock φ1 becomes a low level until a clock φ2 becomes a high level.