JPH0397054A - Fault detecting system for data transfer system - Google Patents

Abstract

PURPOSE:To specify a fault bus slave and to prevent abnormality from being continued when the fault occurs by providing function in the bus slave so as to detect the abnormality of the bus slave itself and displaying or notifying a fault detection output to the side of a bus master. CONSTITUTION:Bus slaves 31-33 are equipped with monitoring circuits 7 to obtain the fault detection outputs when the transfer completion signals of the bus slaves themselves are not generated within a fixed time with transfer requests and address selection form bus masters 21-23 as conditions. The fault bus slaves 31-33 are specified by the fault detection output and for confirming the abnormality when data are transfered, the function to detect the generation of the fault is provided not only on the side of the bus masters 21-23 but also on the side of the bus slaves 31-33. Thus, the bus slave generating the fault can be specified and the abnormality can be prevented from being continued.

Description

[Detailed Description of the Invention] A. INDUSTRIAL APPLICATION FIELD The present invention relates to a failure detection method for a data transfer system using a plurality of bus masters and bus slaves.

B. Summary of the Invention The present invention provides a data transfer system that transfers data using a data transfer request and a transfer completion signal, in which each bus slave detects its own failure by monitoring the time from the transfer request to the output of the transfer completion signal. This makes it possible to identify the bus slave in which a failure has occurred.

C. Prior Art In a system in which data is transferred between a bus master and a bus slave connected to a bus, a transfer request and a transfer completion signal are used for data transfer.

FIG. 2 shows a time chart of data transfer.

When a bus master requests a data transfer from a bus slave, the bus master outputs a transfer request signal along with an address signal to the bus. In response to this request, the bus slave sends a data signal and a transfer completion signal to the bus. Similarly, when transferring data from a bus master to a bus slave, the bus master outputs a data signal together with an address signal, and then outputs a write signal. After the bus slave side takes in the data, it outputs a transfer completion signal.

Therefore, upon receiving the data transfer completion signal, the bus master side confirms and completes the data transfer.

D. Problems to be Solved by the Invention When the conventional data transfer method is applied to a system in which multiple bus masters and bus slaves are connected via a bus, if a transfer completion signal is not returned due to a failure of the bus slave, the bus master waits for the signal. A transfer error occurs from the initial state, and all other bus masters that subsequently accessed the bus also become transfer errors, and the error continues without being able to identify the failed bus slave.

An object of the present invention is to provide a failure detection method that can identify a failed bus slave in a data transfer system in which a plurality of bus masters and bus slaves are bus-coupled.

E. Means and Effects for Solving the Problems In order to achieve the above object, the present invention provides a bus master system in which a plurality of bus masters and bus slaves are connected to each other via a bus. In a data transfer system in which data is transferred between a bus master and a bus slave using a data transfer request and a transfer completion signal, the bus slave generates its own transfer completion signal within a certain period of time based on the transfer request and address selection from the bus master. It is equipped with a monitoring circuit that obtains a failure detection output when the failure detection output is not performed, and the failure detection output is used to identify a failed bus slave, so that abnormalities during data transfer can be confirmed not only on the bus master side but also on the bus slave side. Provide a function to detect.

F. Embodiment FIG. 1 is an apparatus configuration diagram showing an embodiment of the present invention. Bus ■This is the three bus masters 2. ,2. , 23, three bus slaves 3*3t, 33, and a memory 4, etc., are combined in a system configuration.

Bus master 2. 23 perform data transfer processing with the bus slaves 31 to 33 in the same manner as before. Bus slave 3. ~
3, as shown in the bus slave 3, an address decoding circuit 5 and a transfer completion signal control circuit 6.
and a transfer completion signal monitoring circuit 7.

The address decoding circuit 5 detects an address signal possessed by each bus slave from the address bus, and outputs an access to its own bus slave as an address selection signal. The control circuit 6 receives an address selection signal from the address decoding circuit 5, receives a transfer request signal on the bus, controls data transfer, and outputs a transfer completion signal onto the bus. The monitoring circuit 7 receives the address selection signal from the address decoding circuit 5 and the transfer request from the bus, and checks whether the control circuit 6 has issued a transfer completion signal within a certain period of time from the address selection and data transfer request of the self-bus slave. Monitoring is performed, and when the transfer completion signal is not issued within a certain period of time, a failure detection output indicating transfer failure is obtained.

The above-mentioned failure detection by the monitoring circuit 7 is performed, for example, at the timing t of a transfer request from a certain bus master in the transfer procedure shown in FIG. A period T from 1 to a timing t1 at which the address signal becomes inactive on the condition of address selection is determined, and when the transfer completion signal does not become valid within the period T, a failure detection output is obtained. This failure detection output is used by the bus slave to display it as its own failure and to transfer it to all bus masters at once to identify the failed bus slave and to perform processing such as disconnecting the bus slave from the bus.

Therefore, in a system in which multiple bus masters and bus slaves are bus-coupled, if a bus slave fails and does not return a transfer completion signal to the bus master, the failed bus slave can be immediately identified by the failure detection output from the monitoring circuit 7. It is possible to immediately respond to subsequent transfer requests from other bus masters. Furthermore, since failure detection is achieved without intervening software, it is easy to identify a bus slave when a failure occurs.

G. Effects of the Invention As described above, according to the present invention, a bus slave has a function to detect its own abnormality, and by displaying the failure detection output and reporting it to the bus master side, a failed bus slave can be identified, and a failure can be detected. This has the effect of making it possible to immediately transfer data between other bus masters and bus slaves without continuing to experience abnormalities.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an apparatus showing an embodiment of the present invention, and FIG. 2 is a time chart of data transfer. ■・・・Bus, 2,. 2,,2. ...Bassmaster, 3
1, 3,, 3,... bus slave, 5... address recorder circuit, 6... transfer completion signal control circuit, 7... transfer completion signal monitoring circuit. FIG. 1 Embodiment configuration diagram 1...Bus 21, 22.23...Bus master 31.32.33...Pass slave 5...Address decoder circuit 6...Transfer completion signal control circuit 7 ...Transfer completion signal monitoring circuit

Claims (1)

[Claims] (1) In a data transfer system in which multiple bus masters and bus slaves are bus-coupled and data transfer is performed between the bus master and bus slave using a data transfer request and a transfer completion signal, the bus slave receives the transfer request and address from the bus master. A data transfer system comprising a monitoring circuit that obtains a failure detection output when its own transfer completion signal is not generated within a certain period of time based on a selection condition, and identifying a failed bus slave based on the failure detection output. fault detection method.