JPH0395999A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0395999A JPH0395999A JP1230276A JP23027689A JPH0395999A JP H0395999 A JPH0395999 A JP H0395999A JP 1230276 A JP1230276 A JP 1230276A JP 23027689 A JP23027689 A JP 23027689A JP H0395999 A JPH0395999 A JP H0395999A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- tape carrier
- insulator
- conductor
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000004020 conductor Substances 0.000 claims abstract description 29
- 239000012212 insulator Substances 0.000 claims abstract description 21
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 239000011347 resin Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000001035 drying Methods 0.000 claims abstract description 3
- 239000011888 foil Substances 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 238000007747 plating Methods 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001342 Bakelite® Polymers 0.000 description 1
- 229920013683 Celanese Polymers 0.000 description 1
- 229920002160 Celluloid Polymers 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004637 bakelite Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、テープキャリアに半導体チップを搭載した、
テープキャリア方式の半導体装置に関するものである,
〔従来の技術〕
近年、ディスプレイ、電子計算機など半導体を用いるデ
バイスにおいて、小型・薄型・高密度化のため、テープ
キャリア方式が有望視されている.しかしながら、従来
のテープキャリアは、デバイス孔内へ突き出したインナ
ーリードを形或する必要があったため工程が複雑で、不
安定なリードが変形するため歩留まりが悪く、このため
極めてコストも高いという欠点があった.
このような問題を解消するため、本発明者らは先に、デ
バイス孔へ突き出すリードを形戒させることなく半導体
チップを実装する方法の発明をなし開示した.第1図に
示すように、まず絶縁体(1)と導電体(2)よりなる
フレキシブル基板上に形成された導電体パターンに、バ
ンブ(6)を上面に形成した半導体チップ(5)をフェ
イスダウンで位置合わせをする.その後、絶縁体側から
ボンディングツール(7)を当接させ、絶縁体(1)を
介して導電体パターンのインナーリード(3)の先端と
半導体チップ上のバンプ(6)を加熱加圧することによ
り、半導体チップ(5)を実装しテープキャリア方式の
半導体装置が完成する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a tape carrier with a semiconductor chip mounted thereon.
Concerning tape carrier type semiconductor devices. [Prior art] In recent years, tape carrier type devices have been seen as promising for devices using semiconductors such as displays and electronic computers due to their miniaturization, thinness, and high density. However, conventional tape carriers have the drawbacks of complicated manufacturing processes as it is necessary to form inner leads that protrude into device holes, poor yields due to unstable lead deformation, and extremely high costs. there were. In order to solve these problems, the present inventors have previously invented and disclosed a method for mounting a semiconductor chip without restricting the leads that protrude into the device hole. As shown in Figure 1, first, a semiconductor chip (5) with bumps (6) formed on the top surface is attached to a conductor pattern formed on a flexible substrate consisting of an insulator (1) and a conductor (2). Align the position down. Thereafter, the bonding tool (7) is brought into contact with the insulator from the side of the insulator, and the tips of the inner leads (3) of the conductor pattern and the bumps (6) on the semiconductor chip are heated and pressurized through the insulator (1). A semiconductor chip (5) is mounted and a tape carrier type semiconductor device is completed.
この方法では、デバイス孔を形成する必要がないため、
工程が少なくて済み、しかもデバイス孔へ突き出してい
る導電体のリードが変形する不良発生がないため、歩留
まりが高く、低コストになり、さらに接続部の信頼性が
高いという特徴があった・
ところが、このテープキャリアを構戒する絶縁体は、高
い耐熱性を持つ色の濃いポリイミド樹脂を用いることが
多く、この絶縁体を通して半導体チップと導電体パター
ンの位置合わせを精度よく行うことは、半導体チップと
導電体パターンの接続部が見えにくいため極めて難しく
、位置ずれが生じるという欠点があった.
〔発明が解決しようとする課題〕
本発明は、従来技術のこのような欠点に鑑みて種々の検
討の結果なされたものであり、その目的とするところは
、歩留まりが高く、かつ信頼性の高いテープキャリア方
式の半導体装置を提供することにある。With this method, there is no need to form device holes;
However, since it requires fewer steps and does not cause defects such as deformation of the conductor leads protruding into the device hole, the yield is high, the cost is low, and the reliability of the connection part is high. The insulator that makes up this tape carrier is often made of a dark polyimide resin with high heat resistance. Accurately aligning the semiconductor chip and the conductor pattern through this insulator is essential for the semiconductor chip. This is extremely difficult because it is difficult to see the connection between the conductor pattern and the conductor pattern, which has the disadvantage of causing misalignment. [Problems to be Solved by the Invention] The present invention has been made as a result of various studies in view of these drawbacks of the prior art, and its purpose is to provide a high-yield and highly reliable An object of the present invention is to provide a tape carrier type semiconductor device.
すなわち本発明は、可とう性のある絶縁体と導電体より
なるフレキシブル基板上に形成された導電体パターンに
、半導体チップをフェイスダウンで位置合わせをし、前
記絶縁体側からボンディングツールを当接させ、絶縁体
を介して、導電体パターンのインナーリードの先端と半
導体チップの接続部とを加熱加圧することにより、半導
体チップを搭載したテープキャリア方式の半導体装置に
おいて、前記テープキャリアが、透明な絶縁性フィルム
の表面に物理的もしくは化学的方法により金属薄膜層を
形或し、まテープキャリアが、透明な絶縁性樹脂を塗布
、乾燥して得られた2層構造の積層体を用いて導電体回
路パターンを形戒したものであることを特徴とするテー
プキャリア方式の半導体装置に関するものである.
以下、図面により本発明を詳細に説明する.第1図は、
本発明による半導体装置の製造方法を示す要部断面図で
ある.透明な絶縁体(1)と導電体(2)よりなるフレ
キシブル基板上に、フォトエッチングなどの方法により
形成された導電体バクーンの表面にメッキ(4)を施し
たテープキャリアを用意する.このテープキャリアの導
電体パターンを下側にして、上面側にバンブ(6)を形
或した半導体チップ(5)の上に載置し、チップ上のバ
ンブ(6)と導電体パターンのインナーリード(3)の
先端との位置を合わせる.続いて、絶縁体(1)側から
ボンディングツール(7)を当て、加熱加圧して導電体
パターンに半導体チップ(5)を接続する.
このように、テープキャリアに透明な絶縁体を用いるこ
とにより、絶縁体を通して半導体チップと導電体パター
ンが見えるため位置合わせが容易になり、極めて精度よ
く、半導体チップ(5)を実装することが可能となる.
また、半導体チップやテープキャリアに位置合わせのた
めの印を設ければより効果的である.
本発明において使用する透明な絶縁体(1)としては、
これを介して加熱加圧するため、高い耐熱性を持つフィ
ルム・樹脂が望ましく、例えば、スミレジンエクセルC
RC−6 0 6 2 (住友べ一クライト社製L S
IXEF−33・44(ヘキストセラニーズ社製)、セ
藁コファインSP−910(東レ社製)、パイラリンP
I−2566(デュポン社製)、PIX−1200 (
日東電工社製)、サンエバー100(日産化学社製)な
どが使用可能で、かつできるだけ薄いほうが好ましい。That is, the present invention aligns a semiconductor chip face-down to a conductor pattern formed on a flexible substrate made of a flexible insulator and a conductor, and abuts a bonding tool from the insulator side. In a tape carrier type semiconductor device equipped with a semiconductor chip, the tape carrier is made of transparent insulator by heating and pressurizing the tip of the inner lead of the conductor pattern and the connection part of the semiconductor chip through an insulator. A thin metal film layer is formed on the surface of the conductive film by physical or chemical methods, and the tape carrier is a conductive material using a two-layered laminate obtained by coating and drying a transparent insulating resin. This article relates to a tape carrier type semiconductor device characterized by a circuit pattern that is well-defined. The present invention will be explained in detail below with reference to the drawings. Figure 1 shows
1 is a cross-sectional view of a main part showing a method for manufacturing a semiconductor device according to the present invention. A tape carrier is prepared on a flexible substrate consisting of a transparent insulator (1) and a conductor (2), with the surface of a conductor bag formed by a method such as photo-etching and plated (4). With the conductor pattern of this tape carrier facing down, place it on top of the semiconductor chip (5) with bumps (6) formed on the top side, and connect the bumps (6) on the chip and the inner leads of the conductor pattern. Align the position with the tip of (3). Next, a bonding tool (7) is applied from the insulator (1) side, and the semiconductor chip (5) is connected to the conductive pattern by applying heat and pressure. In this way, by using a transparent insulator for the tape carrier, the semiconductor chip and conductor pattern can be seen through the insulator, making alignment easier and making it possible to mount the semiconductor chip (5) with extremely high precision. becomes.
It would also be more effective to provide alignment marks on the semiconductor chip or tape carrier. The transparent insulator (1) used in the present invention includes:
Because heat and pressure are applied through this, it is desirable to use a film or resin with high heat resistance, such as Sumiresin Excel C.
RC-6 0 6 2 (LS manufactured by Sumitomo Beikkulite Co., Ltd.)
IXEF-33/44 (manufactured by Hoechst Celanese), Sewarako Fine SP-910 (manufactured by Toray Industries), Pyralin P
I-2566 (manufactured by DuPont), PIX-1200 (
(manufactured by Nitto Denko Corporation), Sunever 100 (manufactured by Nissan Chemical Co., Ltd.), etc. can be used, and it is preferable that it be as thin as possible.
本発明に用いる導電体(2)は、通常フレキシブル基板
に用いられているものであれば、銅、アルミニウムなど
特に制限はない。また、導電体パターンの表面上に施し
てあるメッキ(4)は、その材質を特に限定するもので
はないが、半導体チップ上のバンブ(6)の材質にあわ
せ、金、錫、はんだなどが好ましい。The conductor (2) used in the present invention is not particularly limited as long as it is normally used in flexible substrates, such as copper or aluminum. Furthermore, the material of the plating (4) applied on the surface of the conductor pattern is not particularly limited, but gold, tin, solder, etc. are preferable depending on the material of the bumps (6) on the semiconductor chip. .
本発明で使用するボンディングツール(7)は、通常半
導体の搭載用に用いられているものであれば特に限定す
るものではないが、500’C,2秒、2 0 0 g
/リード荷重以上の加熱加圧ができ、半導体チップとの
平行度が5μm以下のものであれば、より良好な効果が
得られる。The bonding tool (7) used in the present invention is not particularly limited as long as it is one that is normally used for mounting semiconductors.
A better effect can be obtained if heat and pressure can be applied to a lead load or higher and the parallelism with the semiconductor chip is 5 μm or less.
このように、本発明では、デバイス孔を必要としない、
新しいフィルムキャリア方式の半導体装置の、半導体チ
ップと導電体パターンの位置合わせの難しさという欠点
を排除することができ、高い歩留まりで高信頼製のフィ
ルムキャリア方式の半導体装置が得られる.
以下、本発明の実施例を示す。Thus, the present invention does not require a device hole.
It is possible to eliminate the drawback of new film carrier type semiconductor devices, such as difficulty in aligning the semiconductor chip and conductor pattern, and to obtain highly reliable film carrier type semiconductor devices with high yield. Examples of the present invention will be shown below.
厚さ35μmの電解w4fiに、透明な樹脂ス逅レジン
エクセルCRC−6062 (.住友ベークライト製、
透過率:70%at500nm、20%at400nm
,厚さ50μmの時)を塗布・乾燥して厚さ50μmの
絶縁層を形成し、2層構造の積層体を得た.これを幅3
5III+1のテープ状にスリットし、銅箔面をエッチ
ング加工することにより回路パターンを形成し、表面に
ニッケル5.0μmを下地にして金0.5μmのメッキ
を施してテープキャリアを得た.
次に、半導体チップ上に形成された接続用金バンブとテ
ープキャリアの回路パターンのインナーリードの先端と
を、絶縁樹脂層を通して表面から位置合わせし、絶縁樹
脂層を介して、ボンディングツールを用いて、430゜
C,1秒、1 0 0 g/リード荷重のボンディング
条件で加熱加圧して接合し、半導体チップの搭載を行っ
た。Transparent resin was applied to the electrolytic W4FI with a thickness of 35 μm.Resin Excel CRC-6062 (manufactured by Sumitomo Bakelite,
Transmittance: 70% at 500 nm, 20% at 400 nm
, when the thickness was 50 μm) was coated and dried to form an insulating layer with a thickness of 50 μm to obtain a laminate with a two-layer structure. Width 3
A 5III+1 tape was slit, a circuit pattern was formed by etching the copper foil surface, and the surface was plated with 0.5 μm of gold on a nickel base of 5.0 μm to obtain a tape carrier. Next, the connection gold bumps formed on the semiconductor chip and the tips of the inner leads of the circuit pattern of the tape carrier are aligned from the surface through the insulating resin layer, and a bonding tool is used to bond them through the insulating resin layer. , 430° C., 1 second, and 100 g/lead load.
得られた半導体装置について、インナーリードと半導体
チップ上のバンブとの位置ずれを検査したところ、最大
8μm程度であり、隣接電極との短絡等の不良は無かっ
た。When the obtained semiconductor device was inspected for misalignment between the inner leads and the bumps on the semiconductor chip, the misalignment between the inner leads and the bumps on the semiconductor chip was found to be about 8 μm at most, and there were no defects such as short circuits with adjacent electrodes.
このように、本発明に従うと、デバイス孔のないテープ
キャリア方式の半導体装置の従来の欠点である、半導体
チップとインナーリードの先端の位置合わせが難しいと
いう欠点を克服することができ、極めて簡単な位置合わ
せて半導体チップを実装することができ、その結果、高
い歩留まりでかつ信頼性の高い半導体装置を得ることが
可能となる。As described above, according to the present invention, it is possible to overcome the drawback of the conventional tape carrier type semiconductor device without device holes, which is that it is difficult to align the semiconductor chip and the tip of the inner lead. Semiconductor chips can be mounted with alignment, and as a result, it is possible to obtain a semiconductor device with high yield and high reliability.
第1図は、本発明による半導体装置の製造方法を示す要
部断面図である.
第l図FIG. 1 is a sectional view of a main part showing a method for manufacturing a semiconductor device according to the present invention. Figure l
Claims (1)
ブル基板上に形成された導電体パターンに、半導体チッ
プをフェイスダウンで位置合わせをし、前記絶縁体側か
らボンディングツールを当接させ、絶縁体を介して、導
電体パターンのインナーリードの先端と半導体チップの
接続部とを加熱加圧することにより、半導体チップを搭
載したテープキャリア方式の半導体装置において、前記
テープキャリアが、透明な絶縁性フィルムの表面に物理
的もしくは化学的方法により金属薄膜層を形成し、また
は、金属箔上に透明な絶縁性樹脂を塗布、乾燥して得ら
れた2層構造の積層体を用いて導電体回路パターンを形
成したものであることを特徴とするテープキャリア方式
の半導体装置。(1) Align the semiconductor chip face-down to a conductor pattern formed on a flexible substrate made of a flexible insulator and conductor, and contact the bonding tool from the insulator side to insulate the In a tape carrier-type semiconductor device with a semiconductor chip mounted thereon, the tape carrier is made of a transparent insulating film by heating and pressurizing the tip of the inner lead of the conductor pattern and the connection part of the semiconductor chip through the body. A conductive circuit pattern is created by forming a metal thin film layer on the surface of the metal foil by a physical or chemical method, or by applying a transparent insulating resin on the metal foil and drying it. A tape carrier type semiconductor device, characterized in that it is formed of a tape carrier type semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1230276A JPH0395999A (en) | 1989-09-08 | 1989-09-08 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1230276A JPH0395999A (en) | 1989-09-08 | 1989-09-08 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0395999A true JPH0395999A (en) | 1991-04-22 |
Family
ID=16905265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1230276A Pending JPH0395999A (en) | 1989-09-08 | 1989-09-08 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0395999A (en) |
-
1989
- 1989-09-08 JP JP1230276A patent/JPH0395999A/en active Pending
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