JPH0395772A - Phase synchronizing circuit for disk device - Google Patents

Abstract

PURPOSE:To output the pulse of a frequency, which is N-fold to that of a synchronizing pulse, without erroneous detection from a voltage controlled oscillator (VCO) by keeping a reference signal at a zero level until the revolution a motor to rotate a servo disk reaches a prescribed revolution. CONSTITUTION:This device is provided with a synchronizing pulse generating circuit 1, phase comparator 2, VCO 5 and switch circuits 7 and 8. Since the switch circuits 7 and 8 keep the reference signal at the zero level until the revolution of the motor to rotate the servo disk reaches the prescribed revolution, phase difference between the reference signal and a synchronizing pulse to be compared in the phase comparator 2 obtains a polarity to lower the transmitting frequency of the VCO 5 for the pulse width of the synchronizing pulse. Thus, phase comparison in the phase comparator 2 is started from the low oscillation frequency of the VCO 5, and without the erroneous detection, the pulse of the N-fold frequency to that of the synchronizing pulse can be outputted form the VCO 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a phase synchronization circuit applied to a disk device.

[Conventional technology]

Disk devices generally include magnetic disk devices and optical disk devices, of which magnetic disk devices write and read data to and from data disks based on positional information obtained from servo disks. The timing of reading and writing is controlled by a clock pulse, and the clock pulse is used by changing the frequency of the synchronization pulse transmitted from the servo disk.

An example of a circuit for converting the frequency of the above-mentioned fine synchronization pulse into a different frequency is a fine phase synchronization circuit shown in FIG. In Figure 4, (l) is the servo disk (
(2) is a phase comparator that compares the phase of the synchronization pulse with a reference signal, and is compared with a synchronous flip-flop (3). It consists of a circuit (4). (5) is a voltage controlled oscillator (hereinafter referred to as V
(3 0.!: [f le), (6) Pako's VOO (
5) A frequency divider that divides the frequency of the output pulse to 1/N and outputs the reference signal.

Next, the operation of this device will be explained. @ In Figures 4 and 5, when the power to the magnetic disk device is turned on, V 0
0 (51 starts self-oscillation and the frequency divider (6) outputs a reset pulse as a reference signal. When the servo disk starts rotating, a servo signal is generated and synchronized by the synchronization pulse generation group (1) A pulse is generated.In the synchronous flip-flop (3), an output pulse that rises by the synchronous pulse and falls by the reset pulse is obtained, and this output pulse and the synchronous pulse are connected to the comparator circuit (4).
), each pulse is integrated by a certain number of pulses and converted into direct current, and the difference is taken by a differential amplifier (not shown) and output as the output of the phase comparator (2). In the case of Figure 5, the frequency of the reset pulse is lower than the frequency of the synchronization pulse, so the negative part of the flip-flop output is greater than the positive part of the synchronization pulse (the shaded area). The output of the phase comparator (2) has a negative polarity and works to increase the output frequency of the V O O (5), and the falling edge of the reset pulse moves the signal in the E direction. As stated above, the synchronization pulse and reset pulse are in the same phase! The oscillation frequency of V O O (5) changes. When the phase becomes the same, a pulse whose frequency is N times synchronized with the synchronization pulse is obtained at the output of V O O (5).

[Problems that the invention helps solve]

Since the phase synchronization circuit of a conventional disk device is constructed as described above, when the power is turned on, the rotation speed of the motor that rotates the servo disk is low, so the frequency of the synchronization pulse is lower than the frequency of the reset pulse. Therefore, the phase comparison when the phase comparator (2) is pressed is performed starting from the one with the higher oscillation frequency of V O O (5), and as shown in FIG. 6, at a certain timing. It is possible that the integral values of a certain number of synchronization pulses and flip-flop output pulses match, resulting in false detection and a pulse with a frequency N times that of the synchronization pulse not being returned to the output of v00(5). there were.

This invention was made to solve the above-mentioned problems, and the phase comparison sent to the dual-phase comparator is performed from the lower oscillation frequency of the VCO, so that the oscillation frequency is N times higher than the synchronizing pulse without false detection. The object of the present invention is to obtain a phase synchronization circuit for a disk device that outputs pulses of a frequency of from a VCO.

[Means to solve the problem]

The phase synchronization circuit of the disk device according to the present invention includes a synchronization pulse generation circuit that generates a synchronization pulse from a servo signal detected based on a servo disk rotated by a motor κ, and a phase synchronization circuit between the synchronization pulse and a reference signal. a phase comparator that outputs a signal based on the phase difference, a voltage controlled oscillator that outputs a converted pulse of a frequency corresponding to the output signal of this phase comparator, and a pulse that divides the frequency of the f-converted pulse. When the output frequency divider and the rotational wave of the motor reach a predetermined rotation speed that generates a synchronizing pulse with a frequency e higher than the output pulse frequency of the frequency divider after the power is turned on, the reference signal is set to zero level. and a switching circuit that supplies the output of the frequency divider as the standardization signal after the rotational speed of the motor reaches the predetermined rotational speed.

[Effect]

The switching circuit for this invention is as follows. The reference signal is kept at the zero level until the rotation speed of the motor that rotates the servo disk reaches the specified rotation speed. The phase difference between the reference signal and the synchronization pulse compared by the phase comparator is equal to the pulse width of the synchronization pulse and has a polarity that lowers the oscillation frequency of the voltage control oscillator. The oscillation frequency continues to decrease and after reaching the lowest oscillation frequency, that frequency is maintained.

[Embodiments of the invention]

An embodiment of a phase synchronization circuit for a disk drive according to the present invention will be described below with reference to FIGS. 1 to 3. In Figure 1. (l) is a synchronous pulse generating circuit (2) which generates a synchronous pulse from a servo signal obtained from a servo disk (not shown); a phase comparator which compares the phase of the synchronous pulse with a reference signal; A synchronous flip-flop (3) outputs a pulse that rises at the rising edge of the pulse and falls at the falling edge of the reference signal, and the output pulse of this synchronous flip-flop (3) and the Doi synchronous pulse are each kept constant. Several integrals and synchronous 7 rig flops (
It consists of a comparator circuit (4) in which a signal obtained by integrating the output pulses of step 3) is inputted to the negative side of the differential amplifier, and a signal obtained by integrating the synchronizing pulses is inputted to the positive side of the operational amplifier. (5)
outputs a pulse with a frequency corresponding to the output voltage of this phase comparator (2).
troll-ed Oscillator), t
el is a frequency divider that divides the frequency of the pulse outputted by 51 into 17N and outputs it, and (7) is a sensor (not shown) that detects the rotation speed of the motor that rotates the servo disk. When the output signal from the frequency divider (6) is input and the rotation speed of the motor reaches a predetermined rotation speed that generates a synchronizing pulse with a frequency higher than the output pulse frequency of the frequency divider (6), the output is maintained at a low level, which is considered as a zero level. , a microprocessor that outputs a high-level signal after the rotational speed of the motor reaches the predetermined rotational speed, and (8) is a microprocessor that outputs a high-level signal after the rotational speed of the motor reaches the predetermined rotational speed. This is an AND gate that takes an output signal as an input signal, and the output signal of this AND gate (8) is supplied as the reference signal.

AND case} (81.1!: Microprocessor (
7) constitute a switching circuit.

Next, Figures 1 and 2 explain the operation of this item.
As shown in the figure, when the power is turned on, the motor that rotates the servo disk starts, and at the same time, the cyclic pulse generation circuit (
A synchronizing pulse is output from 1). As the rotation speed of the motor increases, the frequency of the synchronous pulse also increases.
The H wave number of the synchronization pulse is V C! 0 (B when the frequency at point A sufficiently exceeds the lowest oscillation frequency unique to 51)
The microprocessor (
Detected with 7). Microprocessor v (7) The fiAND gate (8) is opened by the high-level signal output from the microprocessor (7), and the reset state of the phase synchronization circuit (2) is released. Thereafter, the rotational speed of the motor continues to increase, and when it reaches a preset rotational speed, it is controlled to maintain that rotational speed, and the frequency of the synchronizing pulse also becomes constant. The operation of the phase synchronized circuit (2) described above will be explained based on the waveforms of each part shown in FIG. When the power is turned on, a synchronization pulse is output from the b phase synchronization circuit (2). On the other hand, V C
O (51 starts self-transmission and this V C O (51
The output pulse is divided into 1/N frequency by the frequency divider (6), but since the rotation speed of the motor has not reached the predetermined rotation speed, it is cut by the AND gate (8), and the reset pulse is Continue to maintain the low level state. In this state, the output of the synchronous flip-flop (3) also becomes low level. In the operational amplifier in the comparator circuit (4) of the phase comparator (2), the minus side goes to low level and the integrated value of the synchronizing pulse is input to the plus side, so as a result, the integrated value of the synchronizing pulse becomes the same. It is output. Since this output voltage has a positive polarity, it acts on vCO(5) rather than lowering its oscillation frequency. V■ (5) drops to its own minimum oscillation frequency 1 and then continues to oscillate at that minimum oscillation frequency. Thereafter, when the rotational speed of the motor reaches a predetermined rotational speed (arrow C point in Fig. 3). The output pulse of the frequency divider (6) with the AND gate (8} open is input to the phase comparator (2) as a reset pulse.The pulse output from the synchronous flip-flop (3) and the synchronous pulse When the respective integral values are compared in the comparison circuit (4).
Since the pulse width of the synchronization pulse is shorter, a phase comparator (2
) becomes negative, increasing the oscillation frequency of VOO(5). Along with this, the frequency of the reset pulse increases, the fall of the reset Hals progresses in the direction of arrow D in Figure 3, and the pulse width of the synchronous pulse matches the pulse width of the output pulse of the synchronous flip-flop (3). At this point, the output voltage of the phase comparator (2) becomes zero. The phases become synchronized. In this state, a conversion pulse synchronized with the synchronization pulse and converted to a frequency N times that of the synchronization pulse is obtained at the output of V O O (51).

〔Effect of the invention〕

From the above, the phase synchronization circuit of the disk device according to the present invention is designed to maintain the reference signal at zero level when the rotational speed of the motor that rotates the servo disk reaches a predetermined rotational speed. , the phase comparator is operated from the lower oscillation frequency of the vCO, and there is an effect that a phase synchronization circuit for a disk device can be obtained which outputs a pulse with a frequency N times the frequency of the synchronization pulse from the vCO without erroneous detection.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a phase synchronization circuit of a disk device according to an embodiment of the present invention, Fig. 2 is a graph showing the relationship between the synchronization pulse frequency and the rotational speed of the motor, and Fig. 3 is the phase synchronization circuit. Figure 4 is a block diagram showing the phase synchronization circuit of a conventional disk drive, and Figure 5 is a time chart showing the relationship of waveforms applied to each part of the phase synchronization circuit. FIG. 6 is a time chart showing the relationship of waveforms at various parts of the phase comparator when the phase comparator makes an erroneous detection. In the figure, (1) is the synchronous pulse generation circuit. (2) is a phase comparator. (3) is a synchronous flip-flop, (4) is a comparison circuit, (5) is a voltage controlled oscillator (voltage controlled oscillator), (
61 u frequency divider, (7) → microprocessor. (8)
is an AND gate ((7) and (8) form a switching circuit). In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A synchronous pulse generation circuit that generates a synchronous pulse from a servo signal detected based on a servo disk rotated by a motor; a phase comparator that compares the phase of the synchronous pulse with a reference signal and outputs a signal based on the phase difference; A voltage control oscillator that outputs a converted pulse with a frequency corresponding to the output signal of the phase comparator, a frequency divider that outputs a pulse obtained by dividing the frequency of the converted pulse, and a frequency divider that outputs a pulse whose frequency corresponds to the output signal of the phase comparator. The reference signal is kept at zero level until the rotational speed of the motor reaches a predetermined rotational speed that generates a synchronizing pulse with a frequency higher than the output pulse frequency of the motor.After the rotational speed of the motor reaches the predetermined rotational speed, the output of the frequency divider is A phase synchronization circuit for a disk device, comprising a switching circuit that supplies the reference signal as described above.