JPH039526A - Forming method of protruded electrode of semiconductor device - Google Patents
Forming method of protruded electrode of semiconductor deviceInfo
- Publication number
- JPH039526A JPH039526A JP1150700A JP15070089A JPH039526A JP H039526 A JPH039526 A JP H039526A JP 1150700 A JP1150700 A JP 1150700A JP 15070089 A JP15070089 A JP 15070089A JP H039526 A JPH039526 A JP H039526A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- synthetic resin
- cathode
- electroplating
- barrier metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000009713 electroplating Methods 0.000 claims abstract description 12
- 238000004544 sputter deposition Methods 0.000 claims abstract description 10
- 229920003002 synthetic resin Polymers 0.000 claims abstract description 10
- 239000000057 synthetic resin Substances 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 abstract description 14
- 229910052751 metal Inorganic materials 0.000 abstract description 14
- 239000002184 metal Substances 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 235000013861 fat-free Nutrition 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Physical Vapour Deposition (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、たとえばワイヤレスボンディングで使用され
る半導体装置の突起電極を形成するための方法に関する
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming protruding electrodes of semiconductor devices used, for example, in wireless bonding.
従来の技術
近年、半導体装置のｖ＆細化に伴い、ＬＳＩ（大規模半
導体＆積回路）接続端子数は、多端子化の傾向がある。2. Description of the Related Art In recent years, as semiconductor devices have become smaller and smaller, there has been a tendency for the number of LSI (Large-Scale Semiconductor & Integrated Circuit) connection terminals to increase.
そのため従来のワイヤボンディングによる端子接続方式
では対処しきれなくなってきており、新たにタブ＜ Ｔ
’ Ａ Ｂ ）方式やフリンブチップ（ＦＣ）方式等の
ワイヤレスボンディングが脚光を浴びている。このワイ
ヤレスボンディング方式における重要な要素技術の１つ
にＩＣチップ電極上へのバンプと呼ばれる突起電極の形
成技術があり、通常、タブ法ではＡ Ｌｌを、ＦＣ法で
は半田が、突起電極材料として用いられている。For this reason, the conventional terminal connection method using wire bonding is no longer able to cope with this problem, and a new tab < T
Wireless bonding methods such as 'A B ) method and the frimbu chip (FC) method are in the spotlight. One of the important elemental technologies in this wireless bonding method is the formation of protruding electrodes called bumps on IC chip electrodes. Usually, A Ll is used as the protruding electrode material in the tab method, and solder is used in the FC method. It is being
、突起電極形成方法としては、電解めっき法が主流とな
っており、そのプロセスの従来からの一例として第３
Ｕｌ （ａ ）〜第３１２ｆｆ（ｆ＞で示すような工程
を有する方法がある。第３図（ａ）では、所定の位置に
ＡＩ等の電極バッド２およびその他の領域にＳｉＮ等の
絶縁層８が形成された半導木基［１を準備する。その基
板１上へ蒸着やスパフタリングなどによってＴ ｉ Ｗ
−Ａ ｕの２層の薄膜をバリアメタル５として被着し
、第３１１Ｚ（ｂ）の構造を得る。, electrolytic plating is the mainstream method for forming protruding electrodes, and the third method is an example of the conventional process.
There is a method having steps as shown by U1(a) to 312ff(f>). In FIG. 3(a), electrode pads 2 such as AI are formed at predetermined positions and insulating layers 8 such as SiN are formed in other areas. A semiconductor wood substrate [1 on which T i W is formed is prepared.T i W
-A two-layer thin film of Au is deposited as the barrier metal 5 to obtain the structure of No. 311Z(b).
次にその表面へ突起電極、すなわちバンプが形成される
べき領域が開口されるように、ホトレジスト膜６を形成
し、第３図（Ｃ）の構造とする。Next, a photoresist film 6 is formed on the surface of the photoresist film 6 so that a region where a protruding electrode, that is, a bump is to be formed, is opened, resulting in the structure shown in FIG. 3(C).
さらにバリアメタル５を陰極として電解めっきを行い、
レジスト開口部へＡｕから成る層７を堆積し、第３図（
ｄ）の構造を得る。その後、ホトレジスト膜６を剥離し
て、第３１ｆｆｉ（ｅ）で示される構造とし、最後にバ
リアメタル５をエツチングして第３図（ｆ＞の構造を得
る。Furthermore, electrolytic plating is performed using barrier metal 5 as a cathode,
A layer 7 made of Au is deposited in the resist opening, as shown in FIG.
Obtain the structure of d). Thereafter, the photoresist film 6 is peeled off to obtain the structure shown in FIG. 31ffi(e), and finally the barrier metal 5 is etched to obtain the structure shown in FIG. 3(f>).
発明が解決すべき課題
しかしながら、このような方法で突起電極を形成した１
９Ｊキ、バリアメタル５のエツチング工程において、突
起電極の傘下部のエツチングを均一に行うことが困難で
あるため、オーバエツチングによって、第４図に示すご
とくバリアメタル５は突起電極の根元までエツチングさ
れてしまい、場外によっては電極バッド２にまでエツチ
ング液が侵入するおそれがある。したがって、この先行
技術では、良好なバリアメタルのエツチングを行うのは
非常に・困難であり、チップの歩留り低下、信頼性の低
下を引き起こす危険性が大きかった。Problems to be Solved by the Invention However, there is no problem with forming protruding electrodes using this method.
In the etching process of the barrier metal 5, it is difficult to uniformly etch the lower part of the protruding electrode, so due to over-etching, the barrier metal 5 is etched to the base of the protruding electrode as shown in FIG. Depending on the location, the etching solution may even enter the electrode pad 2. Therefore, with this prior art, it is very difficult to perform good barrier metal etching, and there is a great risk of lowering the yield and reliability of chips.
本発明の目的は、生産性が向上され、信頼性の向上を図
ることができるようにした、半導体装置の突起電極の形
成方法を提供することである。An object of the present invention is to provide a method for forming protruding electrodes of a semiconductor device, which improves productivity and reliability.
課題を解決するための手段
本発明は、最上層にき成樹脂から成る層を有する半導体
回路基板上へ、逆スパツタリングを行って、前記合成樹
脂層の表面に導電性を与える工程と、
該導電性の表面を陰極として電解めっきを行う工程とを
含むことを特徴とする半導体装置の突起電極の形成方法
である。Means for Solving the Problems The present invention provides a step of performing reverse sputtering on a semiconductor circuit board having a layer made of synthetic resin as the uppermost layer to impart electrical conductivity to the surface of the synthetic resin layer; 1. A method for forming a protruding electrode for a semiconductor device, the method comprising the step of performing electrolytic plating using a solid surface as a cathode.
作 用
本発明に従えば、迩スパッタリングによって導電性を有
する最上層の合成樹脂から成る層の表面を電解めっき時
の陰極として用いることができるので、その突起電極を
電解めっきによって形成した後に、前述の先行技術に関
連して述べたバリアメタルをエツチングする工程が不要
となる。そのため突起電極の根元のオーバエンチングを
防ぐことが可能になる。Function According to the present invention, the surface of the uppermost synthetic resin layer that has conductivity by sputtering can be used as a cathode during electrolytic plating. The step of etching the barrier metal described in connection with the prior art becomes unnecessary. Therefore, it is possible to prevent over-etching of the base of the protruding electrode.
また導電性を帯びたき成樹脂から成る層の表面は、長時
間、大気中に放置しておくか、または加温することによ
って、元の電気絶縁性のある状態に戻すことができる。Further, the surface of the layer made of conductive synthetic resin can be returned to its original electrically insulating state by leaving it in the atmosphere for a long time or by heating it.
実施例
第１図は１本発明の一実施例の半導体装置におけるＡＵ
製突起電極の形成方法を説明する断面図である。シリコ
ンサブストレー１−などのような半導体基板１上にアル
ミニウムの電極バッド１２と、それを開口するように形
成されたき或崩脂、たとえばポリイミドから成る絶縁層
１３とが第１図（ａ）で示すように形成される。Embodiment FIG. 1 shows an AU in a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a method of forming a protruding electrode. As shown in FIG. 1(a), an aluminum electrode pad 12 is formed on a semiconductor substrate 1 such as a silicon substrate 1, and an insulating layer 13 made of a fat-free material, for example, polyimide, is formed to open the aluminum electrode pad 12. formed as shown.
次に第１１１Ｗ（ｂ）で示されるように、最上層の絶縁
層１３上ｌ＼逆スパツタリングを行い、さらにスパッタ
蒸着によってバリアメタル１５を形成する。逆スパツタ
リングというのは、絶縁層１３側にアルゴンＡｒイオン
をあてて、その絶縁層１３の表面の粒子をたたく手法で
ある。バリアメタル１５としては、Ｔ ｉ Ｗ ２４０
０人、その上にＡｕ１０００人が堆積されて構成される
。上述の逆スパツタリングによって、絶縁層１３の表面
１４は導電性を得る。Next, as shown in 111W(b), reverse sputtering is performed on the uppermost insulating layer 13, and a barrier metal 15 is further formed by sputter deposition. Reverse sputtering is a method in which argon Ar ions are applied to the insulating layer 13 side and particles on the surface of the insulating layer 13 are struck. As the barrier metal 15, T i W 240
0 and 1000 Au are deposited on top of it. By the above-described reverse sputtering, the surface 14 of the insulating layer 13 becomes conductive.
次に第１図（Ｃ）で示されるようにホトレジスト層１６
を塗布し、突起電極を形成する領域にパターンニングす
る。次に第１図（ｄ）で示すようにエツチングによって
Ａ ＬｌおよびＴ ｉ Ｗの層であるバリアメタル１５
を部分的に除去し、その後、ホ■・レジスト層１６を除
去する。Next, as shown in FIG. 1(C), a photoresist layer 16 is applied.
is applied and patterned in the area where the protruding electrodes are to be formed. Next, as shown in FIG. 1(d), the barrier metal 15, which is a layer of A Ll and T i W, is etched.
is partially removed, and then the resist layer 16 is removed.
第１［２Ｉ（ｅ）で示すようにホトレジスト層１（５ａ
を塗布し、突起電極が開口されるようにパターンニング
する１次に第１図（ｆ）で示すように導電性を得た絶縁
層１３の表面を陰極として電解めっきを行い、ホトレジ
スト層１６ａの開口部へＡＵ製突起電極１７を堆積して
形成する。As shown in the first [2I(e), photoresist layer 1 (5a
First, as shown in FIG. 1(f), electrolytic plating is performed using the surface of the insulating layer 13, which has obtained conductivity, as a cathode, and the photoresist layer 16a is patterned to form a protruding electrode. An AU protruding electrode 17 is deposited and formed in the opening.
そこで第１図（ｇ）で示すように、ホトレジスト層１６
ａを剥離する。Therefore, as shown in FIG. 1(g), the photoresist layer 16
Peel off a.
第１図（Ｉ〕）では２００℃で３０分間、加温し、絶縁
層１３の表面の導電性を取り除く、この導電性を取り除
くには、長時間大気中に放置してもよい
本発明の他の実施例は、第２Ｉ２Ｉに示されている。In FIG. 1 (I), the conductivity of the surface of the insulating layer 13 is removed by heating at 200° C. for 30 minutes. Another embodiment is shown in No. 2I2I.
第２図（ａ＞で示されるようにアルミニウムの電極バッ
ド１２およびＴ ｉ Ｗ −Ａ ｕの２層のバリアメタ
ル１５と、それを開口するように形成されたポリイミド
などの自戒樹脂製絶縁層１３をシリコンなどの半導体基
板１１上に形成し、第２図（ｂ）で示すようにその絶縁
層１３の表面１４に逆スパｌタリングを行う。これによ
って絶縁層１３の表面１４は導電性を得る。As shown in FIG. 2 (a), an aluminum electrode pad 12 and a two-layer barrier metal 15 of TiW-Au, and an insulating layer 13 made of a resin such as polyimide formed so as to have an opening therebetween. is formed on a semiconductor substrate 11 made of silicon or the like, and reverse sputtering is performed on the surface 14 of the insulating layer 13 as shown in FIG. 2(b).This makes the surface 14 of the insulating layer 13 conductive. .
そこで次に第２図（ｃ）で示すようにホトレジストＪ’
Ｗ１６を通し、突起電極を形成すべき領域にパターンニ
ングする０次に第２図（ｄ）で示されるように導電性を
得た絶縁層１３の表面を陰極として電解めっきを行い、
ホトレジスト層１６の開口部へＡ Ｌｌ製の突起７ｇ、
極１７を堆櫃して形成する。Then, as shown in FIG. 2(c), photoresist J'
Then, as shown in FIG. 2(d), electrolytic plating is performed using the surface of the insulating layer 13, which has obtained conductivity, as a cathode, as shown in FIG. 2(d).
A projection 7g made of A Ll to the opening of the photoresist layer 16,
A pole 17 is deposited and formed.
その決、第２図（ｅ）で示すようにホトレジスト・層１
６を剥離する０次に第２１１Ｚ（ｆ）で示すように２０
０℃で３０分間加温し、絶縁ｌ１１３の表面の導電性を
取り除く。Therefore, as shown in FIG. 2(e), the photoresist layer 1
20 as shown in 211Z(f)
The conductivity of the surface of the insulation l113 is removed by heating at 0° C. for 30 minutes.
突起電極１７は、Ａｕ製に限るものではなく、半田およ
びＣｕなどから成ってもよい。The protruding electrode 17 is not limited to being made of Au, and may be made of solder, Cu, or the like.
このような実施例によれば、突起を極を電解めっきによ
って形成した後に、バリアメタルのエツチングを行う必
要がないので、その突起電極の根元および電極バ・ンド
へのエツチング液の流れ込みを防ぐことが可能となる。According to such an embodiment, there is no need to etch the barrier metal after forming the protrusion by electrolytic plating, so that it is possible to prevent the etching solution from flowing into the base of the protrusion electrode and the electrode band. becomes possible.
したがって半導体チップである半導体基板１１を含む半
導体装置の歩留りを向上することができ、信頼性の向上
に大きく貢献することができる。Therefore, the yield of semiconductor devices including the semiconductor substrate 11, which is a semiconductor chip, can be improved, and this can greatly contribute to improved reliability.
絶縁層１３として、ポリイミドだけでなく、その他の合
成樹脂材料が用いられてもよい。As the insulating layer 13, not only polyimide but also other synthetic resin materials may be used.
発明の効果
以上のように本発明によれば、突起電極の根元のオーバ
エツチングを防ぐことができ、歩留りの向上を図って生
産性の向上を図り、また信頼性を向上することができる
。Effects of the Invention As described above, according to the present invention, over-etching of the base of the protruding electrode can be prevented, yield can be improved, productivity can be improved, and reliability can be improved.
第１１２１は本発明の一実施例の突起電極の形成方法を
示す断面図、第２図は本発明の他の実施例の突起電極の
形成方法を示す断面図、第３図は先行技術の突起＠極の
形成方法を示す断面図、第４図は先行技術において形成
された突起電極付近の断面図である。
１１・・半導体基板、１２・・・ｔＦｆ１バッド、１３
・・・絶縁層、１５・・・バリアメタル、１６．１６ａ
・・−ホトレジスト層、１７・・・突起電極1121 is a sectional view showing a method for forming a protruding electrode according to an embodiment of the present invention, FIG. 2 is a sectional view showing a method for forming a protruding electrode according to another embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view showing a method of forming the @ pole, and is a cross-sectional view of the vicinity of a protruding electrode formed in the prior art. 11...Semiconductor substrate, 12...tFf1 bad, 13
...Insulating layer, 15...Barrier metal, 16.16a
...-photoresist layer, 17... protruding electrode
Claims (1)
上へ、逆スパツタリングを行って、前記合成樹脂層の表
面に導電性を与える工程と、 該導電性の表面を陰極として電解めっきを行う工程とを
含むことを特徴とする半導体装置の突起電極の形成方法
。[Scope of Claims] A step of performing reverse sputtering on a semiconductor circuit board having a layer made of synthetic resin as the uppermost layer to impart conductivity to the surface of the synthetic resin layer, and using the conductive surface as a cathode. 1. A method for forming a protruding electrode for a semiconductor device, the method comprising the step of performing electrolytic plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1150700A JPH039526A (en) | 1989-06-06 | 1989-06-06 | Forming method of protruded electrode of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1150700A JPH039526A (en) | 1989-06-06 | 1989-06-06 | Forming method of protruded electrode of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH039526A true JPH039526A (en) | 1991-01-17 |
Family
ID=15502510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1150700A Pending JPH039526A (en) | 1989-06-06 | 1989-06-06 | Forming method of protruded electrode of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH039526A (en) |
-
1989
- 1989-06-06 JP JP1150700A patent/JPH039526A/en active Pending
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