JPH0394539A - Timing recovery circuit - Google Patents

Abstract

PURPOSE:To generate a stable timing recovery clock without jitter at all times by comparing a peak of an impulse response with two threshold levels as convergence phase object values, generating a non-control signal when the peak exists between both the threshold levels and generating a phase control signal corresponding to the quantity of a difference when the value is at the outside of both the threshold levels. CONSTITUTION:A comparator 6 compares a peak value h0 of an impulse response calculated by an impulse response arithmetic section 5 with two threshold levels hth1, hth2 as convergence phase object values and generates a non- control signal when the peak value h0 is within both the threshold levels and generates a phase control signal corresponding to the quantity of the difference when the peak value h0 exists at the outside of both the threshold levels to give the result to a master clock frequency divider 7. Thus, no phase control is implemented near the convergence phase and phase control is applied only when the convergence phase is parted. Thus, optimum phase control is always realized without jitter.

Description

[Detailed Description of the Invention] [Summary] Regarding a timing regeneration circuit that regenerates the timing used for reproducing and identifying a received signal using a received signal from a transmission line in a digital subscriber line transmission device, etc., the present invention provides constant phase control without jitter. An impulse response calculating section estimates and calculates the peak value of the impulse response from the equalization signal and the identification signal, and compares the peak value with two thresholds as convergence phase target values to calculate the peak value of the impulse response. When the peak value is between both thresholds, an uncontrolled signal is generated, and when it is outside both thresholds, a phase control signal corresponding to the magnitude of the difference is generated, or the peak value is centered around the convergence phase target value. a comparator that generates a phase control signal in which the phase control amount decreases as it approaches the convergent phase target value and increases as it moves away from the converged phase target value; It uses a master clock divider that generates a recovered clock according to the phase control signal. [Industrial Field of Application] The present invention relates to a timing regeneration circuit, and more particularly to a timing regeneration circuit that regenerates timing used for reproducing and identifying received signals using signals received from a transmission path in digital subscriber line transmission equipment and the like. It is. Fig. 5 shows an example of a receiving section of a digital subscriber line transmission device, and the line loss of the transmission line (see Fig. 6 (a))
The received signal, which has been distorted by the above, is equalized in the frequency domain by an R equalizer circuit 1 having characteristics inverse to line loss (see FIG. 6(b)), and then digitized by an A/D converter 2. This digitized signal contains residual intersymbol interference that cannot be completely equalized, and is further equalized by the decision feedback equalization circuit 3 into a signal free of intersymbol interference in the time domain. Further, the timing recovery circuit 10 supplies a sampling clock to the A/D converter 2 so as to perform A/D conversion in phase synchronization with the identification point of the equalized received signal. Devices that transmit digital signals in this way require a timing recovery circuit that can be controlled with high accuracy at all times because the transmitted clock is extracted and used as the clock for the receiving section. [Prior Art] FIG. 7 shows an example of internal control of the timing recovery circuit lO in the digital subscriber line transmission device shown in FIG. A with the sampling clock regenerated from the received signal by the timing regeneration circuit 10.
/D converter 2 generates a sample 411f*', and from this sample value rk°, decision feedback type equalization circuit 3
The intersymbol interference component generated by ``. By subtracting , we obtain a further equalized sample value r. Then, this sample value fk is reproduced by the timing reproducing circuit 10 using the judgment value a judged by the judgment device 4 having the intermediate discrimination level (±0.5>) of the eye pattern as shown in FIG. Here, an example of the decision feedback type equalization circuit 3 is shown in FIG.
The tap coefficients 01 to C. for each symbol interval are determined according to the sample error ek between the determination value a and the determination value a6. is determined, and the judgment value a. By multiplying and convolving the sample value rI1
This is what we are looking for. The timing regeneration circuit 10 also includes an impulse response calculation section (evaluation function calculation section) 5, a comparator 60, and a frequency divider 70.
The impulse response calculating section 5 calculates the impulse response h0 by calculating the following equation. This impulse response h. The comparator 6 that receives the received signal compares h0 with a threshold hth that is slightly smaller than the value of h0 "1" when the sampling phase becomes the peak of the received signal, and divides the frequency divider 70 operating with the master clock as follows. By controlling the phase of , it is possible to obtain a recovered clock that converges to the phase shown in FIG. [Problems to be Solved by the Invention] However, in such a timing regeneration circuit, since phase control is always performed based on the comparison result of the comparator 60,
Even when sampling at a phase close to the convergence phase, the phase is controlled, resulting in a problem of increased jitter. In addition, in order to reduce jitter, a protection stage method can be considered in which the comparison results are integrated and phase control is performed when the integrated value exceeds a certain value, but in this case, it is not possible to perform phase control all the time. Since a delay is multiplied by the phase control, phase deviation may easily occur depending on the frequency error of the master clock. Therefore, the present invention provides a tie-matching regeneration circuit that regenerates a tie-matching used for reproducing and identifying a received signal using a received signal from a transmission line in a digital subscriber line transmission device, etc., which can always perform phase control without jitter. The purpose is to do so. [Means for Solving the Problems] In order to achieve the above object, in the timing recovery circuit according to the present invention, as shown in principle in FIG. The peak value h0 of the impulse response obtained is compared with two thresholds h tkll h tbz as convergence phase target values, and the peak value h0
When the value is between the two threshold values, an uncontrolled signal is generated, and when the value is outside the two threshold values, a phase control signal corresponding to the magnitude of the difference is generated and applied to the mask clock frequency divider 7. ．． In addition, in the present invention, as shown in principle in FIG. 4 or more thresholds h-m*
h Lb+ *- 1+...h. 、． H...
...h L&+-R41r htk+-@ compared to,
A phase control signal in which the phase control amount decreases as it approaches the convergence phase target value and increases as it moves away from the convergence phase target value can be generated and given to the mask clock frequency divider 7a. [Function] In the present invention shown in FIG. 1, the peak value h of the impulse response
0 as the threshold value 11th+. Compare with h. <ho<
When htht, an uncontrolled signal is generated, and at other times, a phase control signal is generated that corresponds to the magnitude of the difference. A signal is generated and given to the mask clock frequency divider 7. Therefore, phase control is not performed near the convergence phase, and phase control is performed only when moving away from the convergence phase. Therefore, optimal phase control can be achieved at all times without jitter. Further, in the present invention shown in FIG. 2, the peak value h0 of the impulse response is set to the convergence phase target value h. Four or more thresholds centered around {ahtb. ．． , H. 1. ...It's hot. I.
htb. -1+...h, 1. It's hot. -7 by the comparator 6a, and in this case, h,,,,>h. 1〉・
...h, 1〉h. -1,...〉h. −−−＋、
＞h■. 1, a phase control signal whose control amount increases as it moves away from the converged phase target value htbo is generated and applied to the mask clock frequency divider 7a, depending on the magnitude relationship with these threshold values. That is, for example, hash. If so, advance the phase to the maximum and h, , > h. >h, if 1, no control, hO
<h. 1, the frequency divider 7o is controlled to delay the phase to the maximum. Therefore, the convergence phase target value is h. If it is far from , it converges quickly and the convergence phase target value h is high. Stable timing playback can be performed in the vicinity. [Embodiment] FIG. 3 shows an embodiment of the timing recovery circuit according to the present invention shown in FIG. , a counter 12 operated by a master clock, and a comparator 13 that compares the output of the selector 11 and the count value of the counter 12. Note that the selector 11 sets the frequency division ratio "l" for the counter 12.
99'', r2ooJ, r201''. Note that the frequency of the master clock f. is f+<-
It is assumed that the received signal frequency is set to 200X. In operation, what is the state of comparator 6 now? ■ha<tt
When tb■O, the phase is delayed by Δ, the 2-bit output of comparator 6 indicates one of the states from ■ to ■ above,
Correspondingly, r199J, r200J, r20
1J, r203". Therefore, ? Ru. Therefore, when the frequency division ratio is 199, a match is detected by the comparator 13 when the counter 12 counts the master clock by 199, and the counter l2 is cleared and one reproduced clock is generated. Therefore, the phase will advance by one clock compared to the normal frequency division ratio of 200, and when the frequency division ratio is 200, the phase will not change.
If the division ratio is 201, the phase will be delayed by one clock. FIG. 4 shows an embodiment of the present invention shown in FIG.
htb-t, and correspondingly, selector lla in frequency divider 7a has a division ratio rl97J of 5, the 3-bint output of comparator 6a indicates one of the states from ■ to ■ above. , and the reproduction clock is controlled in the same way as in the case of FIG. 3. [Effects of the Invention] As explained above, according to the timing recovery circuit according to the present invention, the peak of the impulse response {1 h. is compared with two dark values as convergence phase target values, and the peak value h.
When is between the two thresholds, an uncontrolled signal is generated, and when it is outside the two thresholds, a phase control signal corresponding to the magnitude of the difference is generated, or the peak value is centered around the convergence phase target value. Comparing with four or more threshold values, a phase control signal is generated in which the phase control amount becomes smaller as it approaches the convergence phase target value, and increases as it gets farther away, and is given to the master clock frequency divider. Therefore, phase control is not performed near the convergence phase, and as the clock moves away from the convergence phase, phase control is performed with greater advance or lag, making it possible to always generate a stable timing recovery clock without jitter. ．．

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 and 2 are principle block diagrams of the timing recovery circuit according to the present invention. FIG. 3 is an embodiment of the timing recovery circuit according to the present invention shown in FIG. FIG. 4 is a diagram showing an embodiment of the tying regeneration circuit according to the present invention shown in FIG. 2, and FIG. Figures 6(a) and 6(b) are diagrams showing line loss characteristics and equalization circuit characteristics, respectively, and Figure 7 is a block diagram showing an example of the structure of the circuit. FIG. 8 is a diagram showing the subscriber line transmission device, FIG. 8 is an explanatory diagram of the operation of the decision device, FIG. 9 is a diagram showing the specific structure of the decision feedback type equalization circuit, and FIG.
The figure is an explanatory diagram of the operation of the conventional example. In FIG. 1 and FIG. 2, 5... Impulse response calculation unit, 6.6a... Comparator, 7.18... Master clock frequency divider, lO... Timing recovery circuit.

Claims (2)

[Claims] (1) In a timing regeneration circuit that equalizes the received signal of the data transmission device and reproduces the timing used for reproduction and identification of the received signal from the identified signal, the peak value of the impulse response is estimated and calculated from the equalized signal and the identification signal. An impulse response calculation unit (5) compares the peak value with two threshold values as convergence phase target values, and when the peak value is between the two thresholds, generates an uncontrolled signal and outputs an uncontrolled signal that is outside the two thresholds. Sometimes, it is equipped with a comparator (6) that generates a phase control signal corresponding to the magnitude of the difference, and a master clock frequency divider (7) that generates a recovered clock according to the uncontrolled signal and the phase control signal. A timing regeneration circuit characterized by: (2) In a timing regeneration circuit that equalizes the received signal of the data transmission device and reproduces the timing used for reproducing and identifying the received signal from the identified signal, the peak value of the impulse response is estimated and calculated from the equalized signal and the identification signal. The impulse response calculation unit (5) compares the peak value with four or more threshold values centered around the convergence phase target value, and calculates that the phase control amount decreases as it approaches the convergence phase target value, and as it moves away from the convergence phase target value. Timing recovery characterized by comprising: a comparator (6a) that generates a phase control signal with a larger control amount; and a master clock frequency divider (7a) that generates a recovered clock according to the phase control amount. circuit.