JPH0394345A - Interleaved prefetching device for microprocessor - Google Patents

Abstract

PURPOSE:To improve the bus performance of a microprocessor by increasing data volume to be transferred per unit time. CONSTITUTION:The microprocessor 1 is a 32-bit microprocessor consisting of internal 32 bits and a 16-bit external data bus and its inside is constituted of three circuit parts; i.e. a bus interface unit(BIU), an instruction interpretation unit(IIU) and an instruction execution unit(EU). In the data transfer control of the microprocessor 1, many instruction fetches can be attained only by one address output to an external memory by increasing the number of bus cycle clocks constituting an instruction fetch cycle. Thereby, the data transfer volume per unit bus cycle can be increased. Thus, the bus performance of the microprocessor 1 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to microprocessors, and more particularly to improving the bus performance of microprocessors.

(Prior art) In a microcomputer, a microprocessor, which is the center of data processing, and a main memory are connected via a bus, which is a bundle of wires, and data is transferred between them via this bus. . Therefore, when trying to increase the speed of a microcomputer, the data transfer speed via this bus becomes an issue.

Here, conventional methods for increasing the speed of microcomputers have focused on how to make the memory side follow the speed without reducing the processing speed of the microprocessor. An example of such a method is to connect a microprocessor to a slow, large-capacity main memory through a fast, small-capacity cache memory so that subsequent cycles with the desired data from the main memory are connected. A cache memory method that reads out multiple pieces of data required at the same time and stores them temporarily in cache memory, or prepares multiple low-speed memory banks and accesses one memory bank by a microprocessor. A memory interleaving method is sometimes known that attempts to shorten memory access time by preparing access to another memory bank. However, such a method is merely a technique for bringing the processing speed of the memory closer to the processing speed of the microprocessor, and does not improve the processing speed of the microprocessor itself.

As a conventional method for improving the performance of a microprocessor itself, there is a method of increasing the operating speed of the microprocessor itself. An alternative is to increase the width of the bus while maintaining the same operating speed; for example, using a 32-bit bus instead of a 16-bit bus doubles the data transfer rate.

(Problem to be Solved by the Invention) However, increasing the operating speed of the microprocessor naturally requires increasing the speed of the memory, which poses a problem particularly in terms of cost. Furthermore, increasing the width of the bus inevitably requires an increase in the installation space for the bus, resulting in problems such as an increase in the mounting area and the number of components.

In view of this, an object of the present invention is to improve the amount of data that can be transferred per unit time, which is the bus performance of a microprocessor, without using expensive high-speed memory or increasing the mounting area or number of components. The goal is to increase

(Means for Solving the Problems) In order to achieve the above object, the present invention provides an interleaved system in a microprocessor equipped with a bus interface unit that performs data input/output with a plurality of external memories. A designation means is provided for designating an instruction fetch operation mode called a prefetch operation mode. When the incremental brief fetch operation mode is designated by this designation means, the address means can address M (M: 2 or more correct ) are addressed simultaneously. Further, in this operation mode, the bus cycle control means controls the interleaved mode in which the number of bus cycle clocks constituting the instruction fetch cycle from the external memory is increased by (M-1).
A prefetch cycle is generated. In this interleaved prefetch cycle, the instruction fetch means sequentially fetches instructions from M external memories addressed by the address means.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 and FIG. 2 are schematic configuration diagrams showing one embodiment of the present invention. In the figure, ■ is an integrated circuit microprocessor, which is a complementary metal monoxide semiconductor (CMO
S) process on a single silicon substrate. This microprocessor l has internal 3
2 bits, external data bus 16 bits, 32 bits
It is a microprocessor. The interior can be roughly divided into buses and
Interface unit BIU, instruction translation unit l
It consists of three circuit parts: an IU, and an instruction execution unit (EU). Bus interface unit BIU
are the brief fetch unit BIUa and the bus cycle control unit BI.
Ub, and performs input/output with the external bus. The instruction translation unit IIU translates external instruction codes into normalized instructions. The instruction execution unit t-EU executes the normalized instructions. As can be seen from the figure, each of these control units is connected to the PL
It is constructed using the A logic system. Further, as an input/output terminal directly related to the present invention, the microprocessor I of this example has a 16-bit data bus input terminal D.

~D+5 and a 29-bit address bus output terminal A. -A2m and “interleaved
One input terminal B for controlling "prefetch" operation
It is equipped with IVM and two output terminals BIVE and BIVBS.

In the data transfer control in the microprocessor I of this example, basically two clock cycles are treated as one bus cycle, and two bytes of data are transferred at a time. That is, since the data bus of the microprocessor in this example has a width of 16 bits, the theoretical limit performance is data transfer of 20 Mbytes/sec with a 20 MHz clock. However, in the "included prefetch" mode of operation in this example, 4 bytes of code can be fetched in 3 clock cycles, making it possible to effectively increase the bus bandwidth to 26 Mbytes/sec. There is. The configuration of the parts involved in this "included prefetch" operation will be explained below.

As shown in FIG. 2, the microprocessor 1 includes 16
External memories M1 and M2 of bit data width are connected. That is, address bus output terminals A, ~A2Il of microprocessor l are connected to address decoder A.
D and the address input terminal of each external memory MLM2. Two output terminals of the address decoder AD are connected to one input terminal of OR gates OR1 and OR2, respectively. Further, the output terminal BIVE of the microprocessor is connected to the other input terminal of these OR gates ORISOR2. The output terminals of the OR gates are connected to external memories M1 and M2, respectively. On the other hand, the data output terminals of these external memories M1 and M2 are
Each is connected via a 6-bit data bus to the inputs of a multiplexer MUX, the data output of which is the data input D of the microprocessor I. - Connected to DI 5. Moreover, the switching input terminal of this multiplexer MUX is connected to the terminal BIVBS of the microprocessor.

Further, an output terminal MRD of the microprocessor is connected to lead terminals of external memories M 1 and M 2 .

Next, the input terminal BIVM receives a command signal BI which instructs the "interleaved prefetch" operation mode from the outside.
VMS is now input.

The operation of interleaved briefing of instruction data from external memory will now be described with reference to FIGS. 2 and 3. As mentioned above, the bus cycle in this example consists of two clock cycles, and the two clocks of the basic bus cycle are separated from the T1 state in the first half and the T2 state in the latter half. In an instruction fetch cycle from external memory, two bytes of data are transferred at a time.

However, when the incremental prefetch command signal BIVMS input to the human power terminal BIVMS goes to a high logic level, the external memory Ml, which is controlled by the bus cycle controller of the bus interface unit,
The instruction fetch cycle from M2 is interleaved.
Switching to the prefetch cycle, the above TI, T
A TV state is added after the two states, and the instruction fetch cycle becomes an incremental prefetch cycle consisting of three bus cycles and three clocks. In this cycle, the output signal BI from the output terminal BIVE
VES switches to a high logic level and simultaneously both external memories M1, M2 are set to the enabled state. Here, the multiplexer MtlX is set on the external memory Ml side, and therefore, in read dimming in the T2 state, an instruction read from one external memory Ml side is read. Next, output terminal BIVB
A switching signal BIVBSS is output from S to multiplexer MUX, the multiplexer switches to the external memory M2 side, and the instruction on this memory M2 side is read.

In this way, in the interleaved pre-processing cycle, one bus cycle is added, so 2-byte data is transferred twice consecutively. In other words, it is possible to transfer 4 knots of data in 3 clocks of the clock cycle, which is 1
This is a rate of 0.75 clocks per byte, which is approximately a 30% improvement in data transfer performance compared to the case where one clock cycle per byte is required in a normal instruction cycle.

Note that in this example, interlibd. When a prefetch operation is performed, the brief fetch operation is performed on a 4-byte boundary (
The lower two bits of the address occur every "address Oj". If a branch instruction causes a branch to another address, only the first time, the instruction to fetch is The number of bytes changes as shown in the table below.

(Table) Lower 2 bits of branch destination address 00 --- Perform interleaved prefetch on all 4 bytes.

01' - - Interleaved prefetch is performed on only 3 bytes (1 byte is discarded).

1 0 -- Fetch 2 bytes.

(Normal fetch l times) 1l...Fetch l bytes.

(One normal fetch) Other Embodiments In the embodiments described above, a 32-bit microprocessor with a 16-bit data bus and a 29-bit address node was described as an example. The present invention is applicable to microprocessors having buses of any other number of bits. Further, unlike the above example, if there are two types of data buses, one for brieffetch and one for data, the present invention may be applied to the bus for prefetch.

Further, in the above example, two external memories are connected, but the present invention can be similarly applied to a case where three or more external memories are connected. In this case, enable three or more memories at the same time and add them to the interleaved briefing cycle.
Data transfer performance can be further improved by increasing the number of states accordingly.

(Effects of the Invention) As explained above, in the present invention, by increasing the number of bus cycle clocks constituting an instruction fetch cycle, more instruction fetches can be performed with one address output to an external memory. It makes it possible.

Therefore, according to the present invention, it is possible to increase the amount of data transferred per unit bus cycle, that is, to improve the performance of the microprocessor, compared to the case where the conventionally known instruction brieffetch operation is performed.

[Brief explanation of drawings]

1 and 2 are schematic block diagrams showing a microprocessor to which the present invention is applied and an example of the connection between this microprocessor and an external memory, respectively, and FIG. 3 is a timing diagram showing an incremental brief fetch operation in the device shown in FIG. 2. It is a chart. MU
-D11"゜゛Data input terminal BI VE, BI VB S-1 output terminal BIV
M... Explanation of input terminal symbols 1-1 Microprocessor BIU - HAS interface ●Unit BIU
a--Instruction brief fetch unit BIUb-...゜Bus cycle control unit IIU...゜゜Instruction translation unit E

Claims (1)

[Claims] In a microprocessor equipped with a bus interface unit that performs data input/output with a plurality of external memories, there is provided a designating means for designating an interleaved prefetch operation mode, and a method for specifying an interleaved prefetch operation mode. mode, one address output to the plurality of external memories causes M (M:
a positive integer of 2 or more), and in the interleaved prefetch operation mode, the number of clocks of bus cycles constituting an instruction fetch cycle from the external memory is increased by (M-1). bus cycle control means for generating an interleaved prefetch cycle, and in the interleaved prefetch cycle generated by the bus cycle control means, sequentially from the M external memories addressed by the address means; 1. An interleaved prefetch device for a microprocessor, comprising: instruction prefetch means for performing an instruction prefetch operation.